1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-tcon-top.h> 9#include <dt-bindings/reset/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 clock-latency-ns = <244144>; /* 8 32k periods */ 30 #cooling-cells = <2>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 reg = <1>; 37 enable-method = "psci"; 38 clocks = <&ccu CLK_CPUX>; 39 clock-latency-ns = <244144>; /* 8 32k periods */ 40 #cooling-cells = <2>; 41 }; 42 43 cpu2: cpu@2 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <2>; 47 enable-method = "psci"; 48 clocks = <&ccu CLK_CPUX>; 49 clock-latency-ns = <244144>; /* 8 32k periods */ 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 reg = <3>; 57 enable-method = "psci"; 58 clocks = <&ccu CLK_CPUX>; 59 clock-latency-ns = <244144>; /* 8 32k periods */ 60 #cooling-cells = <2>; 61 }; 62 }; 63 64 de: display-engine { 65 compatible = "allwinner,sun50i-h6-display-engine"; 66 allwinner,pipelines = <&mixer0>; 67 status = "disabled"; 68 }; 69 70 osc24M: osc24M_clk { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <24000000>; 74 clock-output-names = "osc24M"; 75 }; 76 77 pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-0.2"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 arm,no-tick-in-suspend; 94 interrupts = <GIC_PPI 13 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 14 97 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 11 99 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 10 101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 102 }; 103 104 soc { 105 compatible = "simple-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 bus@1000000 { 111 compatible = "allwinner,sun50i-h6-de3", 112 "allwinner,sun50i-a64-de2"; 113 reg = <0x1000000 0x400000>; 114 allwinner,sram = <&de2_sram 1>; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges = <0 0x1000000 0x400000>; 118 119 display_clocks: clock@0 { 120 compatible = "allwinner,sun50i-h6-de3-clk"; 121 reg = <0x0 0x10000>; 122 clocks = <&ccu CLK_BUS_DE>, 123 <&ccu CLK_DE>; 124 clock-names = "bus", 125 "mod"; 126 resets = <&ccu RST_BUS_DE>; 127 #clock-cells = <1>; 128 #reset-cells = <1>; 129 }; 130 131 mixer0: mixer@100000 { 132 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 133 reg = <0x100000 0x100000>; 134 clocks = <&display_clocks CLK_BUS_MIXER0>, 135 <&display_clocks CLK_MIXER0>; 136 clock-names = "bus", 137 "mod"; 138 resets = <&display_clocks RST_MIXER0>; 139 iommus = <&iommu 0>; 140 141 ports { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 mixer0_out: port@1 { 146 reg = <1>; 147 148 mixer0_out_tcon_top_mixer0: endpoint { 149 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 150 }; 151 }; 152 }; 153 }; 154 }; 155 156 video-codec-g2@1c00000 { 157 compatible = "allwinner,sun50i-h6-vpu-g2"; 158 reg = <0x01c00000 0x1000>; 159 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; 161 clock-names = "bus", "mod"; 162 resets = <&ccu RST_BUS_VP9>; 163 }; 164 165 video-codec@1c0e000 { 166 compatible = "allwinner,sun50i-h6-video-engine"; 167 reg = <0x01c0e000 0x2000>; 168 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 169 <&ccu CLK_MBUS_VE>; 170 clock-names = "ahb", "mod", "ram"; 171 resets = <&ccu RST_BUS_VE>; 172 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 173 allwinner,sram = <&ve_sram 1>; 174 iommus = <&iommu 3>; 175 }; 176 177 gpu: gpu@1800000 { 178 compatible = "allwinner,sun50i-h6-mali", 179 "arm,mali-t720"; 180 reg = <0x01800000 0x4000>; 181 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "job", "mmu", "gpu"; 185 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 186 clock-names = "core", "bus"; 187 resets = <&ccu RST_BUS_GPU>; 188 status = "disabled"; 189 }; 190 191 crypto: crypto@1904000 { 192 compatible = "allwinner,sun50i-h6-crypto"; 193 reg = <0x01904000 0x1000>; 194 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 196 clock-names = "bus", "mod", "ram"; 197 resets = <&ccu RST_BUS_CE>; 198 }; 199 200 syscon: syscon@3000000 { 201 compatible = "allwinner,sun50i-h6-system-control", 202 "allwinner,sun50i-a64-system-control"; 203 reg = <0x03000000 0x1000>; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges; 207 208 sram_c: sram@28000 { 209 compatible = "mmio-sram"; 210 reg = <0x00028000 0x1e000>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges = <0 0x00028000 0x1e000>; 214 215 de2_sram: sram-section@0 { 216 compatible = "allwinner,sun50i-h6-sram-c", 217 "allwinner,sun50i-a64-sram-c"; 218 reg = <0x0000 0x1e000>; 219 }; 220 }; 221 222 sram_c1: sram@1a00000 { 223 compatible = "mmio-sram"; 224 reg = <0x01a00000 0x200000>; 225 #address-cells = <1>; 226 #size-cells = <1>; 227 ranges = <0 0x01a00000 0x200000>; 228 229 ve_sram: sram-section@0 { 230 compatible = "allwinner,sun50i-h6-sram-c1", 231 "allwinner,sun4i-a10-sram-c1"; 232 reg = <0x000000 0x200000>; 233 }; 234 }; 235 }; 236 237 ccu: clock@3001000 { 238 compatible = "allwinner,sun50i-h6-ccu"; 239 reg = <0x03001000 0x1000>; 240 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 241 clock-names = "hosc", "losc", "iosc"; 242 #clock-cells = <1>; 243 #reset-cells = <1>; 244 }; 245 246 dma: dma-controller@3002000 { 247 compatible = "allwinner,sun50i-h6-dma"; 248 reg = <0x03002000 0x1000>; 249 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 251 clock-names = "bus", "mbus"; 252 dma-channels = <16>; 253 dma-requests = <46>; 254 resets = <&ccu RST_BUS_DMA>; 255 #dma-cells = <1>; 256 }; 257 258 msgbox: mailbox@3003000 { 259 compatible = "allwinner,sun50i-h6-msgbox", 260 "allwinner,sun6i-a31-msgbox"; 261 reg = <0x03003000 0x1000>; 262 clocks = <&ccu CLK_BUS_MSGBOX>; 263 resets = <&ccu RST_BUS_MSGBOX>; 264 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 265 #mbox-cells = <1>; 266 }; 267 268 sid: efuse@3006000 { 269 compatible = "allwinner,sun50i-h6-sid"; 270 reg = <0x03006000 0x400>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 274 ths_calibration: thermal-sensor-calibration@14 { 275 reg = <0x14 0x8>; 276 }; 277 278 cpu_speed_grade: cpu-speed-grade@1c { 279 reg = <0x1c 0x4>; 280 }; 281 }; 282 283 timer@3009000 { 284 compatible = "allwinner,sun50i-h6-timer", 285 "allwinner,sun8i-a23-timer"; 286 reg = <0x03009000 0xa0>; 287 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&osc24M>; 290 }; 291 292 watchdog: watchdog@30090a0 { 293 compatible = "allwinner,sun50i-h6-wdt", 294 "allwinner,sun6i-a31-wdt"; 295 reg = <0x030090a0 0x20>; 296 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&osc24M>; 298 /* Broken on some H6 boards */ 299 status = "disabled"; 300 }; 301 302 pwm: pwm@300a000 { 303 compatible = "allwinner,sun50i-h6-pwm"; 304 reg = <0x0300a000 0x400>; 305 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 306 clock-names = "mod", "bus"; 307 resets = <&ccu RST_BUS_PWM>; 308 #pwm-cells = <3>; 309 status = "disabled"; 310 }; 311 312 pio: pinctrl@300b000 { 313 compatible = "allwinner,sun50i-h6-pinctrl"; 314 reg = <0x0300b000 0x400>; 315 interrupt-parent = <&r_intc>; 316 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 321 clock-names = "apb", "hosc", "losc"; 322 gpio-controller; 323 #gpio-cells = <3>; 324 interrupt-controller; 325 #interrupt-cells = <3>; 326 327 ext_rgmii_pins: rgmii-pins { 328 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 329 "PD5", "PD7", "PD8", "PD9", "PD10", 330 "PD11", "PD12", "PD13", "PD19", "PD20"; 331 function = "emac"; 332 drive-strength = <40>; 333 }; 334 335 hdmi_pins: hdmi-pins { 336 pins = "PH8", "PH9", "PH10"; 337 function = "hdmi"; 338 }; 339 340 i2c0_pins: i2c0-pins { 341 pins = "PD25", "PD26"; 342 function = "i2c0"; 343 }; 344 345 i2c1_pins: i2c1-pins { 346 pins = "PH5", "PH6"; 347 function = "i2c1"; 348 }; 349 350 i2c2_pins: i2c2-pins { 351 pins = "PD23", "PD24"; 352 function = "i2c2"; 353 }; 354 355 mmc0_pins: mmc0-pins { 356 pins = "PF0", "PF1", "PF2", "PF3", 357 "PF4", "PF5"; 358 function = "mmc0"; 359 drive-strength = <30>; 360 bias-pull-up; 361 }; 362 363 /omit-if-no-ref/ 364 mmc1_pins: mmc1-pins { 365 pins = "PG0", "PG1", "PG2", "PG3", 366 "PG4", "PG5"; 367 function = "mmc1"; 368 drive-strength = <30>; 369 bias-pull-up; 370 }; 371 372 mmc2_pins: mmc2-pins { 373 pins = "PC1", "PC4", "PC5", "PC6", 374 "PC7", "PC8", "PC9", "PC10", 375 "PC11", "PC12", "PC13", "PC14"; 376 function = "mmc2"; 377 drive-strength = <30>; 378 bias-pull-up; 379 }; 380 381 /omit-if-no-ref/ 382 spi0_pins: spi0-pins { 383 pins = "PC0", "PC2", "PC3"; 384 function = "spi0"; 385 }; 386 387 /* pin shared with MMC2-CMD (eMMC) */ 388 /omit-if-no-ref/ 389 spi0_cs_pin: spi0-cs-pin { 390 pins = "PC5"; 391 function = "spi0"; 392 }; 393 394 /omit-if-no-ref/ 395 spi1_pins: spi1-pins { 396 pins = "PH4", "PH5", "PH6"; 397 function = "spi1"; 398 }; 399 400 /omit-if-no-ref/ 401 spi1_cs_pin: spi1-cs-pin { 402 pins = "PH3"; 403 function = "spi1"; 404 }; 405 406 spdif_tx_pin: spdif-tx-pin { 407 pins = "PH7"; 408 function = "spdif"; 409 }; 410 411 uart0_ph_pins: uart0-ph-pins { 412 pins = "PH0", "PH1"; 413 function = "uart0"; 414 }; 415 416 uart1_pins: uart1-pins { 417 pins = "PG6", "PG7"; 418 function = "uart1"; 419 }; 420 421 uart1_rts_cts_pins: uart1-rts-cts-pins { 422 pins = "PG8", "PG9"; 423 function = "uart1"; 424 }; 425 }; 426 427 gic: interrupt-controller@3021000 { 428 compatible = "arm,gic-400"; 429 reg = <0x03021000 0x1000>, 430 <0x03022000 0x2000>, 431 <0x03024000 0x2000>, 432 <0x03026000 0x2000>; 433 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 434 interrupt-controller; 435 #interrupt-cells = <3>; 436 }; 437 438 iommu: iommu@30f0000 { 439 compatible = "allwinner,sun50i-h6-iommu"; 440 reg = <0x030f0000 0x10000>; 441 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&ccu CLK_BUS_IOMMU>; 443 resets = <&ccu RST_BUS_IOMMU>; 444 #iommu-cells = <1>; 445 }; 446 447 mmc0: mmc@4020000 { 448 compatible = "allwinner,sun50i-h6-mmc", 449 "allwinner,sun50i-a64-mmc"; 450 reg = <0x04020000 0x1000>; 451 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 452 clock-names = "ahb", "mmc"; 453 resets = <&ccu RST_BUS_MMC0>; 454 reset-names = "ahb"; 455 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&mmc0_pins>; 458 max-frequency = <150000000>; 459 status = "disabled"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 }; 463 464 mmc1: mmc@4021000 { 465 compatible = "allwinner,sun50i-h6-mmc", 466 "allwinner,sun50i-a64-mmc"; 467 reg = <0x04021000 0x1000>; 468 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 469 clock-names = "ahb", "mmc"; 470 resets = <&ccu RST_BUS_MMC1>; 471 reset-names = "ahb"; 472 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&mmc1_pins>; 475 max-frequency = <150000000>; 476 status = "disabled"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 }; 480 481 mmc2: mmc@4022000 { 482 compatible = "allwinner,sun50i-h6-emmc", 483 "allwinner,sun50i-a64-emmc"; 484 reg = <0x04022000 0x1000>; 485 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 486 clock-names = "ahb", "mmc"; 487 resets = <&ccu RST_BUS_MMC2>; 488 reset-names = "ahb"; 489 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&mmc2_pins>; 492 max-frequency = <150000000>; 493 status = "disabled"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 }; 497 498 uart0: serial@5000000 { 499 compatible = "snps,dw-apb-uart"; 500 reg = <0x05000000 0x400>; 501 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 502 reg-shift = <2>; 503 reg-io-width = <4>; 504 clocks = <&ccu CLK_BUS_UART0>; 505 resets = <&ccu RST_BUS_UART0>; 506 status = "disabled"; 507 }; 508 509 uart1: serial@5000400 { 510 compatible = "snps,dw-apb-uart"; 511 reg = <0x05000400 0x400>; 512 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 clocks = <&ccu CLK_BUS_UART1>; 516 resets = <&ccu RST_BUS_UART1>; 517 status = "disabled"; 518 }; 519 520 uart2: serial@5000800 { 521 compatible = "snps,dw-apb-uart"; 522 reg = <0x05000800 0x400>; 523 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 524 reg-shift = <2>; 525 reg-io-width = <4>; 526 clocks = <&ccu CLK_BUS_UART2>; 527 resets = <&ccu RST_BUS_UART2>; 528 status = "disabled"; 529 }; 530 531 uart3: serial@5000c00 { 532 compatible = "snps,dw-apb-uart"; 533 reg = <0x05000c00 0x400>; 534 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 535 reg-shift = <2>; 536 reg-io-width = <4>; 537 clocks = <&ccu CLK_BUS_UART3>; 538 resets = <&ccu RST_BUS_UART3>; 539 status = "disabled"; 540 }; 541 542 i2c0: i2c@5002000 { 543 compatible = "allwinner,sun50i-h6-i2c", 544 "allwinner,sun6i-a31-i2c"; 545 reg = <0x05002000 0x400>; 546 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&ccu CLK_BUS_I2C0>; 548 resets = <&ccu RST_BUS_I2C0>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&i2c0_pins>; 551 status = "disabled"; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 }; 555 556 i2c1: i2c@5002400 { 557 compatible = "allwinner,sun50i-h6-i2c", 558 "allwinner,sun6i-a31-i2c"; 559 reg = <0x05002400 0x400>; 560 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&ccu CLK_BUS_I2C1>; 562 resets = <&ccu RST_BUS_I2C1>; 563 pinctrl-names = "default"; 564 pinctrl-0 = <&i2c1_pins>; 565 status = "disabled"; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 }; 569 570 i2c2: i2c@5002800 { 571 compatible = "allwinner,sun50i-h6-i2c", 572 "allwinner,sun6i-a31-i2c"; 573 reg = <0x05002800 0x400>; 574 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&ccu CLK_BUS_I2C2>; 576 resets = <&ccu RST_BUS_I2C2>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&i2c2_pins>; 579 status = "disabled"; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 }; 583 584 spi0: spi@5010000 { 585 compatible = "allwinner,sun50i-h6-spi", 586 "allwinner,sun8i-h3-spi"; 587 reg = <0x05010000 0x1000>; 588 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 590 clock-names = "ahb", "mod"; 591 dmas = <&dma 22>, <&dma 22>; 592 dma-names = "rx", "tx"; 593 resets = <&ccu RST_BUS_SPI0>; 594 status = "disabled"; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 }; 598 599 spi1: spi@5011000 { 600 compatible = "allwinner,sun50i-h6-spi", 601 "allwinner,sun8i-h3-spi"; 602 reg = <0x05011000 0x1000>; 603 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 605 clock-names = "ahb", "mod"; 606 dmas = <&dma 23>, <&dma 23>; 607 dma-names = "rx", "tx"; 608 resets = <&ccu RST_BUS_SPI1>; 609 status = "disabled"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 }; 613 614 emac: ethernet@5020000 { 615 compatible = "allwinner,sun50i-h6-emac", 616 "allwinner,sun50i-a64-emac"; 617 syscon = <&syscon>; 618 reg = <0x05020000 0x10000>; 619 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 620 interrupt-names = "macirq"; 621 resets = <&ccu RST_BUS_EMAC>; 622 reset-names = "stmmaceth"; 623 clocks = <&ccu CLK_BUS_EMAC>; 624 clock-names = "stmmaceth"; 625 status = "disabled"; 626 627 mdio: mdio { 628 compatible = "snps,dwmac-mdio"; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 }; 632 }; 633 634 i2s1: i2s@5091000 { 635 #sound-dai-cells = <0>; 636 compatible = "allwinner,sun50i-h6-i2s"; 637 reg = <0x05091000 0x1000>; 638 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 640 clock-names = "apb", "mod"; 641 dmas = <&dma 4>, <&dma 4>; 642 resets = <&ccu RST_BUS_I2S1>; 643 dma-names = "rx", "tx"; 644 status = "disabled"; 645 }; 646 647 spdif: spdif@5093000 { 648 #sound-dai-cells = <0>; 649 compatible = "allwinner,sun50i-h6-spdif"; 650 reg = <0x05093000 0x400>; 651 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 653 clock-names = "apb", "spdif"; 654 resets = <&ccu RST_BUS_SPDIF>; 655 dmas = <&dma 2>; 656 dma-names = "tx"; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&spdif_tx_pin>; 659 status = "disabled"; 660 }; 661 662 usb2otg: usb@5100000 { 663 compatible = "allwinner,sun50i-h6-musb", 664 "allwinner,sun8i-a33-musb"; 665 reg = <0x05100000 0x0400>; 666 clocks = <&ccu CLK_BUS_OTG>; 667 resets = <&ccu RST_BUS_OTG>; 668 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 669 interrupt-names = "mc"; 670 phys = <&usb2phy 0>; 671 phy-names = "usb"; 672 extcon = <&usb2phy 0>; 673 status = "disabled"; 674 }; 675 676 usb2phy: phy@5100400 { 677 compatible = "allwinner,sun50i-h6-usb-phy"; 678 reg = <0x05100400 0x24>, 679 <0x05101800 0x4>, 680 <0x05311800 0x4>; 681 reg-names = "phy_ctrl", 682 "pmu0", 683 "pmu3"; 684 clocks = <&ccu CLK_USB_PHY0>, 685 <&ccu CLK_USB_PHY3>; 686 clock-names = "usb0_phy", 687 "usb3_phy"; 688 resets = <&ccu RST_USB_PHY0>, 689 <&ccu RST_USB_PHY3>; 690 reset-names = "usb0_reset", 691 "usb3_reset"; 692 status = "disabled"; 693 #phy-cells = <1>; 694 }; 695 696 ehci0: usb@5101000 { 697 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 698 reg = <0x05101000 0x100>; 699 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&ccu CLK_BUS_OHCI0>, 701 <&ccu CLK_BUS_EHCI0>, 702 <&ccu CLK_USB_OHCI0>; 703 resets = <&ccu RST_BUS_OHCI0>, 704 <&ccu RST_BUS_EHCI0>; 705 phys = <&usb2phy 0>; 706 phy-names = "usb"; 707 status = "disabled"; 708 }; 709 710 ohci0: usb@5101400 { 711 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 712 reg = <0x05101400 0x100>; 713 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&ccu CLK_BUS_OHCI0>, 715 <&ccu CLK_USB_OHCI0>; 716 resets = <&ccu RST_BUS_OHCI0>; 717 phys = <&usb2phy 0>; 718 phy-names = "usb"; 719 status = "disabled"; 720 }; 721 722 dwc3: usb@5200000 { 723 compatible = "snps,dwc3"; 724 reg = <0x05200000 0x10000>; 725 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&ccu CLK_BUS_XHCI>, 727 <&ccu CLK_BUS_XHCI>, 728 <&rtc 0>; 729 clock-names = "ref", "bus_early", "suspend"; 730 resets = <&ccu RST_BUS_XHCI>; 731 /* 732 * The datasheet of the chip doesn't declare the 733 * peripheral function, and there's no boards known 734 * to have a USB Type-B port routed to the port. 735 * In addition, no one has tested the peripheral 736 * function yet. 737 * So set the dr_mode to "host" in the DTSI file. 738 */ 739 dr_mode = "host"; 740 phys = <&usb3phy>; 741 phy-names = "usb3-phy"; 742 status = "disabled"; 743 }; 744 745 usb3phy: phy@5210000 { 746 compatible = "allwinner,sun50i-h6-usb3-phy"; 747 reg = <0x5210000 0x10000>; 748 clocks = <&ccu CLK_USB_PHY1>; 749 resets = <&ccu RST_USB_PHY1>; 750 #phy-cells = <0>; 751 status = "disabled"; 752 }; 753 754 ehci3: usb@5311000 { 755 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 756 reg = <0x05311000 0x100>; 757 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&ccu CLK_BUS_OHCI3>, 759 <&ccu CLK_BUS_EHCI3>, 760 <&ccu CLK_USB_OHCI3>; 761 resets = <&ccu RST_BUS_OHCI3>, 762 <&ccu RST_BUS_EHCI3>; 763 phys = <&usb2phy 3>; 764 phy-names = "usb"; 765 status = "disabled"; 766 }; 767 768 ohci3: usb@5311400 { 769 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 770 reg = <0x05311400 0x100>; 771 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&ccu CLK_BUS_OHCI3>, 773 <&ccu CLK_USB_OHCI3>; 774 resets = <&ccu RST_BUS_OHCI3>; 775 phys = <&usb2phy 3>; 776 phy-names = "usb"; 777 status = "disabled"; 778 }; 779 780 hdmi: hdmi@6000000 { 781 compatible = "allwinner,sun50i-h6-dw-hdmi"; 782 reg = <0x06000000 0x10000>; 783 reg-io-width = <1>; 784 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 786 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 787 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 788 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 789 "hdcp-bus"; 790 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 791 reset-names = "ctrl", "hdcp"; 792 phys = <&hdmi_phy>; 793 phy-names = "phy"; 794 pinctrl-names = "default"; 795 pinctrl-0 = <&hdmi_pins>; 796 status = "disabled"; 797 798 ports { 799 #address-cells = <1>; 800 #size-cells = <0>; 801 802 hdmi_in: port@0 { 803 reg = <0>; 804 805 hdmi_in_tcon_top: endpoint { 806 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 807 }; 808 }; 809 810 hdmi_out: port@1 { 811 reg = <1>; 812 }; 813 }; 814 }; 815 816 hdmi_phy: hdmi-phy@6010000 { 817 compatible = "allwinner,sun50i-h6-hdmi-phy"; 818 reg = <0x06010000 0x10000>; 819 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 820 clock-names = "bus", "mod"; 821 resets = <&ccu RST_BUS_HDMI>; 822 reset-names = "phy"; 823 #phy-cells = <0>; 824 }; 825 826 tcon_top: tcon-top@6510000 { 827 compatible = "allwinner,sun50i-h6-tcon-top"; 828 reg = <0x06510000 0x1000>; 829 clocks = <&ccu CLK_BUS_TCON_TOP>, 830 <&ccu CLK_TCON_TV0>; 831 clock-names = "bus", 832 "tcon-tv0"; 833 clock-output-names = "tcon-top-tv0"; 834 resets = <&ccu RST_BUS_TCON_TOP>; 835 #clock-cells = <1>; 836 837 ports { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 841 tcon_top_mixer0_in: port@0 { 842 #address-cells = <1>; 843 #size-cells = <0>; 844 reg = <0>; 845 846 tcon_top_mixer0_in_mixer0: endpoint@0 { 847 reg = <0>; 848 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 849 }; 850 }; 851 852 tcon_top_mixer0_out: port@1 { 853 #address-cells = <1>; 854 #size-cells = <0>; 855 reg = <1>; 856 857 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 858 reg = <2>; 859 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 860 }; 861 }; 862 863 tcon_top_hdmi_in: port@4 { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 reg = <4>; 867 868 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 869 reg = <0>; 870 remote-endpoint = <&tcon_tv_out_tcon_top>; 871 }; 872 }; 873 874 tcon_top_hdmi_out: port@5 { 875 reg = <5>; 876 877 tcon_top_hdmi_out_hdmi: endpoint { 878 remote-endpoint = <&hdmi_in_tcon_top>; 879 }; 880 }; 881 }; 882 }; 883 884 tcon_tv: lcd-controller@6515000 { 885 compatible = "allwinner,sun50i-h6-tcon-tv", 886 "allwinner,sun8i-r40-tcon-tv"; 887 reg = <0x06515000 0x1000>; 888 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&ccu CLK_BUS_TCON_TV0>, 890 <&tcon_top CLK_TCON_TOP_TV0>; 891 clock-names = "ahb", 892 "tcon-ch1"; 893 resets = <&ccu RST_BUS_TCON_TV0>; 894 reset-names = "lcd"; 895 896 ports { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 900 tcon_tv_in: port@0 { 901 reg = <0>; 902 903 tcon_tv_in_tcon_top_mixer0: endpoint { 904 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 905 }; 906 }; 907 908 tcon_tv_out: port@1 { 909 #address-cells = <1>; 910 #size-cells = <0>; 911 reg = <1>; 912 913 tcon_tv_out_tcon_top: endpoint@1 { 914 reg = <1>; 915 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 916 }; 917 }; 918 }; 919 }; 920 921 rtc: rtc@7000000 { 922 compatible = "allwinner,sun50i-h6-rtc"; 923 reg = <0x07000000 0x400>; 924 interrupt-parent = <&r_intc>; 925 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 927 clock-output-names = "osc32k", "osc32k-out", "iosc"; 928 #clock-cells = <1>; 929 }; 930 931 r_ccu: clock@7010000 { 932 compatible = "allwinner,sun50i-h6-r-ccu"; 933 reg = <0x07010000 0x400>; 934 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 935 <&ccu CLK_PLL_PERIPH0>; 936 clock-names = "hosc", "losc", "iosc", "pll-periph"; 937 #clock-cells = <1>; 938 #reset-cells = <1>; 939 }; 940 941 r_watchdog: watchdog@7020400 { 942 compatible = "allwinner,sun50i-h6-wdt", 943 "allwinner,sun6i-a31-wdt"; 944 reg = <0x07020400 0x20>; 945 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&osc24M>; 947 }; 948 949 r_intc: interrupt-controller@7021000 { 950 compatible = "allwinner,sun50i-h6-r-intc"; 951 interrupt-controller; 952 #interrupt-cells = <3>; 953 reg = <0x07021000 0x400>; 954 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 955 }; 956 957 r_pio: pinctrl@7022000 { 958 compatible = "allwinner,sun50i-h6-r-pinctrl"; 959 reg = <0x07022000 0x400>; 960 interrupt-parent = <&r_intc>; 961 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 964 clock-names = "apb", "hosc", "losc"; 965 gpio-controller; 966 #gpio-cells = <3>; 967 interrupt-controller; 968 #interrupt-cells = <3>; 969 970 r_i2c_pins: r-i2c-pins { 971 pins = "PL0", "PL1"; 972 function = "s_i2c"; 973 }; 974 975 r_ir_rx_pin: r-ir-rx-pin { 976 pins = "PL9"; 977 function = "s_cir_rx"; 978 }; 979 980 r_rsb_pins: r-rsb-pins { 981 pins = "PL0", "PL1"; 982 function = "s_rsb"; 983 }; 984 }; 985 986 r_ir: ir@7040000 { 987 compatible = "allwinner,sun50i-h6-ir", 988 "allwinner,sun6i-a31-ir"; 989 reg = <0x07040000 0x400>; 990 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&r_ccu CLK_R_APB1_IR>, 992 <&r_ccu CLK_IR>; 993 clock-names = "apb", "ir"; 994 resets = <&r_ccu RST_R_APB1_IR>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&r_ir_rx_pin>; 997 status = "disabled"; 998 }; 999 1000 r_i2c: i2c@7081400 { 1001 compatible = "allwinner,sun50i-h6-i2c", 1002 "allwinner,sun6i-a31-i2c"; 1003 reg = <0x07081400 0x400>; 1004 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&r_ccu CLK_R_APB2_I2C>; 1006 resets = <&r_ccu RST_R_APB2_I2C>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&r_i2c_pins>; 1009 status = "disabled"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 }; 1013 1014 r_rsb: rsb@7083000 { 1015 compatible = "allwinner,sun8i-a23-rsb"; 1016 reg = <0x07083000 0x400>; 1017 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&r_ccu CLK_R_APB2_RSB>; 1019 clock-frequency = <3000000>; 1020 resets = <&r_ccu RST_R_APB2_RSB>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&r_rsb_pins>; 1023 status = "disabled"; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 }; 1027 1028 ths: thermal-sensor@5070400 { 1029 compatible = "allwinner,sun50i-h6-ths"; 1030 reg = <0x05070400 0x100>; 1031 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&ccu CLK_BUS_THS>; 1033 clock-names = "bus"; 1034 resets = <&ccu RST_BUS_THS>; 1035 nvmem-cells = <&ths_calibration>; 1036 nvmem-cell-names = "calibration"; 1037 #thermal-sensor-cells = <1>; 1038 }; 1039 }; 1040 1041 thermal-zones { 1042 cpu-thermal { 1043 polling-delay-passive = <0>; 1044 polling-delay = <0>; 1045 thermal-sensors = <&ths 0>; 1046 1047 trips { 1048 cpu_alert: cpu-alert { 1049 temperature = <85000>; 1050 hysteresis = <2000>; 1051 type = "passive"; 1052 }; 1053 1054 cpu-crit { 1055 temperature = <100000>; 1056 hysteresis = <0>; 1057 type = "critical"; 1058 }; 1059 }; 1060 1061 cooling-maps { 1062 map0 { 1063 trip = <&cpu_alert>; 1064 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1065 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1066 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1067 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1068 }; 1069 }; 1070 }; 1071 1072 gpu-thermal { 1073 polling-delay-passive = <0>; 1074 polling-delay = <0>; 1075 thermal-sensors = <&ths 1>; 1076 }; 1077 }; 1078}; 1079