xref: /freebsd/sys/contrib/device-tree/src/arm64/allwinner/sun50i-h5.dtsi (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2016 ARM Ltd.
3
4#include <arm/sunxi-h3-h5.dtsi>
5
6#include <dt-bindings/thermal/thermal.h>
7
8/ {
9	cpus {
10		#address-cells = <1>;
11		#size-cells = <0>;
12
13		cpu0: cpu@0 {
14			compatible = "arm,cortex-a53";
15			device_type = "cpu";
16			reg = <0>;
17			enable-method = "psci";
18			clocks = <&ccu CLK_CPUX>;
19			clock-latency-ns = <244144>; /* 8 32k periods */
20			#cooling-cells = <2>;
21		};
22
23		cpu1: cpu@1 {
24			compatible = "arm,cortex-a53";
25			device_type = "cpu";
26			reg = <1>;
27			enable-method = "psci";
28			clocks = <&ccu CLK_CPUX>;
29			clock-latency-ns = <244144>; /* 8 32k periods */
30			#cooling-cells = <2>;
31		};
32
33		cpu2: cpu@2 {
34			compatible = "arm,cortex-a53";
35			device_type = "cpu";
36			reg = <2>;
37			enable-method = "psci";
38			clocks = <&ccu CLK_CPUX>;
39			clock-latency-ns = <244144>; /* 8 32k periods */
40			#cooling-cells = <2>;
41		};
42
43		cpu3: cpu@3 {
44			compatible = "arm,cortex-a53";
45			device_type = "cpu";
46			reg = <3>;
47			enable-method = "psci";
48			clocks = <&ccu CLK_CPUX>;
49			clock-latency-ns = <244144>; /* 8 32k periods */
50			#cooling-cells = <2>;
51		};
52	};
53
54	pmu {
55		compatible = "arm,cortex-a53-pmu";
56		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
57			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
58			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
59			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
60		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
61	};
62
63	psci {
64		compatible = "arm,psci-0.2";
65		method = "smc";
66	};
67
68	timer {
69		compatible = "arm,armv8-timer";
70		interrupts = <GIC_PPI 13
71				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72			     <GIC_PPI 14
73				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74			     <GIC_PPI 11
75				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
76			     <GIC_PPI 10
77				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
78	};
79
80	soc {
81		syscon: system-control@1c00000 {
82			compatible = "allwinner,sun50i-h5-system-control";
83			reg = <0x01c00000 0x1000>;
84			#address-cells = <1>;
85			#size-cells = <1>;
86			ranges;
87
88			sram_c1: sram@18000 {
89				compatible = "mmio-sram";
90				reg = <0x00018000 0x1c000>;
91				#address-cells = <1>;
92				#size-cells = <1>;
93				ranges = <0 0x00018000 0x1c000>;
94
95				ve_sram: sram-section@0 {
96					compatible = "allwinner,sun50i-h5-sram-c1",
97						     "allwinner,sun4i-a10-sram-c1";
98					reg = <0x000000 0x1c000>;
99				};
100			};
101		};
102
103		video-codec@1c0e000 {
104			compatible = "allwinner,sun50i-h5-video-engine";
105			reg = <0x01c0e000 0x1000>;
106			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
107				 <&ccu CLK_DRAM_VE>;
108			clock-names = "ahb", "mod", "ram";
109			resets = <&ccu RST_BUS_VE>;
110			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
111			allwinner,sram = <&ve_sram 1>;
112		};
113
114		crypto: crypto@1c15000 {
115			compatible = "allwinner,sun50i-h5-crypto";
116			reg = <0x01c15000 0x1000>;
117			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
118			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
119			clock-names = "bus", "mod";
120			resets = <&ccu RST_BUS_CE>;
121		};
122
123		mali: gpu@1e80000 {
124			compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
125			reg = <0x01e80000 0x30000>;
126			/*
127			 * While the datasheet lists an interrupt for the
128			 * PMU, the actual silicon does not have the PMU
129			 * block. Reads all return zero, and writes are
130			 * ignored.
131			 */
132			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
133				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
134				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
135				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
136				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
137				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
138				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
139				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
140				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
141				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
142				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
143				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
144			interrupt-names = "gp",
145					  "gpmmu",
146					  "pp",
147					  "pp0",
148					  "ppmmu0",
149					  "pp1",
150					  "ppmmu1",
151					  "pp2",
152					  "ppmmu2",
153					  "pp3",
154					  "ppmmu3",
155					  "pmu";
156			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
157			clock-names = "bus", "core";
158			resets = <&ccu RST_BUS_GPU>;
159
160			assigned-clocks = <&ccu CLK_GPU>;
161			assigned-clock-rates = <384000000>;
162		};
163
164		ths: thermal-sensor@1c25000 {
165			compatible = "allwinner,sun50i-h5-ths";
166			reg = <0x01c25000 0x400>;
167			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
168			resets = <&ccu RST_BUS_THS>;
169			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
170			clock-names = "bus", "mod";
171			nvmem-cells = <&ths_calibration>;
172			nvmem-cell-names = "calibration";
173			#thermal-sensor-cells = <1>;
174		};
175	};
176
177	thermal-zones {
178		cpu_thermal: cpu-thermal {
179			polling-delay-passive = <0>;
180			polling-delay = <0>;
181			thermal-sensors = <&ths 0>;
182
183			trips {
184				cpu_hot_trip: cpu-hot {
185					temperature = <80000>;
186					hysteresis = <2000>;
187					type = "passive";
188				};
189
190				cpu_very_hot_trip: cpu-very-hot {
191					temperature = <100000>;
192					hysteresis = <0>;
193					type = "critical";
194				};
195			};
196
197			cooling-maps {
198				cpu-hot-limit {
199					trip = <&cpu_hot_trip>;
200					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
202							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
203							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
204				};
205			};
206		};
207
208		gpu_thermal {
209			polling-delay-passive = <0>;
210			polling-delay = <0>;
211			thermal-sensors = <&ths 1>;
212		};
213	};
214};
215
216&ccu {
217	compatible = "allwinner,sun50i-h5-ccu";
218};
219
220&display_clocks {
221	compatible = "allwinner,sun50i-h5-de2-clk";
222};
223
224&mmc0 {
225	compatible = "allwinner,sun50i-h5-mmc",
226		     "allwinner,sun50i-a64-mmc";
227	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
228	clock-names = "ahb", "mmc";
229};
230
231&mmc1 {
232	compatible = "allwinner,sun50i-h5-mmc",
233		     "allwinner,sun50i-a64-mmc";
234	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
235	clock-names = "ahb", "mmc";
236};
237
238&mmc2 {
239	compatible = "allwinner,sun50i-h5-emmc",
240		     "allwinner,sun50i-a64-emmc";
241	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
242	clock-names = "ahb", "mmc";
243};
244
245&pio {
246	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
247		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
248		     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
249	compatible = "allwinner,sun50i-h5-pinctrl";
250};
251
252&rtc {
253	compatible = "allwinner,sun50i-h5-rtc";
254};
255
256&sid {
257	compatible = "allwinner,sun50i-h5-sid";
258};
259