1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3 4#include <arm/sunxi-h3-h5.dtsi> 5 6#include <dt-bindings/thermal/thermal.h> 7 8/ { 9 cpus { 10 #address-cells = <1>; 11 #size-cells = <0>; 12 13 cpu0: cpu@0 { 14 compatible = "arm,cortex-a53"; 15 device_type = "cpu"; 16 reg = <0>; 17 enable-method = "psci"; 18 clocks = <&ccu CLK_CPUX>; 19 clock-latency-ns = <244144>; /* 8 32k periods */ 20 #cooling-cells = <2>; 21 }; 22 23 cpu1: cpu@1 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <1>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 clock-latency-ns = <244144>; /* 8 32k periods */ 30 #cooling-cells = <2>; 31 }; 32 33 cpu2: cpu@2 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 reg = <2>; 37 enable-method = "psci"; 38 clocks = <&ccu CLK_CPUX>; 39 clock-latency-ns = <244144>; /* 8 32k periods */ 40 #cooling-cells = <2>; 41 }; 42 43 cpu3: cpu@3 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <3>; 47 enable-method = "psci"; 48 clocks = <&ccu CLK_CPUX>; 49 clock-latency-ns = <244144>; /* 8 32k periods */ 50 #cooling-cells = <2>; 51 }; 52 }; 53 54 pmu { 55 compatible = "arm,cortex-a53-pmu"; 56 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 61 }; 62 63 psci { 64 compatible = "arm,psci-0.2"; 65 method = "smc"; 66 }; 67 68 timer { 69 compatible = "arm,armv8-timer"; 70 arm,no-tick-in-suspend; 71 interrupts = <GIC_PPI 13 72 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 14 74 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 10 78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 79 }; 80 81 soc { 82 syscon: system-control@1c00000 { 83 compatible = "allwinner,sun50i-h5-system-control"; 84 reg = <0x01c00000 0x1000>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 89 sram_c1: sram@18000 { 90 compatible = "mmio-sram"; 91 reg = <0x00018000 0x1c000>; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges = <0 0x00018000 0x1c000>; 95 96 ve_sram: sram-section@0 { 97 compatible = "allwinner,sun50i-h5-sram-c1", 98 "allwinner,sun4i-a10-sram-c1"; 99 reg = <0x000000 0x1c000>; 100 }; 101 }; 102 }; 103 104 video-codec@1c0e000 { 105 compatible = "allwinner,sun50i-h5-video-engine"; 106 reg = <0x01c0e000 0x1000>; 107 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 108 <&ccu CLK_DRAM_VE>; 109 clock-names = "ahb", "mod", "ram"; 110 resets = <&ccu RST_BUS_VE>; 111 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 112 allwinner,sram = <&ve_sram 1>; 113 }; 114 115 crypto: crypto@1c15000 { 116 compatible = "allwinner,sun50i-h5-crypto"; 117 reg = <0x01c15000 0x1000>; 118 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 120 clock-names = "bus", "mod"; 121 resets = <&ccu RST_BUS_CE>; 122 }; 123 124 deinterlace: deinterlace@1e00000 { 125 compatible = "allwinner,sun8i-h3-deinterlace"; 126 reg = <0x01e00000 0x20000>; 127 clocks = <&ccu CLK_BUS_DEINTERLACE>, 128 <&ccu CLK_DEINTERLACE>, 129 <&ccu CLK_DRAM_DEINTERLACE>; 130 clock-names = "bus", "mod", "ram"; 131 resets = <&ccu RST_BUS_DEINTERLACE>; 132 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 133 interconnects = <&mbus 9>; 134 interconnect-names = "dma-mem"; 135 }; 136 137 mali: gpu@1e80000 { 138 compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; 139 reg = <0x01e80000 0x30000>; 140 /* 141 * While the datasheet lists an interrupt for the 142 * PMU, the actual silicon does not have the PMU 143 * block. Reads all return zero, and writes are 144 * ignored. 145 */ 146 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-names = "gp", 158 "gpmmu", 159 "pp", 160 "pp0", 161 "ppmmu0", 162 "pp1", 163 "ppmmu1", 164 "pp2", 165 "ppmmu2", 166 "pp3", 167 "ppmmu3"; 168 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 169 clock-names = "bus", "core"; 170 resets = <&ccu RST_BUS_GPU>; 171 172 assigned-clocks = <&ccu CLK_GPU>; 173 assigned-clock-rates = <384000000>; 174 }; 175 176 ths: thermal-sensor@1c25000 { 177 compatible = "allwinner,sun50i-h5-ths"; 178 reg = <0x01c25000 0x400>; 179 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 180 resets = <&ccu RST_BUS_THS>; 181 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 182 clock-names = "bus", "mod"; 183 nvmem-cells = <&ths_calibration>; 184 nvmem-cell-names = "calibration"; 185 #thermal-sensor-cells = <1>; 186 }; 187 }; 188 189 thermal-zones { 190 cpu_thermal: cpu-thermal { 191 polling-delay-passive = <0>; 192 polling-delay = <0>; 193 thermal-sensors = <&ths 0>; 194 195 trips { 196 cpu_hot_trip: cpu-hot { 197 temperature = <80000>; 198 hysteresis = <2000>; 199 type = "passive"; 200 }; 201 202 cpu_very_hot_trip: cpu-very-hot { 203 temperature = <100000>; 204 hysteresis = <0>; 205 type = "critical"; 206 }; 207 }; 208 209 cooling-maps { 210 cpu-hot-limit { 211 trip = <&cpu_hot_trip>; 212 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 213 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 214 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 215 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 216 }; 217 }; 218 }; 219 220 gpu-thermal { 221 polling-delay-passive = <0>; 222 polling-delay = <0>; 223 thermal-sensors = <&ths 1>; 224 }; 225 }; 226}; 227 228&ccu { 229 compatible = "allwinner,sun50i-h5-ccu"; 230}; 231 232&display_clocks { 233 compatible = "allwinner,sun50i-h5-de2-clk"; 234}; 235 236&mbus { 237 compatible = "allwinner,sun50i-h5-mbus"; 238}; 239 240&mmc0 { 241 compatible = "allwinner,sun50i-h5-mmc", 242 "allwinner,sun50i-a64-mmc"; 243 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 244 clock-names = "ahb", "mmc"; 245}; 246 247&mmc1 { 248 compatible = "allwinner,sun50i-h5-mmc", 249 "allwinner,sun50i-a64-mmc"; 250 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 251 clock-names = "ahb", "mmc"; 252}; 253 254&mmc2 { 255 compatible = "allwinner,sun50i-h5-emmc", 256 "allwinner,sun50i-a64-emmc"; 257 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 258 clock-names = "ahb", "mmc"; 259}; 260 261&pio { 262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 265 compatible = "allwinner,sun50i-h5-pinctrl"; 266}; 267 268&rtc { 269 compatible = "allwinner,sun50i-h5-rtc"; 270}; 271 272&sid { 273 compatible = "allwinner,sun50i-h5-sid"; 274}; 275