1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-r-ccu.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/sun50i-a64-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/reset/sun8i-r-ccu.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 chosen { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 simplefb_lcd: framebuffer-lcd { 26 compatible = "allwinner,simple-framebuffer", 27 "simple-framebuffer"; 28 allwinner,pipeline = "mixer0-lcd0"; 29 clocks = <&ccu CLK_TCON0>, 30 <&display_clocks CLK_MIXER0>; 31 status = "disabled"; 32 }; 33 34 simplefb_hdmi: framebuffer-hdmi { 35 compatible = "allwinner,simple-framebuffer", 36 "simple-framebuffer"; 37 allwinner,pipeline = "mixer1-lcd1-hdmi"; 38 clocks = <&display_clocks CLK_MIXER1>, 39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40 status = "disabled"; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 reg = <0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2>; 54 clocks = <&ccu CLK_CPUX>; 55 clock-names = "cpu"; 56 #cooling-cells = <2>; 57 }; 58 59 cpu1: cpu@1 { 60 compatible = "arm,cortex-a53"; 61 device_type = "cpu"; 62 reg = <1>; 63 enable-method = "psci"; 64 next-level-cache = <&L2>; 65 clocks = <&ccu CLK_CPUX>; 66 clock-names = "cpu"; 67 #cooling-cells = <2>; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a53"; 72 device_type = "cpu"; 73 reg = <2>; 74 enable-method = "psci"; 75 next-level-cache = <&L2>; 76 clocks = <&ccu CLK_CPUX>; 77 clock-names = "cpu"; 78 #cooling-cells = <2>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 reg = <3>; 85 enable-method = "psci"; 86 next-level-cache = <&L2>; 87 clocks = <&ccu CLK_CPUX>; 88 clock-names = "cpu"; 89 #cooling-cells = <2>; 90 }; 91 92 L2: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 }; 96 }; 97 98 de: display-engine { 99 compatible = "allwinner,sun50i-a64-display-engine"; 100 allwinner,pipelines = <&mixer0>, 101 <&mixer1>; 102 status = "disabled"; 103 }; 104 105 gpu_opp_table: opp-table-gpu { 106 compatible = "operating-points-v2"; 107 108 opp-120000000 { 109 opp-hz = /bits/ 64 <120000000>; 110 }; 111 112 opp-312000000 { 113 opp-hz = /bits/ 64 <312000000>; 114 }; 115 116 opp-432000000 { 117 opp-hz = /bits/ 64 <432000000>; 118 }; 119 }; 120 121 osc24M: osc24M_clk { 122 #clock-cells = <0>; 123 compatible = "fixed-clock"; 124 clock-frequency = <24000000>; 125 clock-output-names = "osc24M"; 126 }; 127 128 osc32k: osc32k_clk { 129 #clock-cells = <0>; 130 compatible = "fixed-clock"; 131 clock-frequency = <32768>; 132 clock-output-names = "ext-osc32k"; 133 }; 134 135 pmu { 136 compatible = "arm,cortex-a53-pmu"; 137 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 141 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 142 }; 143 144 psci { 145 compatible = "arm,psci-0.2"; 146 method = "smc"; 147 }; 148 149 sound: sound { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 compatible = "simple-audio-card"; 153 simple-audio-card,name = "sun50i-a64-audio"; 154 simple-audio-card,aux-devs = <&codec_analog>; 155 simple-audio-card,routing = 156 "Left DAC", "DACL", 157 "Right DAC", "DACR", 158 "ADCL", "Left ADC", 159 "ADCR", "Right ADC"; 160 status = "disabled"; 161 162 simple-audio-card,dai-link@0 { 163 format = "i2s"; 164 frame-master = <&link0_cpu>; 165 bitclock-master = <&link0_cpu>; 166 mclk-fs = <128>; 167 168 link0_cpu: cpu { 169 sound-dai = <&dai>; 170 }; 171 172 link0_codec: codec { 173 sound-dai = <&codec 0>; 174 }; 175 }; 176 }; 177 178 timer { 179 compatible = "arm,armv8-timer"; 180 allwinner,erratum-unknown1; 181 arm,no-tick-in-suspend; 182 interrupts = <GIC_PPI 13 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 14 185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 186 <GIC_PPI 11 187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 188 <GIC_PPI 10 189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 190 }; 191 192 thermal-zones { 193 cpu_thermal: cpu0-thermal { 194 /* milliseconds */ 195 polling-delay-passive = <0>; 196 polling-delay = <0>; 197 thermal-sensors = <&ths 0>; 198 199 cooling-maps { 200 map0 { 201 trip = <&cpu_alert0>; 202 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 203 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 204 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 205 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 206 }; 207 map1 { 208 trip = <&cpu_alert1>; 209 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 212 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 213 }; 214 }; 215 216 trips { 217 cpu_alert0: cpu_alert0 { 218 /* milliCelsius */ 219 temperature = <75000>; 220 hysteresis = <2000>; 221 type = "passive"; 222 }; 223 224 cpu_alert1: cpu_alert1 { 225 /* milliCelsius */ 226 temperature = <90000>; 227 hysteresis = <2000>; 228 type = "hot"; 229 }; 230 231 cpu_crit: cpu_crit { 232 /* milliCelsius */ 233 temperature = <110000>; 234 hysteresis = <2000>; 235 type = "critical"; 236 }; 237 }; 238 }; 239 240 gpu0_thermal: gpu0-thermal { 241 /* milliseconds */ 242 polling-delay-passive = <0>; 243 polling-delay = <0>; 244 thermal-sensors = <&ths 1>; 245 }; 246 247 gpu1_thermal: gpu1-thermal { 248 /* milliseconds */ 249 polling-delay-passive = <0>; 250 polling-delay = <0>; 251 thermal-sensors = <&ths 2>; 252 }; 253 }; 254 255 soc { 256 compatible = "simple-bus"; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges; 260 261 bus@1000000 { 262 compatible = "allwinner,sun50i-a64-de2"; 263 reg = <0x1000000 0x400000>; 264 allwinner,sram = <&de2_sram 1>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges = <0 0x1000000 0x400000>; 268 269 display_clocks: clock@0 { 270 compatible = "allwinner,sun50i-a64-de2-clk"; 271 reg = <0x0 0x10000>; 272 clocks = <&ccu CLK_BUS_DE>, 273 <&ccu CLK_DE>; 274 clock-names = "bus", 275 "mod"; 276 resets = <&ccu RST_BUS_DE>; 277 #clock-cells = <1>; 278 #reset-cells = <1>; 279 }; 280 281 rotate: rotate@20000 { 282 compatible = "allwinner,sun50i-a64-de2-rotate", 283 "allwinner,sun8i-a83t-de2-rotate"; 284 reg = <0x20000 0x10000>; 285 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&display_clocks CLK_BUS_ROT>, 287 <&display_clocks CLK_ROT>; 288 clock-names = "bus", 289 "mod"; 290 resets = <&display_clocks RST_ROT>; 291 }; 292 293 mixer0: mixer@100000 { 294 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 295 reg = <0x100000 0x100000>; 296 clocks = <&display_clocks CLK_BUS_MIXER0>, 297 <&display_clocks CLK_MIXER0>; 298 clock-names = "bus", 299 "mod"; 300 resets = <&display_clocks RST_MIXER0>; 301 302 ports { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 306 mixer0_out: port@1 { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <1>; 310 311 mixer0_out_tcon0: endpoint@0 { 312 reg = <0>; 313 remote-endpoint = <&tcon0_in_mixer0>; 314 }; 315 316 mixer0_out_tcon1: endpoint@1 { 317 reg = <1>; 318 remote-endpoint = <&tcon1_in_mixer0>; 319 }; 320 }; 321 }; 322 }; 323 324 mixer1: mixer@200000 { 325 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 326 reg = <0x200000 0x100000>; 327 clocks = <&display_clocks CLK_BUS_MIXER1>, 328 <&display_clocks CLK_MIXER1>; 329 clock-names = "bus", 330 "mod"; 331 resets = <&display_clocks RST_MIXER1>; 332 333 ports { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 mixer1_out: port@1 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <1>; 341 342 mixer1_out_tcon0: endpoint@0 { 343 reg = <0>; 344 remote-endpoint = <&tcon0_in_mixer1>; 345 }; 346 347 mixer1_out_tcon1: endpoint@1 { 348 reg = <1>; 349 remote-endpoint = <&tcon1_in_mixer1>; 350 }; 351 }; 352 }; 353 }; 354 }; 355 356 syscon: syscon@1c00000 { 357 compatible = "allwinner,sun50i-a64-system-control"; 358 reg = <0x01c00000 0x1000>; 359 #address-cells = <1>; 360 #size-cells = <1>; 361 ranges; 362 363 sram_c: sram@18000 { 364 compatible = "mmio-sram"; 365 reg = <0x00018000 0x28000>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 ranges = <0 0x00018000 0x28000>; 369 370 de2_sram: sram-section@0 { 371 compatible = "allwinner,sun50i-a64-sram-c"; 372 reg = <0x0000 0x28000>; 373 }; 374 }; 375 376 sram_c1: sram@1d00000 { 377 compatible = "mmio-sram"; 378 reg = <0x01d00000 0x40000>; 379 #address-cells = <1>; 380 #size-cells = <1>; 381 ranges = <0 0x01d00000 0x40000>; 382 383 ve_sram: sram-section@0 { 384 compatible = "allwinner,sun50i-a64-sram-c1", 385 "allwinner,sun4i-a10-sram-c1"; 386 reg = <0x000000 0x40000>; 387 }; 388 }; 389 }; 390 391 dma: dma-controller@1c02000 { 392 compatible = "allwinner,sun50i-a64-dma"; 393 reg = <0x01c02000 0x1000>; 394 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&ccu CLK_BUS_DMA>; 396 dma-channels = <8>; 397 dma-requests = <27>; 398 resets = <&ccu RST_BUS_DMA>; 399 #dma-cells = <1>; 400 }; 401 402 tcon0: lcd-controller@1c0c000 { 403 compatible = "allwinner,sun50i-a64-tcon-lcd", 404 "allwinner,sun8i-a83t-tcon-lcd"; 405 reg = <0x01c0c000 0x1000>; 406 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 408 clock-names = "ahb", "tcon-ch0"; 409 clock-output-names = "tcon-pixel-clock"; 410 #clock-cells = <0>; 411 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 412 reset-names = "lcd", "lvds"; 413 414 ports { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 418 tcon0_in: port@0 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 reg = <0>; 422 423 tcon0_in_mixer0: endpoint@0 { 424 reg = <0>; 425 remote-endpoint = <&mixer0_out_tcon0>; 426 }; 427 428 tcon0_in_mixer1: endpoint@1 { 429 reg = <1>; 430 remote-endpoint = <&mixer1_out_tcon0>; 431 }; 432 }; 433 434 tcon0_out: port@1 { 435 #address-cells = <1>; 436 #size-cells = <0>; 437 reg = <1>; 438 439 tcon0_out_dsi: endpoint@1 { 440 reg = <1>; 441 remote-endpoint = <&dsi_in_tcon0>; 442 allwinner,tcon-channel = <1>; 443 }; 444 }; 445 }; 446 }; 447 448 tcon1: lcd-controller@1c0d000 { 449 compatible = "allwinner,sun50i-a64-tcon-tv", 450 "allwinner,sun8i-a83t-tcon-tv"; 451 reg = <0x01c0d000 0x1000>; 452 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 454 clock-names = "ahb", "tcon-ch1"; 455 resets = <&ccu RST_BUS_TCON1>; 456 reset-names = "lcd"; 457 458 ports { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 462 tcon1_in: port@0 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 reg = <0>; 466 467 tcon1_in_mixer0: endpoint@0 { 468 reg = <0>; 469 remote-endpoint = <&mixer0_out_tcon1>; 470 }; 471 472 tcon1_in_mixer1: endpoint@1 { 473 reg = <1>; 474 remote-endpoint = <&mixer1_out_tcon1>; 475 }; 476 }; 477 478 tcon1_out: port@1 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 reg = <1>; 482 483 tcon1_out_hdmi: endpoint@1 { 484 reg = <1>; 485 remote-endpoint = <&hdmi_in_tcon1>; 486 }; 487 }; 488 }; 489 }; 490 491 video-codec@1c0e000 { 492 compatible = "allwinner,sun50i-a64-video-engine"; 493 reg = <0x01c0e000 0x1000>; 494 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 495 <&ccu CLK_DRAM_VE>; 496 clock-names = "ahb", "mod", "ram"; 497 resets = <&ccu RST_BUS_VE>; 498 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 499 allwinner,sram = <&ve_sram 1>; 500 }; 501 502 mmc0: mmc@1c0f000 { 503 compatible = "allwinner,sun50i-a64-mmc"; 504 reg = <0x01c0f000 0x1000>; 505 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 506 clock-names = "ahb", "mmc"; 507 resets = <&ccu RST_BUS_MMC0>; 508 reset-names = "ahb"; 509 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 510 max-frequency = <150000000>; 511 status = "disabled"; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 }; 515 516 mmc1: mmc@1c10000 { 517 compatible = "allwinner,sun50i-a64-mmc"; 518 reg = <0x01c10000 0x1000>; 519 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 520 clock-names = "ahb", "mmc"; 521 resets = <&ccu RST_BUS_MMC1>; 522 reset-names = "ahb"; 523 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 524 max-frequency = <150000000>; 525 status = "disabled"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 }; 529 530 mmc2: mmc@1c11000 { 531 compatible = "allwinner,sun50i-a64-emmc"; 532 reg = <0x01c11000 0x1000>; 533 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 534 clock-names = "ahb", "mmc"; 535 resets = <&ccu RST_BUS_MMC2>; 536 reset-names = "ahb"; 537 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 538 max-frequency = <150000000>; 539 status = "disabled"; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 }; 543 544 sid: eeprom@1c14000 { 545 compatible = "allwinner,sun50i-a64-sid"; 546 reg = <0x1c14000 0x400>; 547 #address-cells = <1>; 548 #size-cells = <1>; 549 550 ths_calibration: thermal-sensor-calibration@34 { 551 reg = <0x34 0x8>; 552 }; 553 }; 554 555 crypto: crypto@1c15000 { 556 compatible = "allwinner,sun50i-a64-crypto"; 557 reg = <0x01c15000 0x1000>; 558 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 560 clock-names = "bus", "mod"; 561 resets = <&ccu RST_BUS_CE>; 562 }; 563 564 msgbox: mailbox@1c17000 { 565 compatible = "allwinner,sun50i-a64-msgbox", 566 "allwinner,sun6i-a31-msgbox"; 567 reg = <0x01c17000 0x1000>; 568 clocks = <&ccu CLK_BUS_MSGBOX>; 569 resets = <&ccu RST_BUS_MSGBOX>; 570 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 571 #mbox-cells = <1>; 572 }; 573 574 usb_otg: usb@1c19000 { 575 compatible = "allwinner,sun8i-a33-musb"; 576 reg = <0x01c19000 0x0400>; 577 clocks = <&ccu CLK_BUS_OTG>; 578 resets = <&ccu RST_BUS_OTG>; 579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 580 interrupt-names = "mc"; 581 phys = <&usbphy 0>; 582 phy-names = "usb"; 583 extcon = <&usbphy 0>; 584 dr_mode = "otg"; 585 status = "disabled"; 586 }; 587 588 usbphy: phy@1c19400 { 589 compatible = "allwinner,sun50i-a64-usb-phy"; 590 reg = <0x01c19400 0x14>, 591 <0x01c1a800 0x4>, 592 <0x01c1b800 0x4>; 593 reg-names = "phy_ctrl", 594 "pmu0", 595 "pmu1"; 596 clocks = <&ccu CLK_USB_PHY0>, 597 <&ccu CLK_USB_PHY1>; 598 clock-names = "usb0_phy", 599 "usb1_phy"; 600 resets = <&ccu RST_USB_PHY0>, 601 <&ccu RST_USB_PHY1>; 602 reset-names = "usb0_reset", 603 "usb1_reset"; 604 status = "disabled"; 605 #phy-cells = <1>; 606 }; 607 608 ehci0: usb@1c1a000 { 609 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 610 reg = <0x01c1a000 0x100>; 611 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&ccu CLK_BUS_OHCI0>, 613 <&ccu CLK_BUS_EHCI0>, 614 <&ccu CLK_USB_OHCI0>; 615 resets = <&ccu RST_BUS_OHCI0>, 616 <&ccu RST_BUS_EHCI0>; 617 phys = <&usbphy 0>; 618 phy-names = "usb"; 619 status = "disabled"; 620 }; 621 622 ohci0: usb@1c1a400 { 623 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 624 reg = <0x01c1a400 0x100>; 625 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&ccu CLK_BUS_OHCI0>, 627 <&ccu CLK_USB_OHCI0>; 628 resets = <&ccu RST_BUS_OHCI0>; 629 phys = <&usbphy 0>; 630 phy-names = "usb"; 631 status = "disabled"; 632 }; 633 634 ehci1: usb@1c1b000 { 635 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 636 reg = <0x01c1b000 0x100>; 637 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&ccu CLK_BUS_OHCI1>, 639 <&ccu CLK_BUS_EHCI1>, 640 <&ccu CLK_USB_OHCI1>; 641 resets = <&ccu RST_BUS_OHCI1>, 642 <&ccu RST_BUS_EHCI1>; 643 phys = <&usbphy 1>; 644 phy-names = "usb"; 645 status = "disabled"; 646 }; 647 648 ohci1: usb@1c1b400 { 649 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 650 reg = <0x01c1b400 0x100>; 651 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&ccu CLK_BUS_OHCI1>, 653 <&ccu CLK_USB_OHCI1>; 654 resets = <&ccu RST_BUS_OHCI1>; 655 phys = <&usbphy 1>; 656 phy-names = "usb"; 657 status = "disabled"; 658 }; 659 660 ccu: clock@1c20000 { 661 compatible = "allwinner,sun50i-a64-ccu"; 662 reg = <0x01c20000 0x400>; 663 clocks = <&osc24M>, <&rtc 0>; 664 clock-names = "hosc", "losc"; 665 #clock-cells = <1>; 666 #reset-cells = <1>; 667 }; 668 669 pio: pinctrl@1c20800 { 670 compatible = "allwinner,sun50i-a64-pinctrl"; 671 reg = <0x01c20800 0x400>; 672 interrupt-parent = <&r_intc>; 673 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 677 clock-names = "apb", "hosc", "losc"; 678 gpio-controller; 679 #gpio-cells = <3>; 680 interrupt-controller; 681 #interrupt-cells = <3>; 682 683 /omit-if-no-ref/ 684 aif2_pins: aif2-pins { 685 pins = "PB4", "PB5", "PB6", "PB7"; 686 function = "aif2"; 687 }; 688 689 /omit-if-no-ref/ 690 aif3_pins: aif3-pins { 691 pins = "PG10", "PG11", "PG12", "PG13"; 692 function = "aif3"; 693 }; 694 695 csi_pins: csi-pins { 696 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 697 "PE7", "PE8", "PE9", "PE10", "PE11"; 698 function = "csi"; 699 }; 700 701 /omit-if-no-ref/ 702 csi_mclk_pin: csi-mclk-pin { 703 pins = "PE1"; 704 function = "csi"; 705 }; 706 707 i2c0_pins: i2c0-pins { 708 pins = "PH0", "PH1"; 709 function = "i2c0"; 710 }; 711 712 i2c1_pins: i2c1-pins { 713 pins = "PH2", "PH3"; 714 function = "i2c1"; 715 }; 716 717 i2c2_pins: i2c2-pins { 718 pins = "PE14", "PE15"; 719 function = "i2c2"; 720 }; 721 722 /omit-if-no-ref/ 723 lcd_rgb666_pins: lcd-rgb666-pins { 724 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 725 "PD5", "PD6", "PD7", "PD8", "PD9", 726 "PD10", "PD11", "PD12", "PD13", 727 "PD14", "PD15", "PD16", "PD17", 728 "PD18", "PD19", "PD20", "PD21"; 729 function = "lcd0"; 730 }; 731 732 mmc0_pins: mmc0-pins { 733 pins = "PF0", "PF1", "PF2", "PF3", 734 "PF4", "PF5"; 735 function = "mmc0"; 736 drive-strength = <30>; 737 bias-pull-up; 738 }; 739 740 mmc1_pins: mmc1-pins { 741 pins = "PG0", "PG1", "PG2", "PG3", 742 "PG4", "PG5"; 743 function = "mmc1"; 744 drive-strength = <30>; 745 bias-pull-up; 746 }; 747 748 mmc2_pins: mmc2-pins { 749 pins = "PC5", "PC6", "PC8", "PC9", 750 "PC10","PC11", "PC12", "PC13", 751 "PC14", "PC15", "PC16"; 752 function = "mmc2"; 753 drive-strength = <30>; 754 bias-pull-up; 755 }; 756 757 mmc2_ds_pin: mmc2-ds-pin { 758 pins = "PC1"; 759 function = "mmc2"; 760 drive-strength = <30>; 761 bias-pull-up; 762 }; 763 764 pwm_pin: pwm-pin { 765 pins = "PD22"; 766 function = "pwm"; 767 }; 768 769 rmii_pins: rmii-pins { 770 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 771 "PD18", "PD19", "PD20", "PD22", "PD23"; 772 function = "emac"; 773 drive-strength = <40>; 774 }; 775 776 rgmii_pins: rgmii-pins { 777 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 778 "PD13", "PD15", "PD16", "PD17", "PD18", 779 "PD19", "PD20", "PD21", "PD22", "PD23"; 780 function = "emac"; 781 drive-strength = <40>; 782 }; 783 784 spdif_tx_pin: spdif-tx-pin { 785 pins = "PH8"; 786 function = "spdif"; 787 }; 788 789 spi0_pins: spi0-pins { 790 pins = "PC0", "PC1", "PC2", "PC3"; 791 function = "spi0"; 792 }; 793 794 spi1_pins: spi1-pins { 795 pins = "PD0", "PD1", "PD2", "PD3"; 796 function = "spi1"; 797 }; 798 799 uart0_pb_pins: uart0-pb-pins { 800 pins = "PB8", "PB9"; 801 function = "uart0"; 802 }; 803 804 uart1_pins: uart1-pins { 805 pins = "PG6", "PG7"; 806 function = "uart1"; 807 }; 808 809 uart1_rts_cts_pins: uart1-rts-cts-pins { 810 pins = "PG8", "PG9"; 811 function = "uart1"; 812 }; 813 814 uart2_pins: uart2-pins { 815 pins = "PB0", "PB1"; 816 function = "uart2"; 817 }; 818 819 uart3_pins: uart3-pins { 820 pins = "PD0", "PD1"; 821 function = "uart3"; 822 }; 823 824 uart4_pins: uart4-pins { 825 pins = "PD2", "PD3"; 826 function = "uart4"; 827 }; 828 829 uart4_rts_cts_pins: uart4-rts-cts-pins { 830 pins = "PD4", "PD5"; 831 function = "uart4"; 832 }; 833 }; 834 835 timer@1c20c00 { 836 compatible = "allwinner,sun50i-a64-timer", 837 "allwinner,sun8i-a23-timer"; 838 reg = <0x01c20c00 0xa0>; 839 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&osc24M>; 842 }; 843 844 wdt0: watchdog@1c20ca0 { 845 compatible = "allwinner,sun50i-a64-wdt", 846 "allwinner,sun6i-a31-wdt"; 847 reg = <0x01c20ca0 0x20>; 848 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&osc24M>; 850 }; 851 852 spdif: spdif@1c21000 { 853 #sound-dai-cells = <0>; 854 compatible = "allwinner,sun50i-a64-spdif", 855 "allwinner,sun8i-h3-spdif"; 856 reg = <0x01c21000 0x400>; 857 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 859 resets = <&ccu RST_BUS_SPDIF>; 860 clock-names = "apb", "spdif"; 861 dmas = <&dma 2>; 862 dma-names = "tx"; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&spdif_tx_pin>; 865 status = "disabled"; 866 }; 867 868 lradc: lradc@1c21800 { 869 compatible = "allwinner,sun50i-a64-lradc", 870 "allwinner,sun8i-a83t-r-lradc"; 871 reg = <0x01c21800 0x400>; 872 interrupt-parent = <&r_intc>; 873 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 874 status = "disabled"; 875 }; 876 877 i2s0: i2s@1c22000 { 878 #sound-dai-cells = <0>; 879 compatible = "allwinner,sun50i-a64-i2s", 880 "allwinner,sun8i-h3-i2s"; 881 reg = <0x01c22000 0x400>; 882 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 884 clock-names = "apb", "mod"; 885 resets = <&ccu RST_BUS_I2S0>; 886 dma-names = "rx", "tx"; 887 dmas = <&dma 3>, <&dma 3>; 888 status = "disabled"; 889 }; 890 891 i2s1: i2s@1c22400 { 892 #sound-dai-cells = <0>; 893 compatible = "allwinner,sun50i-a64-i2s", 894 "allwinner,sun8i-h3-i2s"; 895 reg = <0x01c22400 0x400>; 896 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 898 clock-names = "apb", "mod"; 899 resets = <&ccu RST_BUS_I2S1>; 900 dma-names = "rx", "tx"; 901 dmas = <&dma 4>, <&dma 4>; 902 status = "disabled"; 903 }; 904 905 i2s2: i2s@1c22800 { 906 #sound-dai-cells = <0>; 907 compatible = "allwinner,sun50i-a64-i2s", 908 "allwinner,sun8i-h3-i2s"; 909 reg = <0x01c22800 0x400>; 910 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 912 clock-names = "apb", "mod"; 913 resets = <&ccu RST_BUS_I2S2>; 914 dma-names = "rx", "tx"; 915 dmas = <&dma 27>, <&dma 27>; 916 status = "disabled"; 917 }; 918 919 dai: dai@1c22c00 { 920 #sound-dai-cells = <0>; 921 compatible = "allwinner,sun50i-a64-codec-i2s"; 922 reg = <0x01c22c00 0x200>; 923 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 925 clock-names = "apb", "mod"; 926 resets = <&ccu RST_BUS_CODEC>; 927 dmas = <&dma 15>, <&dma 15>; 928 dma-names = "rx", "tx"; 929 status = "disabled"; 930 }; 931 932 codec: codec@1c22e00 { 933 #sound-dai-cells = <1>; 934 compatible = "allwinner,sun50i-a64-codec", 935 "allwinner,sun8i-a33-codec"; 936 reg = <0x01c22e00 0x600>; 937 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 939 clock-names = "bus", "mod"; 940 status = "disabled"; 941 }; 942 943 ths: thermal-sensor@1c25000 { 944 compatible = "allwinner,sun50i-a64-ths"; 945 reg = <0x01c25000 0x100>; 946 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 947 clock-names = "bus", "mod"; 948 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 949 resets = <&ccu RST_BUS_THS>; 950 nvmem-cells = <&ths_calibration>; 951 nvmem-cell-names = "calibration"; 952 #thermal-sensor-cells = <1>; 953 }; 954 955 uart0: serial@1c28000 { 956 compatible = "snps,dw-apb-uart"; 957 reg = <0x01c28000 0x400>; 958 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 959 reg-shift = <2>; 960 reg-io-width = <4>; 961 clocks = <&ccu CLK_BUS_UART0>; 962 resets = <&ccu RST_BUS_UART0>; 963 status = "disabled"; 964 }; 965 966 uart1: serial@1c28400 { 967 compatible = "snps,dw-apb-uart"; 968 reg = <0x01c28400 0x400>; 969 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 970 reg-shift = <2>; 971 reg-io-width = <4>; 972 clocks = <&ccu CLK_BUS_UART1>; 973 resets = <&ccu RST_BUS_UART1>; 974 status = "disabled"; 975 }; 976 977 uart2: serial@1c28800 { 978 compatible = "snps,dw-apb-uart"; 979 reg = <0x01c28800 0x400>; 980 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 981 reg-shift = <2>; 982 reg-io-width = <4>; 983 clocks = <&ccu CLK_BUS_UART2>; 984 resets = <&ccu RST_BUS_UART2>; 985 status = "disabled"; 986 }; 987 988 uart3: serial@1c28c00 { 989 compatible = "snps,dw-apb-uart"; 990 reg = <0x01c28c00 0x400>; 991 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 992 reg-shift = <2>; 993 reg-io-width = <4>; 994 clocks = <&ccu CLK_BUS_UART3>; 995 resets = <&ccu RST_BUS_UART3>; 996 status = "disabled"; 997 }; 998 999 uart4: serial@1c29000 { 1000 compatible = "snps,dw-apb-uart"; 1001 reg = <0x01c29000 0x400>; 1002 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1003 reg-shift = <2>; 1004 reg-io-width = <4>; 1005 clocks = <&ccu CLK_BUS_UART4>; 1006 resets = <&ccu RST_BUS_UART4>; 1007 status = "disabled"; 1008 }; 1009 1010 i2c0: i2c@1c2ac00 { 1011 compatible = "allwinner,sun6i-a31-i2c"; 1012 reg = <0x01c2ac00 0x400>; 1013 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&ccu CLK_BUS_I2C0>; 1015 resets = <&ccu RST_BUS_I2C0>; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&i2c0_pins>; 1018 status = "disabled"; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 }; 1022 1023 i2c1: i2c@1c2b000 { 1024 compatible = "allwinner,sun6i-a31-i2c"; 1025 reg = <0x01c2b000 0x400>; 1026 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&ccu CLK_BUS_I2C1>; 1028 resets = <&ccu RST_BUS_I2C1>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&i2c1_pins>; 1031 status = "disabled"; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 }; 1035 1036 i2c2: i2c@1c2b400 { 1037 compatible = "allwinner,sun6i-a31-i2c"; 1038 reg = <0x01c2b400 0x400>; 1039 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&ccu CLK_BUS_I2C2>; 1041 resets = <&ccu RST_BUS_I2C2>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&i2c2_pins>; 1044 status = "disabled"; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 }; 1048 1049 spi0: spi@1c68000 { 1050 compatible = "allwinner,sun8i-h3-spi"; 1051 reg = <0x01c68000 0x1000>; 1052 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1054 clock-names = "ahb", "mod"; 1055 dmas = <&dma 23>, <&dma 23>; 1056 dma-names = "rx", "tx"; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&spi0_pins>; 1059 resets = <&ccu RST_BUS_SPI0>; 1060 status = "disabled"; 1061 num-cs = <1>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 }; 1065 1066 spi1: spi@1c69000 { 1067 compatible = "allwinner,sun8i-h3-spi"; 1068 reg = <0x01c69000 0x1000>; 1069 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1071 clock-names = "ahb", "mod"; 1072 dmas = <&dma 24>, <&dma 24>; 1073 dma-names = "rx", "tx"; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&spi1_pins>; 1076 resets = <&ccu RST_BUS_SPI1>; 1077 status = "disabled"; 1078 num-cs = <1>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 }; 1082 1083 emac: ethernet@1c30000 { 1084 compatible = "allwinner,sun50i-a64-emac"; 1085 syscon = <&syscon>; 1086 reg = <0x01c30000 0x10000>; 1087 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1088 interrupt-names = "macirq"; 1089 resets = <&ccu RST_BUS_EMAC>; 1090 reset-names = "stmmaceth"; 1091 clocks = <&ccu CLK_BUS_EMAC>; 1092 clock-names = "stmmaceth"; 1093 status = "disabled"; 1094 1095 mdio: mdio { 1096 compatible = "snps,dwmac-mdio"; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 }; 1100 }; 1101 1102 mali: gpu@1c40000 { 1103 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 1104 reg = <0x01c40000 0x10000>; 1105 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1112 interrupt-names = "gp", 1113 "gpmmu", 1114 "pp0", 1115 "ppmmu0", 1116 "pp1", 1117 "ppmmu1", 1118 "pmu"; 1119 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 1120 clock-names = "bus", "core"; 1121 resets = <&ccu RST_BUS_GPU>; 1122 operating-points-v2 = <&gpu_opp_table>; 1123 }; 1124 1125 gic: interrupt-controller@1c81000 { 1126 compatible = "arm,gic-400"; 1127 reg = <0x01c81000 0x1000>, 1128 <0x01c82000 0x2000>, 1129 <0x01c84000 0x2000>, 1130 <0x01c86000 0x2000>; 1131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1132 interrupt-controller; 1133 #interrupt-cells = <3>; 1134 }; 1135 1136 pwm: pwm@1c21400 { 1137 compatible = "allwinner,sun50i-a64-pwm", 1138 "allwinner,sun5i-a13-pwm"; 1139 reg = <0x01c21400 0x400>; 1140 clocks = <&osc24M>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&pwm_pin>; 1143 #pwm-cells = <3>; 1144 status = "disabled"; 1145 }; 1146 1147 mbus: dram-controller@1c62000 { 1148 compatible = "allwinner,sun50i-a64-mbus"; 1149 reg = <0x01c62000 0x1000>, 1150 <0x01c63000 0x1000>; 1151 reg-names = "mbus", "dram"; 1152 clocks = <&ccu CLK_MBUS>, 1153 <&ccu CLK_DRAM>, 1154 <&ccu CLK_BUS_DRAM>; 1155 clock-names = "mbus", "dram", "bus"; 1156 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1157 #address-cells = <1>; 1158 #size-cells = <1>; 1159 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1160 #interconnect-cells = <1>; 1161 }; 1162 1163 csi: csi@1cb0000 { 1164 compatible = "allwinner,sun50i-a64-csi"; 1165 reg = <0x01cb0000 0x1000>; 1166 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&ccu CLK_BUS_CSI>, 1168 <&ccu CLK_CSI_SCLK>, 1169 <&ccu CLK_DRAM_CSI>; 1170 clock-names = "bus", "mod", "ram"; 1171 resets = <&ccu RST_BUS_CSI>; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&csi_pins>; 1174 status = "disabled"; 1175 }; 1176 1177 dsi: dsi@1ca0000 { 1178 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1179 reg = <0x01ca0000 0x1000>; 1180 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1182 resets = <&ccu RST_BUS_MIPI_DSI>; 1183 phys = <&dphy>; 1184 phy-names = "dphy"; 1185 status = "disabled"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 1189 port { 1190 dsi_in_tcon0: endpoint { 1191 remote-endpoint = <&tcon0_out_dsi>; 1192 }; 1193 }; 1194 }; 1195 1196 dphy: d-phy@1ca1000 { 1197 compatible = "allwinner,sun50i-a64-mipi-dphy", 1198 "allwinner,sun6i-a31-mipi-dphy"; 1199 reg = <0x01ca1000 0x1000>; 1200 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1201 <&ccu CLK_DSI_DPHY>; 1202 clock-names = "bus", "mod"; 1203 resets = <&ccu RST_BUS_MIPI_DSI>; 1204 status = "disabled"; 1205 #phy-cells = <0>; 1206 }; 1207 1208 deinterlace: deinterlace@1e00000 { 1209 compatible = "allwinner,sun50i-a64-deinterlace", 1210 "allwinner,sun8i-h3-deinterlace"; 1211 reg = <0x01e00000 0x20000>; 1212 clocks = <&ccu CLK_BUS_DEINTERLACE>, 1213 <&ccu CLK_DEINTERLACE>, 1214 <&ccu CLK_DRAM_DEINTERLACE>; 1215 clock-names = "bus", "mod", "ram"; 1216 resets = <&ccu RST_BUS_DEINTERLACE>; 1217 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1218 interconnects = <&mbus 9>; 1219 interconnect-names = "dma-mem"; 1220 }; 1221 1222 hdmi: hdmi@1ee0000 { 1223 compatible = "allwinner,sun50i-a64-dw-hdmi", 1224 "allwinner,sun8i-a83t-dw-hdmi"; 1225 reg = <0x01ee0000 0x10000>; 1226 reg-io-width = <1>; 1227 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1229 <&ccu CLK_HDMI>, <&rtc 0>; 1230 clock-names = "iahb", "isfr", "tmds", "cec"; 1231 resets = <&ccu RST_BUS_HDMI1>; 1232 reset-names = "ctrl"; 1233 phys = <&hdmi_phy>; 1234 phy-names = "phy"; 1235 status = "disabled"; 1236 1237 ports { 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 1241 hdmi_in: port@0 { 1242 reg = <0>; 1243 1244 hdmi_in_tcon1: endpoint { 1245 remote-endpoint = <&tcon1_out_hdmi>; 1246 }; 1247 }; 1248 1249 hdmi_out: port@1 { 1250 reg = <1>; 1251 }; 1252 }; 1253 }; 1254 1255 hdmi_phy: hdmi-phy@1ef0000 { 1256 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1257 reg = <0x01ef0000 0x10000>; 1258 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1259 <&ccu CLK_PLL_VIDEO0>; 1260 clock-names = "bus", "mod", "pll-0"; 1261 resets = <&ccu RST_BUS_HDMI0>; 1262 reset-names = "phy"; 1263 #phy-cells = <0>; 1264 }; 1265 1266 rtc: rtc@1f00000 { 1267 compatible = "allwinner,sun50i-a64-rtc", 1268 "allwinner,sun8i-h3-rtc"; 1269 reg = <0x01f00000 0x400>; 1270 interrupt-parent = <&r_intc>; 1271 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1273 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1274 clocks = <&osc32k>; 1275 #clock-cells = <1>; 1276 }; 1277 1278 r_intc: interrupt-controller@1f00c00 { 1279 compatible = "allwinner,sun50i-a64-r-intc", 1280 "allwinner,sun6i-a31-r-intc"; 1281 interrupt-controller; 1282 #interrupt-cells = <3>; 1283 reg = <0x01f00c00 0x400>; 1284 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1285 }; 1286 1287 r_ccu: clock@1f01400 { 1288 compatible = "allwinner,sun50i-a64-r-ccu"; 1289 reg = <0x01f01400 0x100>; 1290 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1291 <&ccu CLK_PLL_PERIPH0>; 1292 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1293 #clock-cells = <1>; 1294 #reset-cells = <1>; 1295 }; 1296 1297 codec_analog: codec-analog@1f015c0 { 1298 compatible = "allwinner,sun50i-a64-codec-analog"; 1299 reg = <0x01f015c0 0x4>; 1300 status = "disabled"; 1301 }; 1302 1303 r_i2c: i2c@1f02400 { 1304 compatible = "allwinner,sun50i-a64-i2c", 1305 "allwinner,sun6i-a31-i2c"; 1306 reg = <0x01f02400 0x400>; 1307 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&r_ccu CLK_APB0_I2C>; 1309 resets = <&r_ccu RST_APB0_I2C>; 1310 status = "disabled"; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 }; 1314 1315 r_ir: ir@1f02000 { 1316 compatible = "allwinner,sun50i-a64-ir", 1317 "allwinner,sun6i-a31-ir"; 1318 reg = <0x01f02000 0x400>; 1319 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1320 clock-names = "apb", "ir"; 1321 resets = <&r_ccu RST_APB0_IR>; 1322 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&r_ir_rx_pin>; 1325 status = "disabled"; 1326 }; 1327 1328 r_pwm: pwm@1f03800 { 1329 compatible = "allwinner,sun50i-a64-pwm", 1330 "allwinner,sun5i-a13-pwm"; 1331 reg = <0x01f03800 0x400>; 1332 clocks = <&osc24M>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&r_pwm_pin>; 1335 #pwm-cells = <3>; 1336 status = "disabled"; 1337 }; 1338 1339 r_pio: pinctrl@1f02c00 { 1340 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1341 reg = <0x01f02c00 0x400>; 1342 interrupt-parent = <&r_intc>; 1343 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1344 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1345 clock-names = "apb", "hosc", "losc"; 1346 gpio-controller; 1347 #gpio-cells = <3>; 1348 interrupt-controller; 1349 #interrupt-cells = <3>; 1350 1351 r_i2c_pl89_pins: r-i2c-pl89-pins { 1352 pins = "PL8", "PL9"; 1353 function = "s_i2c"; 1354 }; 1355 1356 r_ir_rx_pin: r-ir-rx-pin { 1357 pins = "PL11"; 1358 function = "s_cir_rx"; 1359 }; 1360 1361 r_pwm_pin: r-pwm-pin { 1362 pins = "PL10"; 1363 function = "s_pwm"; 1364 }; 1365 1366 r_rsb_pins: r-rsb-pins { 1367 pins = "PL0", "PL1"; 1368 function = "s_rsb"; 1369 }; 1370 }; 1371 1372 r_rsb: rsb@1f03400 { 1373 compatible = "allwinner,sun8i-a23-rsb"; 1374 reg = <0x01f03400 0x400>; 1375 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&r_ccu 6>; 1377 clock-frequency = <3000000>; 1378 resets = <&r_ccu 2>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&r_rsb_pins>; 1381 status = "disabled"; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 }; 1385 }; 1386}; 1387