1&l4_abe { /* 0x40100000 */ 2 compatible = "ti,omap4-l4-abe", "simple-pm-bus"; 3 reg = <0x40100000 0x400>, 4 <0x40100400 0x400>; 5 reg-names = "la", "ap"; 6 power-domains = <&prm_abe>; 7 /* OMAP4_L4_ABE_CLKCTRL is read-only */ 8 #address-cells = <1>; 9 #size-cells = <1>; 10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ 11 <0x49000000 0x49000000 0x100000>; 12 segment@0 { /* 0x40100000 */ 13 compatible = "simple-pm-bus"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = 17 /* CPU to L4 ABE mapping */ 18 <0x00000000 0x00000000 0x000400>, /* ap 0 */ 19 <0x00000400 0x00000400 0x000400>, /* ap 1 */ 20 <0x00022000 0x00022000 0x001000>, /* ap 2 */ 21 <0x00023000 0x00023000 0x001000>, /* ap 3 */ 22 <0x00024000 0x00024000 0x001000>, /* ap 4 */ 23 <0x00025000 0x00025000 0x001000>, /* ap 5 */ 24 <0x00026000 0x00026000 0x001000>, /* ap 6 */ 25 <0x00027000 0x00027000 0x001000>, /* ap 7 */ 26 <0x00028000 0x00028000 0x001000>, /* ap 8 */ 27 <0x00029000 0x00029000 0x001000>, /* ap 9 */ 28 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ 29 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ 30 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ 31 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ 32 <0x00030000 0x00030000 0x001000>, /* ap 14 */ 33 <0x00031000 0x00031000 0x001000>, /* ap 15 */ 34 <0x00032000 0x00032000 0x001000>, /* ap 16 */ 35 <0x00033000 0x00033000 0x001000>, /* ap 17 */ 36 <0x00038000 0x00038000 0x001000>, /* ap 18 */ 37 <0x00039000 0x00039000 0x001000>, /* ap 19 */ 38 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ 39 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ 40 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ 41 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ 42 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ 43 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ 44 <0x00080000 0x00080000 0x010000>, /* ap 26 */ 45 <0x00080000 0x00080000 0x001000>, /* ap 27 */ 46 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ 47 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ 48 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ 49 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ 50 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ 51 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ 52 53 /* L3 to L4 ABE mapping */ 54 <0x49000000 0x49000000 0x000400>, /* ap 0 */ 55 <0x49000400 0x49000400 0x000400>, /* ap 1 */ 56 <0x49022000 0x49022000 0x001000>, /* ap 2 */ 57 <0x49023000 0x49023000 0x001000>, /* ap 3 */ 58 <0x49024000 0x49024000 0x001000>, /* ap 4 */ 59 <0x49025000 0x49025000 0x001000>, /* ap 5 */ 60 <0x49026000 0x49026000 0x001000>, /* ap 6 */ 61 <0x49027000 0x49027000 0x001000>, /* ap 7 */ 62 <0x49028000 0x49028000 0x001000>, /* ap 8 */ 63 <0x49029000 0x49029000 0x001000>, /* ap 9 */ 64 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ 65 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ 66 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ 67 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ 68 <0x49030000 0x49030000 0x001000>, /* ap 14 */ 69 <0x49031000 0x49031000 0x001000>, /* ap 15 */ 70 <0x49032000 0x49032000 0x001000>, /* ap 16 */ 71 <0x49033000 0x49033000 0x001000>, /* ap 17 */ 72 <0x49038000 0x49038000 0x001000>, /* ap 18 */ 73 <0x49039000 0x49039000 0x001000>, /* ap 19 */ 74 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ 75 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ 76 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ 77 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ 78 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ 79 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ 80 <0x49080000 0x49080000 0x010000>, /* ap 26 */ 81 <0x49080000 0x49080000 0x001000>, /* ap 27 */ 82 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ 83 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ 84 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ 85 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ 86 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ 87 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ 88 89 target-module@22000 { /* 0x40122000, ap 2 02.0 */ 90 compatible = "ti,sysc-omap2", "ti,sysc"; 91 reg = <0x2208c 0x4>; 92 reg-names = "sysc"; 93 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 94 SYSC_OMAP2_ENAWAKEUP | 95 SYSC_OMAP2_SOFTRESET)>; 96 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 97 <SYSC_IDLE_NO>, 98 <SYSC_IDLE_SMART>; 99 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 100 clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; 101 clock-names = "fck"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0x0 0x22000 0x1000>, 105 <0x49022000 0x49022000 0x1000>; 106 107 mcbsp1: mcbsp@0 { 108 compatible = "ti,omap4-mcbsp"; 109 reg = <0x0 0xff>, /* MPU private access */ 110 <0x49022000 0xff>; /* L3 Interconnect */ 111 reg-names = "mpu", "dma"; 112 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 113 interrupt-names = "common"; 114 ti,buffer-size = <128>; 115 dmas = <&sdma 33>, 116 <&sdma 34>; 117 dma-names = "tx", "rx"; 118 status = "disabled"; 119 }; 120 }; 121 122 target-module@24000 { /* 0x40124000, ap 4 04.0 */ 123 compatible = "ti,sysc-omap2", "ti,sysc"; 124 reg = <0x2408c 0x4>; 125 reg-names = "sysc"; 126 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 127 SYSC_OMAP2_ENAWAKEUP | 128 SYSC_OMAP2_SOFTRESET)>; 129 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 130 <SYSC_IDLE_NO>, 131 <SYSC_IDLE_SMART>; 132 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 133 clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; 134 clock-names = "fck"; 135 #address-cells = <1>; 136 #size-cells = <1>; 137 ranges = <0x0 0x24000 0x1000>, 138 <0x49024000 0x49024000 0x1000>; 139 140 mcbsp2: mcbsp@0 { 141 compatible = "ti,omap4-mcbsp"; 142 reg = <0x0 0xff>, /* MPU private access */ 143 <0x49024000 0xff>; /* L3 Interconnect */ 144 reg-names = "mpu", "dma"; 145 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-names = "common"; 147 ti,buffer-size = <128>; 148 dmas = <&sdma 17>, 149 <&sdma 18>; 150 dma-names = "tx", "rx"; 151 status = "disabled"; 152 }; 153 }; 154 155 target-module@26000 { /* 0x40126000, ap 6 06.0 */ 156 compatible = "ti,sysc-omap2", "ti,sysc"; 157 reg = <0x2608c 0x4>; 158 reg-names = "sysc"; 159 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 160 SYSC_OMAP2_ENAWAKEUP | 161 SYSC_OMAP2_SOFTRESET)>; 162 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 163 <SYSC_IDLE_NO>, 164 <SYSC_IDLE_SMART>; 165 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 166 clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; 167 clock-names = "fck"; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0x0 0x26000 0x1000>, 171 <0x49026000 0x49026000 0x1000>; 172 173 mcbsp3: mcbsp@0 { 174 compatible = "ti,omap4-mcbsp"; 175 reg = <0x0 0xff>, /* MPU private access */ 176 <0x49026000 0xff>; /* L3 Interconnect */ 177 reg-names = "mpu", "dma"; 178 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 179 interrupt-names = "common"; 180 ti,buffer-size = <128>; 181 dmas = <&sdma 19>, 182 <&sdma 20>; 183 dma-names = "tx", "rx"; 184 status = "disabled"; 185 }; 186 }; 187 188 target-module@28000 { /* 0x40128000, ap 8 08.0 */ 189 /* 0x4012a000, ap 10 0a.0 */ 190 compatible = "ti,sysc-mcasp", "ti,sysc"; 191 reg = <0x28000 0x4>, 192 <0x28004 0x4>; 193 reg-names = "rev", "sysc"; 194 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 195 <SYSC_IDLE_NO>, 196 <SYSC_IDLE_SMART>; 197 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 198 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; 199 clock-names = "fck"; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 ranges = <0x0 0x28000 0x1000>, 203 <0x49028000 0x49028000 0x1000>, 204 <0x2000 0x2a000 0x1000>, 205 <0x4902a000 0x4902a000 0x1000>; 206 207 mcasp0: mcasp@0 { 208 compatible = "ti,omap4-mcasp-audio"; 209 reg = <0x0 0x2000>, 210 <0x4902a000 0x1000>; /* L3 data port */ 211 reg-names = "mpu","dat"; 212 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-names = "tx"; 214 dmas = <&sdma 8>; 215 dma-names = "tx"; 216 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; 217 clock-names = "fck"; 218 op-mode = <1>; /* MCASP_DIT_MODE */ 219 serial-dir = < 1 >; /* 1 TX serializers */ 220 status = "disabled"; 221 }; 222 }; 223 224 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ 225 compatible = "ti,sysc-omap4", "ti,sysc"; 226 reg = <0x2e000 0x4>, 227 <0x2e010 0x4>; 228 reg-names = "rev", "sysc"; 229 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 230 SYSC_OMAP4_SOFTRESET)>; 231 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 232 <SYSC_IDLE_NO>, 233 <SYSC_IDLE_SMART>, 234 <SYSC_IDLE_SMART_WKUP>; 235 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 236 clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; 237 clock-names = "fck"; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 ranges = <0x0 0x2e000 0x1000>, 241 <0x4902e000 0x4902e000 0x1000>; 242 243 dmic: dmic@0 { 244 compatible = "ti,omap4-dmic"; 245 reg = <0x0 0x7f>, /* MPU private access */ 246 <0x4902e000 0x7f>; /* L3 Interconnect */ 247 reg-names = "mpu", "dma"; 248 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 249 dmas = <&sdma 67>; 250 dma-names = "up_link"; 251 status = "disabled"; 252 }; 253 }; 254 255 target-module@30000 { /* 0x40130000, ap 14 0e.0 */ 256 compatible = "ti,sysc-omap2", "ti,sysc"; 257 reg = <0x30000 0x4>, 258 <0x30010 0x4>, 259 <0x30014 0x4>; 260 reg-names = "rev", "sysc", "syss"; 261 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 262 SYSC_OMAP2_SOFTRESET)>; 263 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 264 <SYSC_IDLE_NO>, 265 <SYSC_IDLE_SMART>, 266 <SYSC_IDLE_SMART_WKUP>; 267 ti,syss-mask = <1>; 268 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 269 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; 270 clock-names = "fck"; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges = <0x0 0x30000 0x1000>, 274 <0x49030000 0x49030000 0x1000>; 275 276 wdt3: wdt@0 { 277 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 278 reg = <0x0 0x80>; 279 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 280 }; 281 }; 282 283 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ 284 compatible = "ti,sysc-omap4", "ti,sysc"; 285 reg = <0x32000 0x4>, 286 <0x32010 0x4>; 287 reg-names = "rev", "sysc"; 288 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 289 SYSC_OMAP4_SOFTRESET)>; 290 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 291 <SYSC_IDLE_NO>, 292 <SYSC_IDLE_SMART>, 293 <SYSC_IDLE_SMART_WKUP>; 294 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 295 clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; 296 clock-names = "fck"; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 ranges = <0x0 0x32000 0x1000>, 300 <0x49032000 0x49032000 0x1000>; 301 302 /* Must be only enabled for boards with pdmclk wired */ 303 status = "disabled"; 304 305 mcpdm: mcpdm@0 { 306 compatible = "ti,omap4-mcpdm"; 307 reg = <0x0 0x7f>, /* MPU private access */ 308 <0x49032000 0x7f>; /* L3 Interconnect */ 309 reg-names = "mpu", "dma"; 310 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 311 dmas = <&sdma 65>, 312 <&sdma 66>; 313 dma-names = "up_link", "dn_link"; 314 }; 315 }; 316 317 target-module@38000 { /* 0x40138000, ap 18 12.0 */ 318 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 319 reg = <0x38000 0x4>, 320 <0x38010 0x4>; 321 reg-names = "rev", "sysc"; 322 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 323 SYSC_OMAP4_SOFTRESET)>; 324 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 325 <SYSC_IDLE_NO>, 326 <SYSC_IDLE_SMART>, 327 <SYSC_IDLE_SMART_WKUP>; 328 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 329 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; 330 clock-names = "fck"; 331 #address-cells = <1>; 332 #size-cells = <1>; 333 ranges = <0x0 0x38000 0x1000>, 334 <0x49038000 0x49038000 0x1000>; 335 336 timer5: timer@0 { 337 compatible = "ti,omap4430-timer"; 338 reg = <0x00000000 0x80>, 339 <0x49038000 0x80>; 340 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>, 341 <&syc_clk_div_ck>; 342 clock-names = "fck", "timer_sys_ck"; 343 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 344 ti,timer-dsp; 345 }; 346 }; 347 348 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ 349 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 350 reg = <0x3a000 0x4>, 351 <0x3a010 0x4>; 352 reg-names = "rev", "sysc"; 353 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 354 SYSC_OMAP4_SOFTRESET)>; 355 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 356 <SYSC_IDLE_NO>, 357 <SYSC_IDLE_SMART>, 358 <SYSC_IDLE_SMART_WKUP>; 359 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 360 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; 361 clock-names = "fck"; 362 #address-cells = <1>; 363 #size-cells = <1>; 364 ranges = <0x0 0x3a000 0x1000>, 365 <0x4903a000 0x4903a000 0x1000>; 366 367 timer6: timer@0 { 368 compatible = "ti,omap4430-timer"; 369 reg = <0x00000000 0x80>, 370 <0x4903a000 0x80>; 371 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>, 372 <&syc_clk_div_ck>; 373 clock-names = "fck", "timer_sys_ck"; 374 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 375 ti,timer-dsp; 376 }; 377 }; 378 379 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ 380 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 381 reg = <0x3c000 0x4>, 382 <0x3c010 0x4>; 383 reg-names = "rev", "sysc"; 384 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 385 SYSC_OMAP4_SOFTRESET)>; 386 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 387 <SYSC_IDLE_NO>, 388 <SYSC_IDLE_SMART>, 389 <SYSC_IDLE_SMART_WKUP>; 390 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 391 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; 392 clock-names = "fck"; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 ranges = <0x0 0x3c000 0x1000>, 396 <0x4903c000 0x4903c000 0x1000>; 397 398 timer7: timer@0 { 399 compatible = "ti,omap4430-timer"; 400 reg = <0x00000000 0x80>, 401 <0x4903c000 0x80>; 402 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>, 403 <&syc_clk_div_ck>; 404 clock-names = "fck", "timer_sys_ck"; 405 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 406 ti,timer-dsp; 407 }; 408 }; 409 410 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ 411 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 412 reg = <0x3e000 0x4>, 413 <0x3e010 0x4>; 414 reg-names = "rev", "sysc"; 415 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 416 SYSC_OMAP4_SOFTRESET)>; 417 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 418 <SYSC_IDLE_NO>, 419 <SYSC_IDLE_SMART>, 420 <SYSC_IDLE_SMART_WKUP>; 421 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 422 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; 423 clock-names = "fck"; 424 #address-cells = <1>; 425 #size-cells = <1>; 426 ranges = <0x0 0x3e000 0x1000>, 427 <0x4903e000 0x4903e000 0x1000>; 428 429 timer8: timer@0 { 430 compatible = "ti,omap4430-timer"; 431 reg = <0x00000000 0x80>, 432 <0x4903e000 0x80>; 433 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>, 434 <&syc_clk_div_ck>; 435 clock-names = "fck", "timer_sys_ck"; 436 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 437 ti,timer-pwm; 438 ti,timer-dsp; 439 }; 440 }; 441 442 target-module@80000 { /* 0x40180000, ap 26 1a.0 */ 443 compatible = "ti,sysc"; 444 status = "disabled"; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 ranges = <0x0 0x80000 0x10000>, 448 <0x49080000 0x49080000 0x10000>; 449 }; 450 451 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ 452 compatible = "ti,sysc"; 453 status = "disabled"; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 ranges = <0x0 0xa0000 0x10000>, 457 <0x490a0000 0x490a0000 0x10000>; 458 }; 459 460 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ 461 compatible = "ti,sysc"; 462 status = "disabled"; 463 #address-cells = <1>; 464 #size-cells = <1>; 465 ranges = <0x0 0xc0000 0x10000>, 466 <0x490c0000 0x490c0000 0x10000>; 467 }; 468 469 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ 470 compatible = "ti,sysc-omap4", "ti,sysc"; 471 reg = <0xf1000 0x4>, 472 <0xf1010 0x4>; 473 reg-names = "rev", "sysc"; 474 ti,sysc-midle = <SYSC_IDLE_FORCE>, 475 <SYSC_IDLE_NO>, 476 <SYSC_IDLE_SMART>, 477 <SYSC_IDLE_SMART_WKUP>; 478 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 479 <SYSC_IDLE_NO>, 480 <SYSC_IDLE_SMART>; 481 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 482 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; 483 clock-names = "fck"; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 ranges = <0x0 0xf1000 0x1000>, 487 <0x490f1000 0x490f1000 0x1000>; 488 489 /* 490 * No child device binding or driver in mainline. 491 * See Android tree and related upstreaming efforts 492 * for the old driver. 493 */ 494 }; 495 }; 496}; 497 498