1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for OMAP3 clock data 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 */ 7&prm_clocks { 8 virt_16_8m_ck: virt_16_8m_ck { 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-frequency = <16800000>; 12 }; 13 14 osc_sys_ck: osc_sys_ck@d40 { 15 #clock-cells = <0>; 16 compatible = "ti,mux-clock"; 17 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; 18 reg = <0x0d40>; 19 }; 20 21 sys_ck: sys_ck@1270 { 22 #clock-cells = <0>; 23 compatible = "ti,divider-clock"; 24 clocks = <&osc_sys_ck>; 25 ti,bit-shift = <6>; 26 ti,max-div = <3>; 27 reg = <0x1270>; 28 ti,index-starts-at-one; 29 }; 30 31 sys_clkout1: sys_clkout1@d70 { 32 #clock-cells = <0>; 33 compatible = "ti,gate-clock"; 34 clocks = <&osc_sys_ck>; 35 reg = <0x0d70>; 36 ti,bit-shift = <7>; 37 }; 38 39 dpll3_x2_ck: dpll3_x2_ck { 40 #clock-cells = <0>; 41 compatible = "fixed-factor-clock"; 42 clocks = <&dpll3_ck>; 43 clock-mult = <2>; 44 clock-div = <1>; 45 }; 46 47 dpll3_m2x2_ck: dpll3_m2x2_ck { 48 #clock-cells = <0>; 49 compatible = "fixed-factor-clock"; 50 clocks = <&dpll3_m2_ck>; 51 clock-mult = <2>; 52 clock-div = <1>; 53 }; 54 55 dpll4_x2_ck: dpll4_x2_ck { 56 #clock-cells = <0>; 57 compatible = "fixed-factor-clock"; 58 clocks = <&dpll4_ck>; 59 clock-mult = <2>; 60 clock-div = <1>; 61 }; 62 63 corex2_fck: corex2_fck { 64 #clock-cells = <0>; 65 compatible = "fixed-factor-clock"; 66 clocks = <&dpll3_m2x2_ck>; 67 clock-mult = <1>; 68 clock-div = <1>; 69 }; 70 71 wkup_l4_ick: wkup_l4_ick { 72 #clock-cells = <0>; 73 compatible = "fixed-factor-clock"; 74 clocks = <&sys_ck>; 75 clock-mult = <1>; 76 clock-div = <1>; 77 }; 78}; 79 80&scm_clocks { 81 /* CONTROL_DEVCONF1 */ 82 clock@68 { 83 compatible = "ti,clksel"; 84 reg = <0x68>; 85 #clock-cells = <2>; 86 #address-cells = <0>; 87 88 mcbsp5_mux_fck: clock-mcbsp5-mux-fck { 89 #clock-cells = <0>; 90 compatible = "ti,composite-mux-clock"; 91 clock-output-names = "mcbsp5_mux_fck"; 92 clocks = <&core_96m_fck>, <&mcbsp_clks>; 93 ti,bit-shift = <4>; 94 }; 95 96 mcbsp3_mux_fck: clock-mcbsp3-mux-fck { 97 #clock-cells = <0>; 98 compatible = "ti,composite-mux-clock"; 99 clock-output-names = "mcbsp3_mux_fck"; 100 clocks = <&per_96m_fck>, <&mcbsp_clks>; 101 }; 102 103 mcbsp4_mux_fck: clock-mcbsp4-mux-fck { 104 #clock-cells = <0>; 105 compatible = "ti,composite-mux-clock"; 106 clock-output-names = "mcbsp4_mux_fck"; 107 clocks = <&per_96m_fck>, <&mcbsp_clks>; 108 ti,bit-shift = <2>; 109 }; 110 }; 111 112 mcbsp5_fck: mcbsp5_fck { 113 #clock-cells = <0>; 114 compatible = "ti,composite-clock"; 115 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; 116 }; 117 118 /* CONTROL_DEVCONF0 */ 119 clock@4 { 120 compatible = "ti,clksel"; 121 reg = <0x4>; 122 #clock-cells = <2>; 123 #address-cells = <0>; 124 125 mcbsp1_mux_fck: clock-mcbsp1-mux-fck { 126 #clock-cells = <0>; 127 compatible = "ti,composite-mux-clock"; 128 clock-output-names = "mcbsp1_mux_fck"; 129 clocks = <&core_96m_fck>, <&mcbsp_clks>; 130 ti,bit-shift = <2>; 131 }; 132 133 mcbsp2_mux_fck: clock-mcbsp2-mux-fck { 134 #clock-cells = <0>; 135 compatible = "ti,composite-mux-clock"; 136 clock-output-names = "mcbsp2_mux_fck"; 137 clocks = <&per_96m_fck>, <&mcbsp_clks>; 138 ti,bit-shift = <6>; 139 }; 140 }; 141 142 mcbsp1_fck: mcbsp1_fck { 143 #clock-cells = <0>; 144 compatible = "ti,composite-clock"; 145 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; 146 }; 147 148 mcbsp2_fck: mcbsp2_fck { 149 #clock-cells = <0>; 150 compatible = "ti,composite-clock"; 151 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; 152 }; 153 154 mcbsp3_fck: mcbsp3_fck { 155 #clock-cells = <0>; 156 compatible = "ti,composite-clock"; 157 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; 158 }; 159 160 mcbsp4_fck: mcbsp4_fck { 161 #clock-cells = <0>; 162 compatible = "ti,composite-clock"; 163 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; 164 }; 165}; 166&cm_clocks { 167 dummy_apb_pclk: dummy_apb_pclk { 168 #clock-cells = <0>; 169 compatible = "fixed-clock"; 170 clock-frequency = <0x0>; 171 }; 172 173 omap_32k_fck: omap_32k_fck { 174 #clock-cells = <0>; 175 compatible = "fixed-clock"; 176 clock-frequency = <32768>; 177 }; 178 179 virt_12m_ck: virt_12m_ck { 180 #clock-cells = <0>; 181 compatible = "fixed-clock"; 182 clock-frequency = <12000000>; 183 }; 184 185 virt_13m_ck: virt_13m_ck { 186 #clock-cells = <0>; 187 compatible = "fixed-clock"; 188 clock-frequency = <13000000>; 189 }; 190 191 virt_19200000_ck: virt_19200000_ck { 192 #clock-cells = <0>; 193 compatible = "fixed-clock"; 194 clock-frequency = <19200000>; 195 }; 196 197 virt_26000000_ck: virt_26000000_ck { 198 #clock-cells = <0>; 199 compatible = "fixed-clock"; 200 clock-frequency = <26000000>; 201 }; 202 203 virt_38_4m_ck: virt_38_4m_ck { 204 #clock-cells = <0>; 205 compatible = "fixed-clock"; 206 clock-frequency = <38400000>; 207 }; 208 209 dpll4_ck: dpll4_ck@d00 { 210 #clock-cells = <0>; 211 compatible = "ti,omap3-dpll-per-clock"; 212 clocks = <&sys_ck>, <&sys_ck>; 213 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; 214 }; 215 216 dpll4_m2_ck: dpll4_m2_ck@d48 { 217 #clock-cells = <0>; 218 compatible = "ti,divider-clock"; 219 clocks = <&dpll4_ck>; 220 ti,max-div = <63>; 221 reg = <0x0d48>; 222 ti,index-starts-at-one; 223 }; 224 225 dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { 226 #clock-cells = <0>; 227 compatible = "fixed-factor-clock"; 228 clocks = <&dpll4_m2_ck>; 229 clock-mult = <2>; 230 clock-div = <1>; 231 }; 232 233 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { 234 #clock-cells = <0>; 235 compatible = "ti,gate-clock"; 236 clocks = <&dpll4_m2x2_mul_ck>; 237 ti,bit-shift = <0x1b>; 238 reg = <0x0d00>; 239 ti,set-bit-to-disable; 240 }; 241 242 omap_96m_alwon_fck: omap_96m_alwon_fck { 243 #clock-cells = <0>; 244 compatible = "fixed-factor-clock"; 245 clocks = <&dpll4_m2x2_ck>; 246 clock-mult = <1>; 247 clock-div = <1>; 248 }; 249 250 dpll3_ck: dpll3_ck@d00 { 251 #clock-cells = <0>; 252 compatible = "ti,omap3-dpll-core-clock"; 253 clocks = <&sys_ck>, <&sys_ck>; 254 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; 255 }; 256 257 /* CM_CLKSEL1_EMU */ 258 clock@1140 { 259 compatible = "ti,clksel"; 260 reg = <0x1140>; 261 #clock-cells = <2>; 262 #address-cells = <0>; 263 264 dpll3_m3_ck: clock-dpll3-m3 { 265 #clock-cells = <0>; 266 compatible = "ti,divider-clock"; 267 clock-output-names = "dpll3_m3_ck"; 268 clocks = <&dpll3_ck>; 269 ti,bit-shift = <16>; 270 ti,max-div = <31>; 271 ti,index-starts-at-one; 272 }; 273 274 dpll4_m6_ck: clock-dpll4-m6 { 275 #clock-cells = <0>; 276 compatible = "ti,divider-clock"; 277 clock-output-names = "dpll4_m6_ck"; 278 clocks = <&dpll4_ck>; 279 ti,bit-shift = <24>; 280 ti,max-div = <63>; 281 ti,index-starts-at-one; 282 }; 283 284 emu_src_mux_ck: clock-emu-src-mux { 285 #clock-cells = <0>; 286 compatible = "ti,mux-clock"; 287 clock-output-names = "emu_src_mux_ck"; 288 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; 289 }; 290 291 pclk_fck: clock-pclk-fck { 292 #clock-cells = <0>; 293 compatible = "ti,divider-clock"; 294 clock-output-names = "pclk_fck"; 295 clocks = <&emu_src_ck>; 296 ti,bit-shift = <8>; 297 ti,max-div = <7>; 298 ti,index-starts-at-one; 299 }; 300 301 pclkx2_fck: clock-pclkx2-fck { 302 #clock-cells = <0>; 303 compatible = "ti,divider-clock"; 304 clock-output-names = "pclkx2_fck"; 305 clocks = <&emu_src_ck>; 306 ti,bit-shift = <6>; 307 ti,max-div = <3>; 308 ti,index-starts-at-one; 309 }; 310 311 atclk_fck: clock-atclk-fck { 312 #clock-cells = <0>; 313 compatible = "ti,divider-clock"; 314 clock-output-names = "atclk_fck"; 315 clocks = <&emu_src_ck>; 316 ti,bit-shift = <4>; 317 ti,max-div = <3>; 318 ti,index-starts-at-one; 319 }; 320 321 traceclk_src_fck: clock-traceclk-src-fck { 322 #clock-cells = <0>; 323 compatible = "ti,mux-clock"; 324 clock-output-names = "traceclk_src_fck"; 325 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; 326 ti,bit-shift = <2>; 327 }; 328 329 traceclk_fck: clock-traceclk-fck { 330 #clock-cells = <0>; 331 compatible = "ti,divider-clock"; 332 clock-output-names = "traceclk_fck"; 333 clocks = <&traceclk_src_fck>; 334 ti,bit-shift = <11>; 335 ti,max-div = <7>; 336 ti,index-starts-at-one; 337 }; 338 }; 339 340 dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { 341 #clock-cells = <0>; 342 compatible = "fixed-factor-clock"; 343 clocks = <&dpll3_m3_ck>; 344 clock-mult = <2>; 345 clock-div = <1>; 346 }; 347 348 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { 349 #clock-cells = <0>; 350 compatible = "ti,gate-clock"; 351 clocks = <&dpll3_m3x2_mul_ck>; 352 ti,bit-shift = <0xc>; 353 reg = <0x0d00>; 354 ti,set-bit-to-disable; 355 }; 356 357 emu_core_alwon_ck: emu_core_alwon_ck { 358 #clock-cells = <0>; 359 compatible = "fixed-factor-clock"; 360 clocks = <&dpll3_m3x2_ck>; 361 clock-mult = <1>; 362 clock-div = <1>; 363 }; 364 365 sys_altclk: sys_altclk { 366 #clock-cells = <0>; 367 compatible = "fixed-clock"; 368 clock-frequency = <0x0>; 369 }; 370 371 mcbsp_clks: mcbsp_clks { 372 #clock-cells = <0>; 373 compatible = "fixed-clock"; 374 clock-frequency = <0x0>; 375 }; 376 377 core_ck: core_ck { 378 #clock-cells = <0>; 379 compatible = "fixed-factor-clock"; 380 clocks = <&dpll3_m2_ck>; 381 clock-mult = <1>; 382 clock-div = <1>; 383 }; 384 385 dpll1_fck: dpll1_fck@940 { 386 #clock-cells = <0>; 387 compatible = "ti,divider-clock"; 388 clocks = <&core_ck>; 389 ti,bit-shift = <19>; 390 ti,max-div = <7>; 391 reg = <0x0940>; 392 ti,index-starts-at-one; 393 }; 394 395 dpll1_ck: dpll1_ck@904 { 396 #clock-cells = <0>; 397 compatible = "ti,omap3-dpll-clock"; 398 clocks = <&sys_ck>, <&dpll1_fck>; 399 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; 400 }; 401 402 dpll1_x2_ck: dpll1_x2_ck { 403 #clock-cells = <0>; 404 compatible = "fixed-factor-clock"; 405 clocks = <&dpll1_ck>; 406 clock-mult = <2>; 407 clock-div = <1>; 408 }; 409 410 dpll1_x2m2_ck: dpll1_x2m2_ck@944 { 411 #clock-cells = <0>; 412 compatible = "ti,divider-clock"; 413 clocks = <&dpll1_x2_ck>; 414 ti,max-div = <31>; 415 reg = <0x0944>; 416 ti,index-starts-at-one; 417 }; 418 419 cm_96m_fck: cm_96m_fck { 420 #clock-cells = <0>; 421 compatible = "fixed-factor-clock"; 422 clocks = <&omap_96m_alwon_fck>; 423 clock-mult = <1>; 424 clock-div = <1>; 425 }; 426 427 /* CM_CLKSEL1_PLL */ 428 clock@d40 { 429 compatible = "ti,clksel"; 430 reg = <0xd40>; 431 #clock-cells = <2>; 432 #address-cells = <0>; 433 434 dpll3_m2_ck: clock-dpll3-m2 { 435 #clock-cells = <0>; 436 compatible = "ti,divider-clock"; 437 clock-output-names = "dpll3_m2_ck"; 438 clocks = <&dpll3_ck>; 439 ti,bit-shift = <27>; 440 ti,max-div = <31>; 441 ti,index-starts-at-one; 442 }; 443 444 omap_96m_fck: clock-omap-96m-fck { 445 #clock-cells = <0>; 446 compatible = "ti,mux-clock"; 447 clock-output-names = "omap_96m_fck"; 448 clocks = <&cm_96m_fck>, <&sys_ck>; 449 ti,bit-shift = <6>; 450 }; 451 452 omap_54m_fck: clock-omap-54m-fck { 453 #clock-cells = <0>; 454 compatible = "ti,mux-clock"; 455 clock-output-names = "omap_54m_fck"; 456 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; 457 ti,bit-shift = <5>; 458 }; 459 460 omap_48m_fck: clock-omap-48m-fck { 461 #clock-cells = <0>; 462 compatible = "ti,mux-clock"; 463 clock-output-names = "omap_48m_fck"; 464 clocks = <&cm_96m_d2_fck>, <&sys_altclk>; 465 ti,bit-shift = <3>; 466 }; 467 }; 468 469 /* CM_CLKSEL_DSS */ 470 clock@e40 { 471 compatible = "ti,clksel"; 472 reg = <0xe40>; 473 #clock-cells = <2>; 474 #address-cells = <0>; 475 476 dpll4_m3_ck: clock-dpll4-m3 { 477 #clock-cells = <0>; 478 compatible = "ti,divider-clock"; 479 clock-output-names = "dpll4_m3_ck"; 480 clocks = <&dpll4_ck>; 481 ti,bit-shift = <8>; 482 ti,max-div = <32>; 483 ti,index-starts-at-one; 484 }; 485 486 dpll4_m4_ck: clock-dpll4-m4 { 487 #clock-cells = <0>; 488 compatible = "ti,divider-clock"; 489 clock-output-names = "dpll4_m4_ck"; 490 clocks = <&dpll4_ck>; 491 ti,max-div = <16>; 492 ti,index-starts-at-one; 493 }; 494 }; 495 496 dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { 497 #clock-cells = <0>; 498 compatible = "fixed-factor-clock"; 499 clocks = <&dpll4_m3_ck>; 500 clock-mult = <2>; 501 clock-div = <1>; 502 }; 503 504 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { 505 #clock-cells = <0>; 506 compatible = "ti,gate-clock"; 507 clocks = <&dpll4_m3x2_mul_ck>; 508 ti,bit-shift = <0x1c>; 509 reg = <0x0d00>; 510 ti,set-bit-to-disable; 511 }; 512 513 cm_96m_d2_fck: cm_96m_d2_fck { 514 #clock-cells = <0>; 515 compatible = "fixed-factor-clock"; 516 clocks = <&cm_96m_fck>; 517 clock-mult = <1>; 518 clock-div = <2>; 519 }; 520 521 omap_12m_fck: omap_12m_fck { 522 #clock-cells = <0>; 523 compatible = "fixed-factor-clock"; 524 clocks = <&omap_48m_fck>; 525 clock-mult = <1>; 526 clock-div = <4>; 527 }; 528 529 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { 530 #clock-cells = <0>; 531 compatible = "ti,fixed-factor-clock"; 532 clocks = <&dpll4_m4_ck>; 533 ti,clock-mult = <2>; 534 ti,clock-div = <1>; 535 ti,set-rate-parent; 536 }; 537 538 dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { 539 #clock-cells = <0>; 540 compatible = "ti,gate-clock"; 541 clocks = <&dpll4_m4x2_mul_ck>; 542 ti,bit-shift = <0x1d>; 543 reg = <0x0d00>; 544 ti,set-bit-to-disable; 545 ti,set-rate-parent; 546 }; 547 548 dpll4_m5_ck: dpll4_m5_ck@f40 { 549 #clock-cells = <0>; 550 compatible = "ti,divider-clock"; 551 clocks = <&dpll4_ck>; 552 ti,max-div = <63>; 553 reg = <0x0f40>; 554 ti,index-starts-at-one; 555 }; 556 557 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { 558 #clock-cells = <0>; 559 compatible = "ti,fixed-factor-clock"; 560 clocks = <&dpll4_m5_ck>; 561 ti,clock-mult = <2>; 562 ti,clock-div = <1>; 563 ti,set-rate-parent; 564 }; 565 566 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { 567 #clock-cells = <0>; 568 compatible = "ti,gate-clock"; 569 clocks = <&dpll4_m5x2_mul_ck>; 570 ti,bit-shift = <0x1e>; 571 reg = <0x0d00>; 572 ti,set-bit-to-disable; 573 ti,set-rate-parent; 574 }; 575 576 dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { 577 #clock-cells = <0>; 578 compatible = "fixed-factor-clock"; 579 clocks = <&dpll4_m6_ck>; 580 clock-mult = <2>; 581 clock-div = <1>; 582 }; 583 584 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { 585 #clock-cells = <0>; 586 compatible = "ti,gate-clock"; 587 clocks = <&dpll4_m6x2_mul_ck>; 588 ti,bit-shift = <0x1f>; 589 reg = <0x0d00>; 590 ti,set-bit-to-disable; 591 }; 592 593 emu_per_alwon_ck: emu_per_alwon_ck { 594 #clock-cells = <0>; 595 compatible = "fixed-factor-clock"; 596 clocks = <&dpll4_m6x2_ck>; 597 clock-mult = <1>; 598 clock-div = <1>; 599 }; 600 601 /* CM_CLKOUT_CTRL */ 602 clock@d70 { 603 compatible = "ti,clksel"; 604 reg = <0xd70>; 605 #clock-cells = <2>; 606 #address-cells = <0>; 607 608 clkout2_src_gate_ck: clock-clkout2-src-gate { 609 #clock-cells = <0>; 610 compatible = "ti,composite-no-wait-gate-clock"; 611 clock-output-names = "clkout2_src_gate_ck"; 612 clocks = <&core_ck>; 613 ti,bit-shift = <7>; 614 }; 615 616 clkout2_src_mux_ck: clock-clkout2-src-mux { 617 #clock-cells = <0>; 618 compatible = "ti,composite-mux-clock"; 619 clock-output-names = "clkout2_src_mux_ck"; 620 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; 621 }; 622 623 sys_clkout2: clock-sys-clkout2 { 624 #clock-cells = <0>; 625 compatible = "ti,divider-clock"; 626 clock-output-names = "sys_clkout2"; 627 clocks = <&clkout2_src_ck>; 628 ti,bit-shift = <3>; 629 ti,max-div = <64>; 630 ti,index-power-of-two; 631 }; 632 }; 633 634 clkout2_src_ck: clkout2_src_ck { 635 #clock-cells = <0>; 636 compatible = "ti,composite-clock"; 637 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; 638 }; 639 640 mpu_ck: mpu_ck { 641 #clock-cells = <0>; 642 compatible = "fixed-factor-clock"; 643 clocks = <&dpll1_x2m2_ck>; 644 clock-mult = <1>; 645 clock-div = <1>; 646 }; 647 648 arm_fck: arm_fck@924 { 649 #clock-cells = <0>; 650 compatible = "ti,divider-clock"; 651 clocks = <&mpu_ck>; 652 reg = <0x0924>; 653 ti,max-div = <2>; 654 }; 655 656 emu_mpu_alwon_ck: emu_mpu_alwon_ck { 657 #clock-cells = <0>; 658 compatible = "fixed-factor-clock"; 659 clocks = <&mpu_ck>; 660 clock-mult = <1>; 661 clock-div = <1>; 662 }; 663 664 /* CM_CLKSEL_CORE */ 665 clock@a40 { 666 compatible = "ti,clksel"; 667 reg = <0xa40>; 668 #clock-cells = <2>; 669 #address-cells = <0>; 670 671 l3_ick: clock-l3-ick { 672 #clock-cells = <0>; 673 compatible = "ti,divider-clock"; 674 clock-output-names = "l3_ick"; 675 clocks = <&core_ck>; 676 ti,max-div = <3>; 677 ti,index-starts-at-one; 678 }; 679 680 l4_ick: clock-l4-ick { 681 #clock-cells = <0>; 682 compatible = "ti,divider-clock"; 683 clock-output-names = "l4_ick"; 684 clocks = <&l3_ick>; 685 ti,bit-shift = <2>; 686 ti,max-div = <3>; 687 ti,index-starts-at-one; 688 }; 689 690 gpt10_mux_fck: clock-gpt10-mux-fck { 691 #clock-cells = <0>; 692 compatible = "ti,composite-mux-clock"; 693 clock-output-names = "gpt10_mux_fck"; 694 clocks = <&omap_32k_fck>, <&sys_ck>; 695 ti,bit-shift = <6>; 696 }; 697 698 gpt11_mux_fck: clock-gpt11-mux-fck { 699 #clock-cells = <0>; 700 compatible = "ti,composite-mux-clock"; 701 clock-output-names = "gpt11_mux_fck"; 702 clocks = <&omap_32k_fck>, <&sys_ck>; 703 ti,bit-shift = <7>; 704 }; 705 }; 706 707 /* CM_CLKSEL_WKUP */ 708 clock@c40 { 709 compatible = "ti,clksel"; 710 reg = <0xc40>; 711 #clock-cells = <2>; 712 #address-cells = <0>; 713 714 rm_ick: clock-rm-ick { 715 #clock-cells = <0>; 716 compatible = "ti,divider-clock"; 717 clock-output-names = "rm_ick"; 718 clocks = <&l4_ick>; 719 ti,bit-shift = <1>; 720 ti,max-div = <3>; 721 ti,index-starts-at-one; 722 }; 723 724 gpt1_mux_fck: clock-gpt1-mux-fck { 725 #clock-cells = <0>; 726 compatible = "ti,composite-mux-clock"; 727 clock-output-names = "gpt1_mux_fck"; 728 clocks = <&omap_32k_fck>, <&sys_ck>; 729 }; 730 }; 731 732 /* CM_FCLKEN1_CORE */ 733 clock@a00 { 734 compatible = "ti,clksel"; 735 reg = <0xa00>; 736 #clock-cells = <2>; 737 #address-cells = <0>; 738 739 gpt10_gate_fck: clock-gpt10-gate-fck { 740 #clock-cells = <0>; 741 compatible = "ti,composite-gate-clock"; 742 clock-output-names = "gpt10_gate_fck"; 743 clocks = <&sys_ck>; 744 ti,bit-shift = <11>; 745 }; 746 747 gpt11_gate_fck: clock-gpt11-gate-fck { 748 #clock-cells = <0>; 749 compatible = "ti,composite-gate-clock"; 750 clock-output-names = "gpt11_gate_fck"; 751 clocks = <&sys_ck>; 752 ti,bit-shift = <12>; 753 }; 754 755 mmchs2_fck: clock-mmchs2-fck { 756 #clock-cells = <0>; 757 compatible = "ti,wait-gate-clock"; 758 clock-output-names = "mmchs2_fck"; 759 clocks = <&core_96m_fck>; 760 ti,bit-shift = <25>; 761 }; 762 763 mmchs1_fck: clock-mmchs1-fck { 764 #clock-cells = <0>; 765 compatible = "ti,wait-gate-clock"; 766 clock-output-names = "mmchs1_fck"; 767 clocks = <&core_96m_fck>; 768 ti,bit-shift = <24>; 769 }; 770 771 i2c3_fck: clock-i2c3-fck { 772 #clock-cells = <0>; 773 compatible = "ti,wait-gate-clock"; 774 clock-output-names = "i2c3_fck"; 775 clocks = <&core_96m_fck>; 776 ti,bit-shift = <17>; 777 }; 778 779 i2c2_fck: clock-i2c2-fck { 780 #clock-cells = <0>; 781 compatible = "ti,wait-gate-clock"; 782 clock-output-names = "i2c2_fck"; 783 clocks = <&core_96m_fck>; 784 ti,bit-shift = <16>; 785 }; 786 787 i2c1_fck: clock-i2c1-fck { 788 #clock-cells = <0>; 789 compatible = "ti,wait-gate-clock"; 790 clock-output-names = "i2c1_fck"; 791 clocks = <&core_96m_fck>; 792 ti,bit-shift = <15>; 793 }; 794 795 mcbsp5_gate_fck: clock-mcbsp5-gate-fck { 796 #clock-cells = <0>; 797 compatible = "ti,composite-gate-clock"; 798 clock-output-names = "mcbsp5_gate_fck"; 799 clocks = <&mcbsp_clks>; 800 ti,bit-shift = <10>; 801 }; 802 803 mcbsp1_gate_fck: clock-mcbsp1-gate-fck { 804 #clock-cells = <0>; 805 compatible = "ti,composite-gate-clock"; 806 clock-output-names = "mcbsp1_gate_fck"; 807 clocks = <&mcbsp_clks>; 808 ti,bit-shift = <9>; 809 }; 810 811 mcspi4_fck: clock-mcspi4-fck { 812 #clock-cells = <0>; 813 compatible = "ti,wait-gate-clock"; 814 clock-output-names = "mcspi4_fck"; 815 clocks = <&core_48m_fck>; 816 ti,bit-shift = <21>; 817 }; 818 819 mcspi3_fck: clock-mcspi3-fck { 820 #clock-cells = <0>; 821 compatible = "ti,wait-gate-clock"; 822 clock-output-names = "mcspi3_fck"; 823 clocks = <&core_48m_fck>; 824 ti,bit-shift = <20>; 825 }; 826 827 mcspi2_fck: clock-mcspi2-fck { 828 #clock-cells = <0>; 829 compatible = "ti,wait-gate-clock"; 830 clock-output-names = "mcspi2_fck"; 831 clocks = <&core_48m_fck>; 832 ti,bit-shift = <19>; 833 }; 834 835 mcspi1_fck: clock-mcspi1-fck { 836 #clock-cells = <0>; 837 compatible = "ti,wait-gate-clock"; 838 clock-output-names = "mcspi1_fck"; 839 clocks = <&core_48m_fck>; 840 ti,bit-shift = <18>; 841 }; 842 843 uart2_fck: clock-uart2-fck { 844 #clock-cells = <0>; 845 compatible = "ti,wait-gate-clock"; 846 clock-output-names = "uart2_fck"; 847 clocks = <&core_48m_fck>; 848 ti,bit-shift = <14>; 849 }; 850 851 uart1_fck: clock-uart1-fck { 852 #clock-cells = <0>; 853 compatible = "ti,wait-gate-clock"; 854 clock-output-names = "uart1_fck"; 855 clocks = <&core_48m_fck>; 856 ti,bit-shift = <13>; 857 }; 858 859 hdq_fck: clock-hdq-fck { 860 #clock-cells = <0>; 861 compatible = "ti,wait-gate-clock"; 862 clock-output-names = "hdq_fck"; 863 clocks = <&core_12m_fck>; 864 ti,bit-shift = <22>; 865 }; 866 }; 867 868 gpt10_fck: gpt10_fck { 869 #clock-cells = <0>; 870 compatible = "ti,composite-clock"; 871 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; 872 }; 873 874 gpt11_fck: gpt11_fck { 875 #clock-cells = <0>; 876 compatible = "ti,composite-clock"; 877 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; 878 }; 879 880 core_96m_fck: core_96m_fck { 881 #clock-cells = <0>; 882 compatible = "fixed-factor-clock"; 883 clocks = <&omap_96m_fck>; 884 clock-mult = <1>; 885 clock-div = <1>; 886 }; 887 888 core_48m_fck: core_48m_fck { 889 #clock-cells = <0>; 890 compatible = "fixed-factor-clock"; 891 clocks = <&omap_48m_fck>; 892 clock-mult = <1>; 893 clock-div = <1>; 894 }; 895 896 core_12m_fck: core_12m_fck { 897 #clock-cells = <0>; 898 compatible = "fixed-factor-clock"; 899 clocks = <&omap_12m_fck>; 900 clock-mult = <1>; 901 clock-div = <1>; 902 }; 903 904 core_l3_ick: core_l3_ick { 905 #clock-cells = <0>; 906 compatible = "fixed-factor-clock"; 907 clocks = <&l3_ick>; 908 clock-mult = <1>; 909 clock-div = <1>; 910 }; 911 912 /* CM_ICLKEN1_CORE */ 913 clock@a10 { 914 compatible = "ti,clksel"; 915 reg = <0xa10>; 916 #clock-cells = <2>; 917 #address-cells = <0>; 918 919 sdrc_ick: clock-sdrc-ick { 920 #clock-cells = <0>; 921 compatible = "ti,wait-gate-clock"; 922 clock-output-names = "sdrc_ick"; 923 clocks = <&core_l3_ick>; 924 ti,bit-shift = <1>; 925 }; 926 927 mmchs2_ick: clock-mmchs2-ick { 928 #clock-cells = <0>; 929 compatible = "ti,omap3-interface-clock"; 930 clock-output-names = "mmchs2_ick"; 931 clocks = <&core_l4_ick>; 932 ti,bit-shift = <25>; 933 }; 934 935 mmchs1_ick: clock-mmchs1-ick { 936 #clock-cells = <0>; 937 compatible = "ti,omap3-interface-clock"; 938 clock-output-names = "mmchs1_ick"; 939 clocks = <&core_l4_ick>; 940 ti,bit-shift = <24>; 941 }; 942 943 hdq_ick: clock-hdq-ick { 944 #clock-cells = <0>; 945 compatible = "ti,omap3-interface-clock"; 946 clock-output-names = "hdq_ick"; 947 clocks = <&core_l4_ick>; 948 ti,bit-shift = <22>; 949 }; 950 951 mcspi4_ick: clock-mcspi4-ick { 952 #clock-cells = <0>; 953 compatible = "ti,omap3-interface-clock"; 954 clock-output-names = "mcspi4_ick"; 955 clocks = <&core_l4_ick>; 956 ti,bit-shift = <21>; 957 }; 958 959 mcspi3_ick: clock-mcspi3-ick { 960 #clock-cells = <0>; 961 compatible = "ti,omap3-interface-clock"; 962 clock-output-names = "mcspi3_ick"; 963 clocks = <&core_l4_ick>; 964 ti,bit-shift = <20>; 965 }; 966 967 mcspi2_ick: clock-mcspi2-ick { 968 #clock-cells = <0>; 969 compatible = "ti,omap3-interface-clock"; 970 clock-output-names = "mcspi2_ick"; 971 clocks = <&core_l4_ick>; 972 ti,bit-shift = <19>; 973 }; 974 975 mcspi1_ick: clock-mcspi1-ick { 976 #clock-cells = <0>; 977 compatible = "ti,omap3-interface-clock"; 978 clock-output-names = "mcspi1_ick"; 979 clocks = <&core_l4_ick>; 980 ti,bit-shift = <18>; 981 }; 982 983 i2c3_ick: clock-i2c3-ick { 984 #clock-cells = <0>; 985 compatible = "ti,omap3-interface-clock"; 986 clock-output-names = "i2c3_ick"; 987 clocks = <&core_l4_ick>; 988 ti,bit-shift = <17>; 989 }; 990 991 i2c2_ick: clock-i2c2-ick { 992 #clock-cells = <0>; 993 compatible = "ti,omap3-interface-clock"; 994 clock-output-names = "i2c2_ick"; 995 clocks = <&core_l4_ick>; 996 ti,bit-shift = <16>; 997 }; 998 999 i2c1_ick: clock-i2c1-ick { 1000 #clock-cells = <0>; 1001 compatible = "ti,omap3-interface-clock"; 1002 clock-output-names = "i2c1_ick"; 1003 clocks = <&core_l4_ick>; 1004 ti,bit-shift = <15>; 1005 }; 1006 1007 uart2_ick: clock-uart2-ick { 1008 #clock-cells = <0>; 1009 compatible = "ti,omap3-interface-clock"; 1010 clock-output-names = "uart2_ick"; 1011 clocks = <&core_l4_ick>; 1012 ti,bit-shift = <14>; 1013 }; 1014 1015 uart1_ick: clock-uart1-ick { 1016 #clock-cells = <0>; 1017 compatible = "ti,omap3-interface-clock"; 1018 clock-output-names = "uart1_ick"; 1019 clocks = <&core_l4_ick>; 1020 ti,bit-shift = <13>; 1021 }; 1022 1023 gpt11_ick: clock-gpt11-ick { 1024 #clock-cells = <0>; 1025 compatible = "ti,omap3-interface-clock"; 1026 clock-output-names = "gpt11_ick"; 1027 clocks = <&core_l4_ick>; 1028 ti,bit-shift = <12>; 1029 }; 1030 1031 gpt10_ick: clock-gpt10-ick { 1032 #clock-cells = <0>; 1033 compatible = "ti,omap3-interface-clock"; 1034 clock-output-names = "gpt10_ick"; 1035 clocks = <&core_l4_ick>; 1036 ti,bit-shift = <11>; 1037 }; 1038 1039 mcbsp5_ick: clock-mcbsp5-ick { 1040 #clock-cells = <0>; 1041 compatible = "ti,omap3-interface-clock"; 1042 clock-output-names = "mcbsp5_ick"; 1043 clocks = <&core_l4_ick>; 1044 ti,bit-shift = <10>; 1045 }; 1046 1047 mcbsp1_ick: clock-mcbsp1-ick { 1048 #clock-cells = <0>; 1049 compatible = "ti,omap3-interface-clock"; 1050 clock-output-names = "mcbsp1_ick"; 1051 clocks = <&core_l4_ick>; 1052 ti,bit-shift = <9>; 1053 }; 1054 1055 omapctrl_ick: clock-omapctrl-ick { 1056 #clock-cells = <0>; 1057 compatible = "ti,omap3-interface-clock"; 1058 clock-output-names = "omapctrl_ick"; 1059 clocks = <&core_l4_ick>; 1060 ti,bit-shift = <6>; 1061 }; 1062 1063 aes2_ick: clock-aes2-ick { 1064 #clock-cells = <0>; 1065 compatible = "ti,omap3-interface-clock"; 1066 clock-output-names = "aes2_ick"; 1067 clocks = <&core_l4_ick>; 1068 ti,bit-shift = <28>; 1069 }; 1070 1071 sha12_ick: clock-sha12-ick { 1072 #clock-cells = <0>; 1073 compatible = "ti,omap3-interface-clock"; 1074 clock-output-names = "sha12_ick"; 1075 clocks = <&core_l4_ick>; 1076 ti,bit-shift = <27>; 1077 }; 1078 }; 1079 1080 gpmc_fck: gpmc_fck { 1081 #clock-cells = <0>; 1082 compatible = "fixed-factor-clock"; 1083 clocks = <&core_l3_ick>; 1084 clock-mult = <1>; 1085 clock-div = <1>; 1086 }; 1087 1088 core_l4_ick: core_l4_ick { 1089 #clock-cells = <0>; 1090 compatible = "fixed-factor-clock"; 1091 clocks = <&l4_ick>; 1092 clock-mult = <1>; 1093 clock-div = <1>; 1094 }; 1095 1096 /* CM_FCLKEN_DSS */ 1097 clock@e00 { 1098 compatible = "ti,clksel"; 1099 reg = <0xe00>; 1100 #clock-cells = <2>; 1101 #address-cells = <0>; 1102 1103 dss_tv_fck: clock-dss-tv-fck { 1104 #clock-cells = <0>; 1105 compatible = "ti,gate-clock"; 1106 clock-output-names = "dss_tv_fck"; 1107 clocks = <&omap_54m_fck>; 1108 ti,bit-shift = <2>; 1109 }; 1110 1111 dss_96m_fck: clock-dss-96m-fck { 1112 #clock-cells = <0>; 1113 compatible = "ti,gate-clock"; 1114 clock-output-names = "dss_96m_fck"; 1115 clocks = <&omap_96m_fck>; 1116 ti,bit-shift = <2>; 1117 }; 1118 1119 dss2_alwon_fck: clock-dss2-alwon-fck { 1120 #clock-cells = <0>; 1121 compatible = "ti,gate-clock"; 1122 clock-output-names = "dss2_alwon_fck"; 1123 clocks = <&sys_ck>; 1124 ti,bit-shift = <1>; 1125 }; 1126 }; 1127 1128 dummy_ck: dummy_ck { 1129 #clock-cells = <0>; 1130 compatible = "fixed-clock"; 1131 clock-frequency = <0>; 1132 }; 1133 1134 /* CM_FCLKEN_WKUP */ 1135 clock@c00 { 1136 compatible = "ti,clksel"; 1137 reg = <0xc00>; 1138 #clock-cells = <2>; 1139 #address-cells = <0>; 1140 1141 gpt1_gate_fck: clock-gpt1-gate-fck { 1142 #clock-cells = <0>; 1143 compatible = "ti,composite-gate-clock"; 1144 clock-output-names = "gpt1_gate_fck"; 1145 clocks = <&sys_ck>; 1146 ti,bit-shift = <0>; 1147 }; 1148 1149 gpio1_dbck: clock-gpio1-dbck { 1150 #clock-cells = <0>; 1151 compatible = "ti,gate-clock"; 1152 clock-output-names = "gpio1_dbck"; 1153 clocks = <&wkup_32k_fck>; 1154 ti,bit-shift = <3>; 1155 }; 1156 1157 wdt2_fck: clock-wdt2-fck { 1158 #clock-cells = <0>; 1159 compatible = "ti,wait-gate-clock"; 1160 clock-output-names = "wdt2_fck"; 1161 clocks = <&wkup_32k_fck>; 1162 ti,bit-shift = <5>; 1163 }; 1164 }; 1165 1166 gpt1_fck: gpt1_fck { 1167 #clock-cells = <0>; 1168 compatible = "ti,composite-clock"; 1169 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; 1170 }; 1171 1172 wkup_32k_fck: wkup_32k_fck { 1173 #clock-cells = <0>; 1174 compatible = "fixed-factor-clock"; 1175 clocks = <&omap_32k_fck>; 1176 clock-mult = <1>; 1177 clock-div = <1>; 1178 }; 1179 1180 /* CM_ICLKEN_WKUP */ 1181 clock@c10 { 1182 compatible = "ti,clksel"; 1183 reg = <0xc10>; 1184 #clock-cells = <2>; 1185 #address-cells = <0>; 1186 1187 wdt2_ick: clock-wdt2-ick { 1188 #clock-cells = <0>; 1189 compatible = "ti,omap3-interface-clock"; 1190 clock-output-names = "wdt2_ick"; 1191 clocks = <&wkup_l4_ick>; 1192 ti,bit-shift = <5>; 1193 }; 1194 1195 wdt1_ick: clock-wdt1-ick { 1196 #clock-cells = <0>; 1197 compatible = "ti,omap3-interface-clock"; 1198 clock-output-names = "wdt1_ick"; 1199 clocks = <&wkup_l4_ick>; 1200 ti,bit-shift = <4>; 1201 }; 1202 1203 gpio1_ick: clock-gpio1-ick { 1204 #clock-cells = <0>; 1205 compatible = "ti,omap3-interface-clock"; 1206 clock-output-names = "gpio1_ick"; 1207 clocks = <&wkup_l4_ick>; 1208 ti,bit-shift = <3>; 1209 }; 1210 1211 omap_32ksync_ick: clock-omap-32ksync-ick { 1212 #clock-cells = <0>; 1213 compatible = "ti,omap3-interface-clock"; 1214 clock-output-names = "omap_32ksync_ick"; 1215 clocks = <&wkup_l4_ick>; 1216 ti,bit-shift = <2>; 1217 }; 1218 1219 gpt12_ick: clock-gpt12-ick { 1220 #clock-cells = <0>; 1221 compatible = "ti,omap3-interface-clock"; 1222 clock-output-names = "gpt12_ick"; 1223 clocks = <&wkup_l4_ick>; 1224 ti,bit-shift = <1>; 1225 }; 1226 1227 gpt1_ick: clock-gpt1-ick { 1228 #clock-cells = <0>; 1229 compatible = "ti,omap3-interface-clock"; 1230 clock-output-names = "gpt1_ick"; 1231 clocks = <&wkup_l4_ick>; 1232 ti,bit-shift = <0>; 1233 }; 1234 }; 1235 1236 per_96m_fck: per_96m_fck { 1237 #clock-cells = <0>; 1238 compatible = "fixed-factor-clock"; 1239 clocks = <&omap_96m_alwon_fck>; 1240 clock-mult = <1>; 1241 clock-div = <1>; 1242 }; 1243 1244 per_48m_fck: per_48m_fck { 1245 #clock-cells = <0>; 1246 compatible = "fixed-factor-clock"; 1247 clocks = <&omap_48m_fck>; 1248 clock-mult = <1>; 1249 clock-div = <1>; 1250 }; 1251 1252 /* CM_FCLKEN_PER */ 1253 clock@1000 { 1254 compatible = "ti,clksel"; 1255 reg = <0x1000>; 1256 #clock-cells = <2>; 1257 #address-cells = <0>; 1258 1259 uart3_fck: clock-uart3-fck { 1260 #clock-cells = <0>; 1261 compatible = "ti,wait-gate-clock"; 1262 clock-output-names = "uart3_fck"; 1263 clocks = <&per_48m_fck>; 1264 ti,bit-shift = <11>; 1265 }; 1266 1267 gpt2_gate_fck: clock-gpt2-gate-fck { 1268 #clock-cells = <0>; 1269 compatible = "ti,composite-gate-clock"; 1270 clock-output-names = "gpt2_gate_fck"; 1271 clocks = <&sys_ck>; 1272 ti,bit-shift = <3>; 1273 }; 1274 1275 gpt3_gate_fck: clock-gpt3-gate-fck { 1276 #clock-cells = <0>; 1277 compatible = "ti,composite-gate-clock"; 1278 clock-output-names = "gpt3_gate_fck"; 1279 clocks = <&sys_ck>; 1280 ti,bit-shift = <4>; 1281 }; 1282 1283 gpt4_gate_fck: clock-gpt4-gate-fck { 1284 #clock-cells = <0>; 1285 compatible = "ti,composite-gate-clock"; 1286 clock-output-names = "gpt4_gate_fck"; 1287 clocks = <&sys_ck>; 1288 ti,bit-shift = <5>; 1289 }; 1290 1291 gpt5_gate_fck: clock-gpt5-gate-fck { 1292 #clock-cells = <0>; 1293 compatible = "ti,composite-gate-clock"; 1294 clock-output-names = "gpt5_gate_fck"; 1295 clocks = <&sys_ck>; 1296 ti,bit-shift = <6>; 1297 }; 1298 1299 gpt6_gate_fck: clock-gpt6-gate-fck { 1300 #clock-cells = <0>; 1301 compatible = "ti,composite-gate-clock"; 1302 clock-output-names = "gpt6_gate_fck"; 1303 clocks = <&sys_ck>; 1304 ti,bit-shift = <7>; 1305 }; 1306 1307 gpt7_gate_fck: clock-gpt7-gate-fck { 1308 #clock-cells = <0>; 1309 compatible = "ti,composite-gate-clock"; 1310 clock-output-names = "gpt7_gate_fck"; 1311 clocks = <&sys_ck>; 1312 ti,bit-shift = <8>; 1313 }; 1314 1315 gpt8_gate_fck: clock-gpt8-gate-fck { 1316 #clock-cells = <0>; 1317 compatible = "ti,composite-gate-clock"; 1318 clock-output-names = "gpt8_gate_fck"; 1319 clocks = <&sys_ck>; 1320 ti,bit-shift = <9>; 1321 }; 1322 1323 gpt9_gate_fck: clock-gpt9-gate-fck { 1324 #clock-cells = <0>; 1325 compatible = "ti,composite-gate-clock"; 1326 clock-output-names = "gpt9_gate_fck"; 1327 clocks = <&sys_ck>; 1328 ti,bit-shift = <10>; 1329 }; 1330 1331 gpio6_dbck: clock-gpio6-dbck { 1332 #clock-cells = <0>; 1333 compatible = "ti,gate-clock"; 1334 clock-output-names = "gpio6_dbck"; 1335 clocks = <&per_32k_alwon_fck>; 1336 ti,bit-shift = <17>; 1337 }; 1338 1339 gpio5_dbck: clock-gpio5-dbck { 1340 #clock-cells = <0>; 1341 compatible = "ti,gate-clock"; 1342 clock-output-names = "gpio5_dbck"; 1343 clocks = <&per_32k_alwon_fck>; 1344 ti,bit-shift = <16>; 1345 }; 1346 1347 gpio4_dbck: clock-gpio4-dbck { 1348 #clock-cells = <0>; 1349 compatible = "ti,gate-clock"; 1350 clock-output-names = "gpio4_dbck"; 1351 clocks = <&per_32k_alwon_fck>; 1352 ti,bit-shift = <15>; 1353 }; 1354 1355 gpio3_dbck: clock-gpio3-dbck { 1356 #clock-cells = <0>; 1357 compatible = "ti,gate-clock"; 1358 clock-output-names = "gpio3_dbck"; 1359 clocks = <&per_32k_alwon_fck>; 1360 ti,bit-shift = <14>; 1361 }; 1362 1363 gpio2_dbck: clock-gpio2-dbck { 1364 #clock-cells = <0>; 1365 compatible = "ti,gate-clock"; 1366 clock-output-names = "gpio2_dbck"; 1367 clocks = <&per_32k_alwon_fck>; 1368 ti,bit-shift = <13>; 1369 }; 1370 1371 wdt3_fck: clock-wdt3-fck { 1372 #clock-cells = <0>; 1373 compatible = "ti,wait-gate-clock"; 1374 clock-output-names = "wdt3_fck"; 1375 clocks = <&per_32k_alwon_fck>; 1376 ti,bit-shift = <12>; 1377 }; 1378 1379 mcbsp2_gate_fck: clock-mcbsp2-gate-fck { 1380 #clock-cells = <0>; 1381 compatible = "ti,composite-gate-clock"; 1382 clock-output-names = "mcbsp2_gate_fck"; 1383 clocks = <&mcbsp_clks>; 1384 ti,bit-shift = <0>; 1385 }; 1386 1387 mcbsp3_gate_fck: clock-mcbsp3-gate-fck { 1388 #clock-cells = <0>; 1389 compatible = "ti,composite-gate-clock"; 1390 clock-output-names = "mcbsp3_gate_fck"; 1391 clocks = <&mcbsp_clks>; 1392 ti,bit-shift = <1>; 1393 }; 1394 1395 mcbsp4_gate_fck: clock-mcbsp4-gate-fck { 1396 #clock-cells = <0>; 1397 compatible = "ti,composite-gate-clock"; 1398 clock-output-names = "mcbsp4_gate_fck"; 1399 clocks = <&mcbsp_clks>; 1400 ti,bit-shift = <2>; 1401 }; 1402 }; 1403 1404 /* CM_CLKSEL_PER */ 1405 clock@1040 { 1406 compatible = "ti,clksel"; 1407 reg = <0x1040>; 1408 #clock-cells = <2>; 1409 #address-cells = <0>; 1410 1411 gpt2_mux_fck: clock-gpt2-mux-fck { 1412 #clock-cells = <0>; 1413 compatible = "ti,composite-mux-clock"; 1414 clock-output-names = "gpt2_mux_fck"; 1415 clocks = <&omap_32k_fck>, <&sys_ck>; 1416 }; 1417 1418 gpt3_mux_fck: clock-gpt3-mux-fck { 1419 #clock-cells = <0>; 1420 compatible = "ti,composite-mux-clock"; 1421 clock-output-names = "gpt3_mux_fck"; 1422 clocks = <&omap_32k_fck>, <&sys_ck>; 1423 ti,bit-shift = <1>; 1424 }; 1425 1426 gpt4_mux_fck: clock-gpt4-mux-fck { 1427 #clock-cells = <0>; 1428 compatible = "ti,composite-mux-clock"; 1429 clock-output-names = "gpt4_mux_fck"; 1430 clocks = <&omap_32k_fck>, <&sys_ck>; 1431 ti,bit-shift = <2>; 1432 }; 1433 1434 gpt5_mux_fck: clock-gpt5-mux-fck { 1435 #clock-cells = <0>; 1436 compatible = "ti,composite-mux-clock"; 1437 clock-output-names = "gpt5_mux_fck"; 1438 clocks = <&omap_32k_fck>, <&sys_ck>; 1439 ti,bit-shift = <3>; 1440 }; 1441 1442 gpt6_mux_fck: clock-gpt6-mux-fck { 1443 #clock-cells = <0>; 1444 compatible = "ti,composite-mux-clock"; 1445 clock-output-names = "gpt6_mux_fck"; 1446 clocks = <&omap_32k_fck>, <&sys_ck>; 1447 ti,bit-shift = <4>; 1448 }; 1449 1450 gpt7_mux_fck: clock-gpt7-mux-fck { 1451 #clock-cells = <0>; 1452 compatible = "ti,composite-mux-clock"; 1453 clock-output-names = "gpt7_mux_fck"; 1454 clocks = <&omap_32k_fck>, <&sys_ck>; 1455 ti,bit-shift = <5>; 1456 }; 1457 1458 gpt8_mux_fck: clock-gpt8-mux-fck { 1459 #clock-cells = <0>; 1460 compatible = "ti,composite-mux-clock"; 1461 clock-output-names = "gpt8_mux_fck"; 1462 clocks = <&omap_32k_fck>, <&sys_ck>; 1463 ti,bit-shift = <6>; 1464 }; 1465 1466 gpt9_mux_fck: clock-gpt9-mux-fck { 1467 #clock-cells = <0>; 1468 compatible = "ti,composite-mux-clock"; 1469 clock-output-names = "gpt9_mux_fck"; 1470 clocks = <&omap_32k_fck>, <&sys_ck>; 1471 ti,bit-shift = <7>; 1472 }; 1473 }; 1474 1475 gpt2_fck: gpt2_fck { 1476 #clock-cells = <0>; 1477 compatible = "ti,composite-clock"; 1478 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; 1479 }; 1480 1481 gpt3_fck: gpt3_fck { 1482 #clock-cells = <0>; 1483 compatible = "ti,composite-clock"; 1484 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; 1485 }; 1486 1487 gpt4_fck: gpt4_fck { 1488 #clock-cells = <0>; 1489 compatible = "ti,composite-clock"; 1490 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; 1491 }; 1492 1493 gpt5_fck: gpt5_fck { 1494 #clock-cells = <0>; 1495 compatible = "ti,composite-clock"; 1496 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; 1497 }; 1498 1499 gpt6_fck: gpt6_fck { 1500 #clock-cells = <0>; 1501 compatible = "ti,composite-clock"; 1502 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; 1503 }; 1504 1505 gpt7_fck: gpt7_fck { 1506 #clock-cells = <0>; 1507 compatible = "ti,composite-clock"; 1508 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; 1509 }; 1510 1511 gpt8_fck: gpt8_fck { 1512 #clock-cells = <0>; 1513 compatible = "ti,composite-clock"; 1514 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; 1515 }; 1516 1517 gpt9_fck: gpt9_fck { 1518 #clock-cells = <0>; 1519 compatible = "ti,composite-clock"; 1520 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; 1521 }; 1522 1523 per_32k_alwon_fck: per_32k_alwon_fck { 1524 #clock-cells = <0>; 1525 compatible = "fixed-factor-clock"; 1526 clocks = <&omap_32k_fck>; 1527 clock-mult = <1>; 1528 clock-div = <1>; 1529 }; 1530 1531 per_l4_ick: per_l4_ick { 1532 #clock-cells = <0>; 1533 compatible = "fixed-factor-clock"; 1534 clocks = <&l4_ick>; 1535 clock-mult = <1>; 1536 clock-div = <1>; 1537 }; 1538 1539 /* CM_ICLKEN_PER */ 1540 clock@1010 { 1541 compatible = "ti,clksel"; 1542 reg = <0x1010>; 1543 #clock-cells = <2>; 1544 #address-cells = <0>; 1545 1546 gpio6_ick: clock-gpio6-ick { 1547 #clock-cells = <0>; 1548 compatible = "ti,omap3-interface-clock"; 1549 clock-output-names = "gpio6_ick"; 1550 clocks = <&per_l4_ick>; 1551 ti,bit-shift = <17>; 1552 }; 1553 1554 gpio5_ick: clock-gpio5-ick { 1555 #clock-cells = <0>; 1556 compatible = "ti,omap3-interface-clock"; 1557 clock-output-names = "gpio5_ick"; 1558 clocks = <&per_l4_ick>; 1559 ti,bit-shift = <16>; 1560 }; 1561 1562 gpio4_ick: clock-gpio4-ick { 1563 #clock-cells = <0>; 1564 compatible = "ti,omap3-interface-clock"; 1565 clock-output-names = "gpio4_ick"; 1566 clocks = <&per_l4_ick>; 1567 ti,bit-shift = <15>; 1568 }; 1569 1570 gpio3_ick: clock-gpio3-ick { 1571 #clock-cells = <0>; 1572 compatible = "ti,omap3-interface-clock"; 1573 clock-output-names = "gpio3_ick"; 1574 clocks = <&per_l4_ick>; 1575 ti,bit-shift = <14>; 1576 }; 1577 1578 gpio2_ick: clock-gpio2-ick { 1579 #clock-cells = <0>; 1580 compatible = "ti,omap3-interface-clock"; 1581 clock-output-names = "gpio2_ick"; 1582 clocks = <&per_l4_ick>; 1583 ti,bit-shift = <13>; 1584 }; 1585 1586 wdt3_ick: clock-wdt3-ick { 1587 #clock-cells = <0>; 1588 compatible = "ti,omap3-interface-clock"; 1589 clock-output-names = "wdt3_ick"; 1590 clocks = <&per_l4_ick>; 1591 ti,bit-shift = <12>; 1592 }; 1593 1594 uart3_ick: clock-uart3-ick { 1595 #clock-cells = <0>; 1596 compatible = "ti,omap3-interface-clock"; 1597 clock-output-names = "uart3_ick"; 1598 clocks = <&per_l4_ick>; 1599 ti,bit-shift = <11>; 1600 }; 1601 1602 uart4_ick: clock-uart4-ick { 1603 #clock-cells = <0>; 1604 compatible = "ti,omap3-interface-clock"; 1605 clock-output-names = "uart4_ick"; 1606 clocks = <&per_l4_ick>; 1607 ti,bit-shift = <18>; 1608 }; 1609 1610 gpt9_ick: clock-gpt9-ick { 1611 #clock-cells = <0>; 1612 compatible = "ti,omap3-interface-clock"; 1613 clock-output-names = "gpt9_ick"; 1614 clocks = <&per_l4_ick>; 1615 ti,bit-shift = <10>; 1616 }; 1617 1618 gpt8_ick: clock-gpt8-ick { 1619 #clock-cells = <0>; 1620 compatible = "ti,omap3-interface-clock"; 1621 clock-output-names = "gpt8_ick"; 1622 clocks = <&per_l4_ick>; 1623 ti,bit-shift = <9>; 1624 }; 1625 1626 gpt7_ick: clock-gpt7-ick { 1627 #clock-cells = <0>; 1628 compatible = "ti,omap3-interface-clock"; 1629 clock-output-names = "gpt7_ick"; 1630 clocks = <&per_l4_ick>; 1631 ti,bit-shift = <8>; 1632 }; 1633 1634 gpt6_ick: clock-gpt6-ick { 1635 #clock-cells = <0>; 1636 compatible = "ti,omap3-interface-clock"; 1637 clock-output-names = "gpt6_ick"; 1638 clocks = <&per_l4_ick>; 1639 ti,bit-shift = <7>; 1640 }; 1641 1642 gpt5_ick: clock-gpt5-ick { 1643 #clock-cells = <0>; 1644 compatible = "ti,omap3-interface-clock"; 1645 clock-output-names = "gpt5_ick"; 1646 clocks = <&per_l4_ick>; 1647 ti,bit-shift = <6>; 1648 }; 1649 1650 gpt4_ick: clock-gpt4-ick { 1651 #clock-cells = <0>; 1652 compatible = "ti,omap3-interface-clock"; 1653 clock-output-names = "gpt4_ick"; 1654 clocks = <&per_l4_ick>; 1655 ti,bit-shift = <5>; 1656 }; 1657 1658 gpt3_ick: clock-gpt3-ick { 1659 #clock-cells = <0>; 1660 compatible = "ti,omap3-interface-clock"; 1661 clock-output-names = "gpt3_ick"; 1662 clocks = <&per_l4_ick>; 1663 ti,bit-shift = <4>; 1664 }; 1665 1666 gpt2_ick: clock-gpt2-ick { 1667 #clock-cells = <0>; 1668 compatible = "ti,omap3-interface-clock"; 1669 clock-output-names = "gpt2_ick"; 1670 clocks = <&per_l4_ick>; 1671 ti,bit-shift = <3>; 1672 }; 1673 1674 mcbsp2_ick: clock-mcbsp2-ick { 1675 #clock-cells = <0>; 1676 compatible = "ti,omap3-interface-clock"; 1677 clock-output-names = "mcbsp2_ick"; 1678 clocks = <&per_l4_ick>; 1679 ti,bit-shift = <0>; 1680 }; 1681 1682 mcbsp3_ick: clock-mcbsp3-ick { 1683 #clock-cells = <0>; 1684 compatible = "ti,omap3-interface-clock"; 1685 clock-output-names = "mcbsp3_ick"; 1686 clocks = <&per_l4_ick>; 1687 ti,bit-shift = <1>; 1688 }; 1689 1690 mcbsp4_ick: clock-mcbsp4-ick { 1691 #clock-cells = <0>; 1692 compatible = "ti,omap3-interface-clock"; 1693 clock-output-names = "mcbsp4_ick"; 1694 clocks = <&per_l4_ick>; 1695 ti,bit-shift = <2>; 1696 }; 1697 }; 1698 1699 emu_src_ck: emu_src_ck { 1700 #clock-cells = <0>; 1701 compatible = "ti,clkdm-gate-clock"; 1702 clocks = <&emu_src_mux_ck>; 1703 }; 1704 1705 secure_32k_fck: secure_32k_fck { 1706 #clock-cells = <0>; 1707 compatible = "fixed-clock"; 1708 clock-frequency = <32768>; 1709 }; 1710 1711 gpt12_fck: gpt12_fck { 1712 #clock-cells = <0>; 1713 compatible = "fixed-factor-clock"; 1714 clocks = <&secure_32k_fck>; 1715 clock-mult = <1>; 1716 clock-div = <1>; 1717 }; 1718 1719 wdt1_fck: wdt1_fck { 1720 #clock-cells = <0>; 1721 compatible = "fixed-factor-clock"; 1722 clocks = <&secure_32k_fck>; 1723 clock-mult = <1>; 1724 clock-div = <1>; 1725 }; 1726}; 1727 1728&cm_clockdomains { 1729 core_l3_clkdm: core_l3_clkdm { 1730 compatible = "ti,clockdomain"; 1731 clocks = <&sdrc_ick>; 1732 }; 1733 1734 dpll3_clkdm: dpll3_clkdm { 1735 compatible = "ti,clockdomain"; 1736 clocks = <&dpll3_ck>; 1737 }; 1738 1739 dpll1_clkdm: dpll1_clkdm { 1740 compatible = "ti,clockdomain"; 1741 clocks = <&dpll1_ck>; 1742 }; 1743 1744 per_clkdm: per_clkdm { 1745 compatible = "ti,clockdomain"; 1746 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, 1747 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, 1748 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, 1749 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, 1750 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, 1751 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, 1752 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, 1753 <&mcbsp4_ick>; 1754 }; 1755 1756 emu_clkdm: emu_clkdm { 1757 compatible = "ti,clockdomain"; 1758 clocks = <&emu_src_ck>; 1759 }; 1760 1761 dpll4_clkdm: dpll4_clkdm { 1762 compatible = "ti,clockdomain"; 1763 clocks = <&dpll4_ck>; 1764 }; 1765 1766 wkup_clkdm: wkup_clkdm { 1767 compatible = "ti,clockdomain"; 1768 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, 1769 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, 1770 <&gpt1_ick>; 1771 }; 1772 1773 dss_clkdm: dss_clkdm { 1774 compatible = "ti,clockdomain"; 1775 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; 1776 }; 1777 1778 core_l4_clkdm: core_l4_clkdm { 1779 compatible = "ti,clockdomain"; 1780 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, 1781 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, 1782 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, 1783 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, 1784 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, 1785 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, 1786 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 1787 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 1788 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; 1789 }; 1790}; 1791