1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 */ 7&prm_clocks { 8 corex2_d3_fck: corex2_d3_fck { 9 #clock-cells = <0>; 10 compatible = "fixed-factor-clock"; 11 clocks = <&corex2_fck>; 12 clock-mult = <1>; 13 clock-div = <3>; 14 }; 15 16 corex2_d5_fck: corex2_d5_fck { 17 #clock-cells = <0>; 18 compatible = "fixed-factor-clock"; 19 clocks = <&corex2_fck>; 20 clock-mult = <1>; 21 clock-div = <5>; 22 }; 23}; 24&cm_clocks { 25 dpll5_ck: dpll5_ck@d04 { 26 #clock-cells = <0>; 27 compatible = "ti,omap3-dpll-clock"; 28 clocks = <&sys_ck>, <&sys_ck>; 29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; 30 ti,low-power-stop; 31 ti,lock; 32 }; 33 34 dpll5_m2_ck: dpll5_m2_ck@d50 { 35 #clock-cells = <0>; 36 compatible = "ti,divider-clock"; 37 clocks = <&dpll5_ck>; 38 ti,max-div = <31>; 39 reg = <0x0d50>; 40 ti,index-starts-at-one; 41 }; 42 43 sgx_gate_fck: sgx_gate_fck@b00 { 44 #clock-cells = <0>; 45 compatible = "ti,composite-gate-clock"; 46 clocks = <&core_ck>; 47 ti,bit-shift = <1>; 48 reg = <0x0b00>; 49 }; 50 51 core_d3_ck: core_d3_ck { 52 #clock-cells = <0>; 53 compatible = "fixed-factor-clock"; 54 clocks = <&core_ck>; 55 clock-mult = <1>; 56 clock-div = <3>; 57 }; 58 59 core_d4_ck: core_d4_ck { 60 #clock-cells = <0>; 61 compatible = "fixed-factor-clock"; 62 clocks = <&core_ck>; 63 clock-mult = <1>; 64 clock-div = <4>; 65 }; 66 67 core_d6_ck: core_d6_ck { 68 #clock-cells = <0>; 69 compatible = "fixed-factor-clock"; 70 clocks = <&core_ck>; 71 clock-mult = <1>; 72 clock-div = <6>; 73 }; 74 75 omap_192m_alwon_fck: omap_192m_alwon_fck { 76 #clock-cells = <0>; 77 compatible = "fixed-factor-clock"; 78 clocks = <&dpll4_m2x2_ck>; 79 clock-mult = <1>; 80 clock-div = <1>; 81 }; 82 83 core_d2_ck: core_d2_ck { 84 #clock-cells = <0>; 85 compatible = "fixed-factor-clock"; 86 clocks = <&core_ck>; 87 clock-mult = <1>; 88 clock-div = <2>; 89 }; 90 91 sgx_mux_fck: sgx_mux_fck@b40 { 92 #clock-cells = <0>; 93 compatible = "ti,composite-mux-clock"; 94 clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; 95 reg = <0x0b40>; 96 }; 97 98 sgx_fck: sgx_fck { 99 #clock-cells = <0>; 100 compatible = "ti,composite-clock"; 101 clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; 102 }; 103 104 sgx_ick: sgx_ick@b10 { 105 #clock-cells = <0>; 106 compatible = "ti,wait-gate-clock"; 107 clocks = <&l3_ick>; 108 reg = <0x0b10>; 109 ti,bit-shift = <0>; 110 }; 111 112 cpefuse_fck: cpefuse_fck@a08 { 113 #clock-cells = <0>; 114 compatible = "ti,gate-clock"; 115 clocks = <&sys_ck>; 116 reg = <0x0a08>; 117 ti,bit-shift = <0>; 118 }; 119 120 ts_fck: ts_fck@a08 { 121 #clock-cells = <0>; 122 compatible = "ti,gate-clock"; 123 clocks = <&omap_32k_fck>; 124 reg = <0x0a08>; 125 ti,bit-shift = <1>; 126 }; 127 128 usbtll_fck: usbtll_fck@a08 { 129 #clock-cells = <0>; 130 compatible = "ti,wait-gate-clock"; 131 clocks = <&dpll5_m2_ck>; 132 reg = <0x0a08>; 133 ti,bit-shift = <2>; 134 }; 135 136 /* CM_ICLKEN3_CORE */ 137 clock@a18 { 138 compatible = "ti,clksel"; 139 reg = <0xa18>; 140 #clock-cells = <2>; 141 #address-cells = <0>; 142 143 usbtll_ick: clock-usbtll-ick { 144 #clock-cells = <0>; 145 compatible = "ti,omap3-interface-clock"; 146 clock-output-names = "usbtll_ick"; 147 clocks = <&core_l4_ick>; 148 ti,bit-shift = <2>; 149 }; 150 }; 151 152 clock@a10 { 153 compatible = "ti,clksel"; 154 reg = <0xa10>; 155 #clock-cells = <2>; 156 #address-cells = <0>; 157 158 mmchs3_ick: clock-mmchs3-ick { 159 #clock-cells = <0>; 160 compatible = "ti,omap3-interface-clock"; 161 clock-output-names = "mmchs3_ick"; 162 clocks = <&core_l4_ick>; 163 ti,bit-shift = <30>; 164 }; 165 }; 166 167 clock@a00 { 168 compatible = "ti,clksel"; 169 reg = <0xa00>; 170 #clock-cells = <2>; 171 #address-cells = <0>; 172 173 mmchs3_fck: clock-mmchs3-fck { 174 #clock-cells = <0>; 175 compatible = "ti,wait-gate-clock"; 176 clock-output-names = "mmchs3_fck"; 177 clocks = <&core_96m_fck>; 178 ti,bit-shift = <30>; 179 }; 180 }; 181 182 clock@e00 { 183 compatible = "ti,clksel"; 184 reg = <0xe00>; 185 #clock-cells = <2>; 186 #address-cells = <0>; 187 188 dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { 189 #clock-cells = <0>; 190 compatible = "ti,dss-gate-clock"; 191 clock-output-names = "dss1_alwon_fck_3430es2"; 192 clocks = <&dpll4_m4x2_ck>; 193 ti,bit-shift = <0>; 194 ti,set-rate-parent; 195 }; 196 }; 197 198 dss_ick: dss_ick_3430es2@e10 { 199 #clock-cells = <0>; 200 compatible = "ti,omap3-dss-interface-clock"; 201 clocks = <&l4_ick>; 202 reg = <0x0e10>; 203 ti,bit-shift = <0>; 204 }; 205 206 usbhost_120m_fck: usbhost_120m_fck@1400 { 207 #clock-cells = <0>; 208 compatible = "ti,gate-clock"; 209 clocks = <&dpll5_m2_ck>; 210 reg = <0x1400>; 211 ti,bit-shift = <1>; 212 }; 213 214 usbhost_48m_fck: usbhost_48m_fck@1400 { 215 #clock-cells = <0>; 216 compatible = "ti,dss-gate-clock"; 217 clocks = <&omap_48m_fck>; 218 reg = <0x1400>; 219 ti,bit-shift = <0>; 220 }; 221 222 usbhost_ick: usbhost_ick@1410 { 223 #clock-cells = <0>; 224 compatible = "ti,omap3-dss-interface-clock"; 225 clocks = <&l4_ick>; 226 reg = <0x1410>; 227 ti,bit-shift = <0>; 228 }; 229}; 230 231&cm_clockdomains { 232 dpll5_clkdm: dpll5_clkdm { 233 compatible = "ti,clockdomain"; 234 clocks = <&dpll5_ck>; 235 }; 236 237 sgx_clkdm: sgx_clkdm { 238 compatible = "ti,clockdomain"; 239 clocks = <&sgx_ick>; 240 }; 241 242 dss_clkdm: dss_clkdm { 243 compatible = "ti,clockdomain"; 244 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, 245 <&dss1_alwon_fck>, <&dss_ick>; 246 }; 247 248 core_l4_clkdm: core_l4_clkdm { 249 compatible = "ti,clockdomain"; 250 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, 251 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, 252 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, 253 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, 254 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, 255 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, 256 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 257 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 258 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, 259 <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, 260 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; 261 }; 262 263 usbhost_clkdm: usbhost_clkdm { 264 compatible = "ti,clockdomain"; 265 clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, 266 <&usbhost_ick>; 267 }; 268}; 269