1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. 4 * 5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/* 9 * Rules for modifying this file: 10 * a) Update of this file should typically correspond to a datamanual revision. 11 * Datamanual revision that was used should be updated in comment below. 12 * If there is no update to datamanual, do not update the values. If you 13 * need to use values different from that recommended by the datamanual 14 * for your design, then you should consider adding values to the device- 15 * -tree file for your board directly. 16 * b) We keep the mode names as close to the datamanual as possible. So 17 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, 18 * we follow that in code too. 19 * c) If the values change between multiple revisions of silicon, we add 20 * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, 21 * 'rev20' for PG 2.0 and so on. 22 * d) The node name and node label should be the exact same string. This is 23 * to curb naming creativity and achieve consistency. 24 * 25 * Datamanual Revisions: 26 * 27 * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019 28 * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 29 * 30 */ 31 32&dra7_pmx_core { 33 mmc1_pins_default: mmc1-default-pins { 34 pinctrl-single,pins = < 35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 41 >; 42 }; 43 44 mmc1_pins_sdr12: mmc1-sdr12-pins { 45 pinctrl-single,pins = < 46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 50 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 51 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 52 >; 53 }; 54 55 mmc1_pins_hs: mmc1-hs-pins { 56 pinctrl-single,pins = < 57 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ 58 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ 59 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ 60 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ 61 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ 62 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ 63 >; 64 }; 65 66 mmc1_pins_sdr25: mmc1-sdr25-pins { 67 pinctrl-single,pins = < 68 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ 69 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ 70 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ 71 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ 72 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ 73 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ 74 >; 75 }; 76 77 mmc1_pins_sdr50: mmc1-sdr50-pins { 78 pinctrl-single,pins = < 79 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ 80 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ 81 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ 82 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ 83 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ 84 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ 85 >; 86 }; 87 88 mmc1_pins_ddr50: mmc1-ddr50-pins { 89 pinctrl-single,pins = < 90 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ 91 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ 92 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ 93 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ 94 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ 95 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ 96 >; 97 }; 98 99 mmc1_pins_sdr104: mmc1-sdr104-pins { 100 pinctrl-single,pins = < 101 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ 102 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ 103 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ 104 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ 105 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ 106 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ 107 >; 108 }; 109 110 mmc2_pins_default: mmc2-default-pins { 111 pinctrl-single,pins = < 112 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 113 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 114 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 115 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 116 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 117 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 118 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 119 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 120 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 121 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 122 >; 123 }; 124 125 mmc2_pins_hs: mmc2-hs-pins { 126 pinctrl-single,pins = < 127 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 128 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 129 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 130 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 131 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 132 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 133 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 134 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 135 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 136 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 137 >; 138 }; 139 140 mmc2_pins_ddr_3_3v_rev11: mmc2-ddr-3-3v-rev11-pins { 141 pinctrl-single,pins = < 142 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 143 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 144 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 145 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 146 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 147 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 148 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 149 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 150 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 151 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 152 >; 153 }; 154 155 mmc2_pins_ddr_1_8v_rev11: mmc2-ddr-1-8v-rev11-pins { 156 pinctrl-single,pins = < 157 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 158 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 159 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 160 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 161 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 162 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 163 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 164 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 165 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 166 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 167 >; 168 }; 169 170 mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { 171 pinctrl-single,pins = < 172 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 173 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 174 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 175 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 176 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 177 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 178 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 179 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 180 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 181 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 182 >; 183 }; 184 185 mmc2_pins_hs200: mmc2-hs200-pins { 186 pinctrl-single,pins = < 187 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 188 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 189 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 190 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 191 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 192 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 193 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 194 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 195 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 196 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 197 >; 198 }; 199 200 mmc4_pins_default: mmc4-default-pins { 201 pinctrl-single,pins = < 202 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 203 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 204 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 205 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 206 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 207 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 208 >; 209 }; 210 211 mmc4_pins_hs: mmc4-hs-pins { 212 pinctrl-single,pins = < 213 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 214 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 215 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 216 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 217 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 218 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 219 >; 220 }; 221 222 mmc3_pins_default: mmc3-default-pins { 223 pinctrl-single,pins = < 224 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 225 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 226 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 227 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 228 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 229 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 230 >; 231 }; 232 233 mmc3_pins_hs: mmc3-hs-pins { 234 pinctrl-single,pins = < 235 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 236 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 237 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 238 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 239 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 240 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 241 >; 242 }; 243 244 mmc3_pins_sdr12: mmc3-sdr12-pins { 245 pinctrl-single,pins = < 246 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 247 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 248 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 249 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 250 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 251 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 252 >; 253 }; 254 255 mmc3_pins_sdr25: mmc3-sdr25-pins { 256 pinctrl-single,pins = < 257 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 258 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 259 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 260 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 261 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 262 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 263 >; 264 }; 265 266 mmc3_pins_sdr50: mmc3-sdr50-pins { 267 pinctrl-single,pins = < 268 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 269 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 270 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 271 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 272 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 273 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 274 >; 275 }; 276 277 mmc4_pins_sdr12: mmc4-sdr12-pins { 278 pinctrl-single,pins = < 279 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 280 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 281 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 282 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 283 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 284 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 285 >; 286 }; 287 288 mmc4_pins_sdr25: mmc4-sdr25-pins { 289 pinctrl-single,pins = < 290 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 291 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 292 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 293 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 294 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 295 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 296 >; 297 }; 298}; 299 300&dra7_iodelay_core { 301 302 /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ 303 mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf { 304 pinctrl-pin-array = < 305 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */ 306 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ 307 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */ 308 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 309 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 310 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */ 311 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 312 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 313 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */ 314 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 315 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 316 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */ 317 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 318 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 319 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ 320 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 321 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 322 >; 323 }; 324 325 /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ 326 mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { 327 pinctrl-pin-array = < 328 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */ 329 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ 330 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ 331 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 332 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 333 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ 334 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 335 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 336 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ 337 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 338 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 339 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ 340 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 341 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 342 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ 343 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 344 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 345 >; 346 }; 347 348 /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ 349 mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { 350 pinctrl-pin-array = < 351 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */ 352 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 353 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 354 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 355 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 356 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 357 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 358 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 359 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 360 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 361 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 362 >; 363 }; 364 365 /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ 366 mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { 367 pinctrl-pin-array = < 368 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */ 369 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 370 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 371 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 372 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 373 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 374 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 375 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 376 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 377 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 378 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 379 >; 380 }; 381 382 /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ 383 mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf { 384 pinctrl-pin-array = < 385 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */ 386 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ 387 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */ 388 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 389 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */ 390 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 391 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */ 392 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 393 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */ 394 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */ 395 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 396 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */ 397 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 398 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */ 399 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 400 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */ 401 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 402 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */ 403 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 404 >; 405 }; 406 407 /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ 408 mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { 409 pinctrl-pin-array = < 410 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 411 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ 412 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 413 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 414 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 415 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 416 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 417 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 418 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */ 419 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 420 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 421 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 422 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 423 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 424 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 425 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 426 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 427 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 428 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 429 >; 430 }; 431 432 /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */ 433 mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf { 434 pinctrl-pin-array = < 435 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ 436 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 437 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ 438 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ 439 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 440 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 441 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ 442 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 443 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 444 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ 445 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 446 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 447 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ 448 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ 449 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ 450 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 451 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 452 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 453 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 454 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 455 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */ 456 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 457 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 458 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ 459 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 460 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 461 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ 462 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 463 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 464 >; 465 }; 466 467 /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */ 468 mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { 469 pinctrl-pin-array = < 470 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ 471 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 472 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ 473 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */ 474 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 475 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 476 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */ 477 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 478 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 479 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */ 480 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 481 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 482 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */ 483 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ 484 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */ 485 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 486 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 487 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 488 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 489 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 490 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */ 491 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 492 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 493 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */ 494 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 495 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 496 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ 497 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 498 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 499 >; 500 }; 501 502 /* Corresponds to MMC3_MANUAL1 in datamanual */ 503 mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf { 504 pinctrl-pin-array = < 505 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ 506 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ 507 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ 508 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ 509 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ 510 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ 511 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ 512 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ 513 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ 514 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ 515 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ 516 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ 517 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ 518 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ 519 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ 520 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ 521 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ 522 >; 523 }; 524 525 /* Corresponds to MMC3_MANUAL1 in datamanual */ 526 mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf { 527 pinctrl-pin-array = < 528 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ 529 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ 530 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ 531 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ 532 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ 533 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ 534 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ 535 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ 536 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ 537 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ 538 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ 539 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ 540 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ 541 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ 542 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ 543 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ 544 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ 545 >; 546 }; 547 548 /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ 549 mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf { 550 pinctrl-pin-array = < 551 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 552 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 553 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 554 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 555 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 556 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 557 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 558 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 559 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ 560 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 561 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 562 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ 563 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 564 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 565 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ 566 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 567 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 568 >; 569 }; 570 571 /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ 572 mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf { 573 pinctrl-pin-array = < 574 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 575 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 576 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 577 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 578 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 579 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 580 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 581 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 582 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ 583 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 584 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 585 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ 586 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 587 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 588 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ 589 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 590 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 591 >; 592 }; 593 594 /* Corresponds to MMC4_MANUAL1 in datamanual */ 595 mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { 596 pinctrl-pin-array = < 597 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 598 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 599 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 600 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 601 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 602 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 603 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 604 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 605 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ 606 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 607 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 608 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ 609 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 610 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 611 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ 612 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 613 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 614 >; 615 }; 616 617 /* Corresponds to MMC4_MANUAL1 in datamanual */ 618 mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { 619 pinctrl-pin-array = < 620 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 621 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 622 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 623 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 624 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 625 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 626 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 627 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 628 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ 629 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 630 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 631 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ 632 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 633 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 634 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ 635 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 636 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 637 >; 638 }; 639}; 640