1&l4_wkup { /* 0x44c00000 */ 2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; 3 power-domains = <&prm_wkup>; 4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 5 clock-names = "fck"; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 10 reg-names = "ap", "la", "ia0", "ia1"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 16 17 segment@0 { /* 0x44c00000 */ 18 compatible = "simple-pm-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 22 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 23 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 24 <0x00001400 0x00001400 0x000400>; /* ap 3 */ 25 }; 26 27 segment@100000 { /* 0x44d00000 */ 28 compatible = "simple-pm-bus"; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 32 <0x00004000 0x00104000 0x001000>, /* ap 5 */ 33 <0x00080000 0x00180000 0x002000>, /* ap 6 */ 34 <0x00082000 0x00182000 0x001000>; /* ap 7 */ 35 36 target-module@0 { /* 0x44d00000, ap 4 28.0 */ 37 compatible = "ti,sysc-omap4", "ti,sysc"; 38 reg = <0x0 0x4>; 39 reg-names = "rev"; 40 clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; 41 clock-names = "fck"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x00000000 0x00000000 0x4000>, 45 <0x00080000 0x00080000 0x2000>; 46 47 wkup_m3: cpu@0 { 48 compatible = "ti,am3352-wkup-m3"; 49 reg = <0x00000000 0x4000>, 50 <0x00080000 0x2000>; 51 reg-names = "umem", "dmem"; 52 resets = <&prm_wkup 3>; 53 reset-names = "rstctrl"; 54 ti,pm-firmware = "am335x-pm-firmware.elf"; 55 }; 56 }; 57 }; 58 59 segment@200000 { /* 0x44e00000 */ 60 compatible = "simple-pm-bus"; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ 64 <0x00002000 0x00202000 0x001000>, /* ap 9 */ 65 <0x00003000 0x00203000 0x001000>, /* ap 10 */ 66 <0x00004000 0x00204000 0x001000>, /* ap 11 */ 67 <0x00005000 0x00205000 0x001000>, /* ap 12 */ 68 <0x00006000 0x00206000 0x001000>, /* ap 13 */ 69 <0x00007000 0x00207000 0x001000>, /* ap 14 */ 70 <0x00008000 0x00208000 0x001000>, /* ap 15 */ 71 <0x00009000 0x00209000 0x001000>, /* ap 16 */ 72 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 73 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 74 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 75 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 76 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 77 <0x00010000 0x00210000 0x010000>, /* ap 22 */ 78 <0x00020000 0x00220000 0x010000>, /* ap 23 */ 79 <0x00030000 0x00230000 0x001000>, /* ap 24 */ 80 <0x00031000 0x00231000 0x001000>, /* ap 25 */ 81 <0x00032000 0x00232000 0x001000>, /* ap 26 */ 82 <0x00033000 0x00233000 0x001000>, /* ap 27 */ 83 <0x00034000 0x00234000 0x001000>, /* ap 28 */ 84 <0x00035000 0x00235000 0x001000>, /* ap 29 */ 85 <0x00036000 0x00236000 0x001000>, /* ap 30 */ 86 <0x00037000 0x00237000 0x001000>, /* ap 31 */ 87 <0x00038000 0x00238000 0x001000>, /* ap 32 */ 88 <0x00039000 0x00239000 0x001000>, /* ap 33 */ 89 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ 90 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ 91 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ 92 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ 93 <0x00040000 0x00240000 0x040000>, /* ap 38 */ 94 <0x00080000 0x00280000 0x001000>; /* ap 39 */ 95 96 target-module@0 { /* 0x44e00000, ap 8 58.0 */ 97 compatible = "ti,sysc-omap4", "ti,sysc"; 98 reg = <0 0x4>; 99 reg-names = "rev"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0x0 0x0 0x2000>; 103 104 prcm: prcm@0 { 105 compatible = "ti,am3-prcm", "simple-bus"; 106 reg = <0 0x2000>; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0 0x2000>; 110 111 prcm_clocks: clocks { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 }; 115 116 prcm_clockdomains: clockdomains { 117 }; 118 }; 119 }; 120 121 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 122 compatible = "ti,sysc"; 123 status = "disabled"; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0x0 0x3000 0x1000>; 127 }; 128 129 target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 130 compatible = "ti,sysc"; 131 status = "disabled"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges = <0x0 0x5000 0x1000>; 135 }; 136 137 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 138 compatible = "ti,sysc-omap2", "ti,sysc"; 139 reg = <0x7000 0x4>, 140 <0x7010 0x4>, 141 <0x7114 0x4>; 142 reg-names = "rev", "sysc", "syss"; 143 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 144 SYSC_OMAP2_SOFTRESET | 145 SYSC_OMAP2_AUTOIDLE)>; 146 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 147 <SYSC_IDLE_NO>, 148 <SYSC_IDLE_SMART>, 149 <SYSC_IDLE_SMART_WKUP>; 150 ti,syss-mask = <1>; 151 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 152 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, 153 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; 154 clock-names = "fck", "dbclk"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 ranges = <0x0 0x7000 0x1000>; 158 159 gpio0: gpio@0 { 160 compatible = "ti,omap4-gpio"; 161 gpio-ranges = <&am33xx_pinmux 0 82 8>, 162 <&am33xx_pinmux 8 52 4>, 163 <&am33xx_pinmux 12 94 4>, 164 <&am33xx_pinmux 16 71 2>, 165 <&am33xx_pinmux 18 135 1>, 166 <&am33xx_pinmux 19 108 2>, 167 <&am33xx_pinmux 21 73 1>, 168 <&am33xx_pinmux 22 8 2>, 169 <&am33xx_pinmux 26 10 2>, 170 <&am33xx_pinmux 28 74 1>, 171 <&am33xx_pinmux 29 81 1>, 172 <&am33xx_pinmux 30 28 2>; 173 gpio-controller; 174 #gpio-cells = <2>; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 reg = <0x0 0x1000>; 178 interrupts = <96>; 179 }; 180 }; 181 182 target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 183 compatible = "ti,sysc-omap2", "ti,sysc"; 184 reg = <0x9050 0x4>, 185 <0x9054 0x4>, 186 <0x9058 0x4>; 187 reg-names = "rev", "sysc", "syss"; 188 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 189 SYSC_OMAP2_SOFTRESET | 190 SYSC_OMAP2_AUTOIDLE)>; 191 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 192 <SYSC_IDLE_NO>, 193 <SYSC_IDLE_SMART>, 194 <SYSC_IDLE_SMART_WKUP>; 195 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 196 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; 197 clock-names = "fck"; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0x0 0x9000 0x1000>; 201 202 uart0: serial@0 { 203 compatible = "ti,am3352-uart", "ti,omap3-uart"; 204 clock-frequency = <48000000>; 205 reg = <0x0 0x1000>; 206 interrupts = <72>; 207 status = "disabled"; 208 dmas = <&edma 26 0>, <&edma 27 0>; 209 dma-names = "tx", "rx"; 210 }; 211 }; 212 213 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 214 compatible = "ti,sysc-omap2", "ti,sysc"; 215 reg = <0xb000 0x8>, 216 <0xb010 0x8>, 217 <0xb090 0x8>; 218 reg-names = "rev", "sysc", "syss"; 219 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 220 SYSC_OMAP2_ENAWAKEUP | 221 SYSC_OMAP2_SOFTRESET | 222 SYSC_OMAP2_AUTOIDLE)>; 223 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 224 <SYSC_IDLE_NO>, 225 <SYSC_IDLE_SMART>, 226 <SYSC_IDLE_SMART_WKUP>; 227 ti,syss-mask = <1>; 228 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 229 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; 230 clock-names = "fck"; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 ranges = <0x0 0xb000 0x1000>; 234 235 i2c0: i2c@0 { 236 compatible = "ti,omap4-i2c"; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 reg = <0x0 0x1000>; 240 interrupts = <70>; 241 status = "disabled"; 242 }; 243 }; 244 245 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 246 compatible = "ti,sysc-omap4", "ti,sysc"; 247 reg = <0xd000 0x4>, 248 <0xd010 0x4>; 249 reg-names = "rev", "sysc"; 250 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 251 <SYSC_IDLE_NO>, 252 <SYSC_IDLE_SMART>, 253 <SYSC_IDLE_SMART_WKUP>; 254 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 255 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; 256 clock-names = "fck"; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges = <0x00000000 0x0000d000 0x00001000>, 260 <0x00001000 0x0000e000 0x00001000>; 261 262 tscadc: tscadc@0 { 263 compatible = "ti,am3359-tscadc"; 264 reg = <0x0 0x1000>; 265 interrupts = <16>; 266 clocks = <&adc_tsc_fck>; 267 clock-names = "fck"; 268 status = "disabled"; 269 dmas = <&edma 53 0>, <&edma 57 0>; 270 dma-names = "fifo0", "fifo1"; 271 272 tsc { 273 compatible = "ti,am3359-tsc"; 274 }; 275 am335x_adc: adc { 276 #io-channel-cells = <1>; 277 compatible = "ti,am3359-adc"; 278 }; 279 }; 280 }; 281 282 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 283 compatible = "ti,sysc-omap4", "ti,sysc"; 284 reg = <0x10000 0x4>; 285 reg-names = "rev"; 286 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; 287 clock-names = "fck"; 288 ti,no-idle; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 ranges = <0x00000000 0x00010000 0x00010000>, 292 <0x00010000 0x00020000 0x00010000>; 293 294 scm: scm@0 { 295 compatible = "ti,am3-scm", "simple-bus"; 296 reg = <0x0 0x2000>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 #pinctrl-cells = <1>; 300 ranges = <0 0 0x2000>; 301 302 am33xx_pinmux: pinmux@800 { 303 compatible = "pinctrl-single"; 304 reg = <0x800 0x238>; 305 #pinctrl-cells = <1>; 306 pinctrl-single,register-width = <32>; 307 pinctrl-single,function-mask = <0x7f>; 308 }; 309 310 scm_conf: scm_conf@0 { 311 compatible = "syscon", "simple-bus"; 312 reg = <0x0 0x800>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0 0 0x800>; 316 317 phy_gmii_sel: phy-gmii-sel { 318 compatible = "ti,am3352-phy-gmii-sel"; 319 reg = <0x650 0x4>; 320 #phy-cells = <2>; 321 }; 322 323 scm_clocks: clocks { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 }; 327 }; 328 329 usb_ctrl_mod: control@620 { 330 compatible = "ti,am335x-usb-ctrl-module"; 331 reg = <0x620 0x10>, 332 <0x648 0x4>; 333 reg-names = "phy_ctrl", "wakeup"; 334 }; 335 336 wkup_m3_ipc: wkup_m3_ipc@1324 { 337 compatible = "ti,am3352-wkup-m3-ipc"; 338 reg = <0x1324 0x24>; 339 interrupts = <78>; 340 ti,rproc = <&wkup_m3>; 341 mboxes = <&mailbox &mbox_wkupm3>; 342 }; 343 344 edma_xbar: dma-router@f90 { 345 compatible = "ti,am335x-edma-crossbar"; 346 reg = <0xf90 0x40>; 347 #dma-cells = <3>; 348 dma-requests = <32>; 349 dma-masters = <&edma>; 350 }; 351 352 scm_clockdomains: clockdomains { 353 }; 354 }; 355 }; 356 357 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ 358 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 359 reg = <0x31000 0x4>, 360 <0x31010 0x4>, 361 <0x31014 0x4>; 362 reg-names = "rev", "sysc", "syss"; 363 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 364 SYSC_OMAP2_SOFTRESET | 365 SYSC_OMAP2_AUTOIDLE)>; 366 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 367 <SYSC_IDLE_NO>, 368 <SYSC_IDLE_SMART>; 369 ti,syss-mask = <1>; 370 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 371 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; 372 clock-names = "fck"; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges = <0x0 0x31000 0x1000>; 376 377 timer1: timer@0 { 378 compatible = "ti,am335x-timer-1ms"; 379 reg = <0x0 0x400>; 380 interrupts = <67>; 381 ti,timer-alwon; 382 clocks = <&timer1_fck>; 383 clock-names = "fck"; 384 }; 385 }; 386 387 target-module@33000 { /* 0x44e33000, ap 27 18.0 */ 388 compatible = "ti,sysc"; 389 status = "disabled"; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 ranges = <0x0 0x33000 0x1000>; 393 }; 394 395 target-module@35000 { /* 0x44e35000, ap 29 50.0 */ 396 compatible = "ti,sysc-omap2", "ti,sysc"; 397 reg = <0x35000 0x4>, 398 <0x35010 0x4>, 399 <0x35014 0x4>; 400 reg-names = "rev", "sysc", "syss"; 401 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 402 SYSC_OMAP2_SOFTRESET)>; 403 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 404 <SYSC_IDLE_NO>, 405 <SYSC_IDLE_SMART>, 406 <SYSC_IDLE_SMART_WKUP>; 407 ti,syss-mask = <1>; 408 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 409 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 410 clock-names = "fck"; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges = <0x0 0x35000 0x1000>; 414 415 wdt2: wdt@0 { 416 compatible = "ti,omap3-wdt"; 417 reg = <0x0 0x1000>; 418 interrupts = <91>; 419 }; 420 }; 421 422 target-module@37000 { /* 0x44e37000, ap 31 08.0 */ 423 compatible = "ti,sysc"; 424 status = "disabled"; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 ranges = <0x0 0x37000 0x1000>; 428 }; 429 430 target-module@39000 { /* 0x44e39000, ap 33 02.0 */ 431 compatible = "ti,sysc"; 432 status = "disabled"; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 ranges = <0x0 0x39000 0x1000>; 436 }; 437 438 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ 439 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 440 reg = <0x3e074 0x4>, 441 <0x3e078 0x4>; 442 reg-names = "rev", "sysc"; 443 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 444 <SYSC_IDLE_NO>, 445 <SYSC_IDLE_SMART>, 446 <SYSC_IDLE_SMART_WKUP>; 447 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 448 power-domains = <&prm_rtc>; 449 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; 450 clock-names = "fck"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges = <0x0 0x3e000 0x1000>; 454 455 rtc: rtc@0 { 456 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 457 reg = <0x0 0x1000>; 458 interrupts = <75>, 459 <76>; 460 }; 461 }; 462 463 target-module@40000 { /* 0x44e40000, ap 38 68.0 */ 464 compatible = "ti,sysc"; 465 status = "disabled"; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 ranges = <0x0 0x40000 0x40000>; 469 }; 470 }; 471}; 472 473&l4_fw { /* 0x47c00000 */ 474 compatible = "ti,am33xx-l4-fw", "simple-bus"; 475 reg = <0x47c00000 0x800>, 476 <0x47c00800 0x800>, 477 <0x47c01000 0x400>; 478 reg-names = "ap", "la", "ia0"; 479 #address-cells = <1>; 480 #size-cells = <1>; 481 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ 482 483 segment@0 { /* 0x47c00000 */ 484 compatible = "simple-bus"; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 488 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 489 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 490 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ 491 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ 492 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ 493 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ 494 <0x00010000 0x00010000 0x001000>, /* ap 7 */ 495 <0x00011000 0x00011000 0x001000>, /* ap 8 */ 496 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ 497 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ 498 <0x00024000 0x00024000 0x001000>, /* ap 11 */ 499 <0x00025000 0x00025000 0x001000>, /* ap 12 */ 500 <0x00026000 0x00026000 0x001000>, /* ap 13 */ 501 <0x00027000 0x00027000 0x001000>, /* ap 14 */ 502 <0x00030000 0x00030000 0x001000>, /* ap 15 */ 503 <0x00031000 0x00031000 0x001000>, /* ap 16 */ 504 <0x00038000 0x00038000 0x001000>, /* ap 17 */ 505 <0x00039000 0x00039000 0x001000>, /* ap 18 */ 506 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ 507 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ 508 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 509 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ 510 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 511 <0x00040000 0x00040000 0x001000>, /* ap 24 */ 512 <0x00046000 0x00046000 0x001000>, /* ap 25 */ 513 <0x00047000 0x00047000 0x001000>, /* ap 26 */ 514 <0x00044000 0x00044000 0x001000>, /* ap 27 */ 515 <0x00045000 0x00045000 0x001000>, /* ap 28 */ 516 <0x00028000 0x00028000 0x001000>, /* ap 29 */ 517 <0x00029000 0x00029000 0x001000>, /* ap 30 */ 518 <0x00032000 0x00032000 0x001000>, /* ap 31 */ 519 <0x00033000 0x00033000 0x001000>, /* ap 32 */ 520 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ 521 <0x00041000 0x00041000 0x001000>, /* ap 34 */ 522 <0x00042000 0x00042000 0x001000>, /* ap 35 */ 523 <0x00043000 0x00043000 0x001000>, /* ap 36 */ 524 <0x00014000 0x00014000 0x001000>, /* ap 37 */ 525 <0x00015000 0x00015000 0x001000>; /* ap 38 */ 526 527 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 528 compatible = "ti,sysc"; 529 status = "disabled"; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges = <0x0 0xc000 0x1000>; 533 }; 534 535 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ 536 compatible = "ti,sysc"; 537 status = "disabled"; 538 #address-cells = <1>; 539 #size-cells = <1>; 540 ranges = <0x0 0xe000 0x1000>; 541 }; 542 543 target-module@10000 { /* 0x47c10000, ap 7 20.0 */ 544 compatible = "ti,sysc"; 545 status = "disabled"; 546 #address-cells = <1>; 547 #size-cells = <1>; 548 ranges = <0x0 0x10000 0x1000>; 549 }; 550 551 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ 552 compatible = "ti,sysc"; 553 status = "disabled"; 554 #address-cells = <1>; 555 #size-cells = <1>; 556 ranges = <0x0 0x14000 0x1000>; 557 }; 558 559 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ 560 compatible = "ti,sysc"; 561 status = "disabled"; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 ranges = <0x0 0x1a000 0x1000>; 565 }; 566 567 target-module@24000 { /* 0x47c24000, ap 11 28.0 */ 568 compatible = "ti,sysc"; 569 status = "disabled"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges = <0x0 0x24000 0x1000>; 573 }; 574 575 target-module@26000 { /* 0x47c26000, ap 13 30.0 */ 576 compatible = "ti,sysc"; 577 status = "disabled"; 578 #address-cells = <1>; 579 #size-cells = <1>; 580 ranges = <0x0 0x26000 0x1000>; 581 }; 582 583 target-module@28000 { /* 0x47c28000, ap 29 40.0 */ 584 compatible = "ti,sysc"; 585 status = "disabled"; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges = <0x0 0x28000 0x1000>; 589 }; 590 591 target-module@30000 { /* 0x47c30000, ap 15 14.0 */ 592 compatible = "ti,sysc"; 593 status = "disabled"; 594 #address-cells = <1>; 595 #size-cells = <1>; 596 ranges = <0x0 0x30000 0x1000>; 597 }; 598 599 target-module@32000 { /* 0x47c32000, ap 31 06.0 */ 600 compatible = "ti,sysc"; 601 status = "disabled"; 602 #address-cells = <1>; 603 #size-cells = <1>; 604 ranges = <0x0 0x32000 0x1000>; 605 }; 606 607 target-module@38000 { /* 0x47c38000, ap 17 18.0 */ 608 compatible = "ti,sysc"; 609 status = "disabled"; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges = <0x0 0x38000 0x1000>; 613 }; 614 615 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ 616 compatible = "ti,sysc"; 617 status = "disabled"; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 ranges = <0x0 0x3a000 0x1000>; 621 }; 622 623 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ 624 compatible = "ti,sysc"; 625 status = "disabled"; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 ranges = <0x0 0x3c000 0x1000>; 629 }; 630 631 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ 632 compatible = "ti,sysc"; 633 status = "disabled"; 634 #address-cells = <1>; 635 #size-cells = <1>; 636 ranges = <0x0 0x3e000 0x1000>; 637 }; 638 639 target-module@40000 { /* 0x47c40000, ap 24 02.0 */ 640 compatible = "ti,sysc"; 641 status = "disabled"; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 ranges = <0x0 0x40000 0x1000>; 645 }; 646 647 target-module@42000 { /* 0x47c42000, ap 35 34.0 */ 648 compatible = "ti,sysc"; 649 status = "disabled"; 650 #address-cells = <1>; 651 #size-cells = <1>; 652 ranges = <0x0 0x42000 0x1000>; 653 }; 654 655 target-module@44000 { /* 0x47c44000, ap 27 24.0 */ 656 compatible = "ti,sysc"; 657 status = "disabled"; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 ranges = <0x0 0x44000 0x1000>; 661 }; 662 663 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ 664 compatible = "ti,sysc"; 665 status = "disabled"; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 ranges = <0x0 0x46000 0x1000>; 669 }; 670 }; 671}; 672 673&l4_fast { /* 0x4a000000 */ 674 compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; 675 power-domains = <&prm_per>; 676 clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; 677 clock-names = "fck"; 678 reg = <0x4a000000 0x800>, 679 <0x4a000800 0x800>, 680 <0x4a001000 0x400>; 681 reg-names = "ap", "la", "ia0"; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 685 686 segment@0 { /* 0x4a000000 */ 687 compatible = "simple-pm-bus"; 688 #address-cells = <1>; 689 #size-cells = <1>; 690 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 691 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 692 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 693 <0x00100000 0x00100000 0x008000>, /* ap 3 */ 694 <0x00108000 0x00108000 0x001000>, /* ap 4 */ 695 <0x00180000 0x00180000 0x020000>, /* ap 5 */ 696 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ 697 <0x00200000 0x00200000 0x080000>, /* ap 7 */ 698 <0x00280000 0x00280000 0x001000>, /* ap 8 */ 699 <0x00300000 0x00300000 0x080000>, /* ap 9 */ 700 <0x00380000 0x00380000 0x001000>; /* ap 10 */ 701 702 target-module@100000 { /* 0x4a100000, ap 3 08.0 */ 703 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 704 reg = <0x101200 0x4>, 705 <0x101208 0x4>, 706 <0x101204 0x4>; 707 reg-names = "rev", "sysc", "syss"; 708 ti,sysc-mask = <0>; 709 ti,sysc-midle = <SYSC_IDLE_FORCE>, 710 <SYSC_IDLE_NO>; 711 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 712 <SYSC_IDLE_NO>; 713 ti,syss-mask = <1>; 714 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 715 clock-names = "fck"; 716 #address-cells = <1>; 717 #size-cells = <1>; 718 ranges = <0x0 0x100000 0x8000>; 719 720 mac: ethernet@0 { 721 compatible = "ti,am335x-cpsw","ti,cpsw"; 722 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 723 clock-names = "fck", "cpts"; 724 cpdma_channels = <8>; 725 ale_entries = <1024>; 726 bd_ram_size = <0x2000>; 727 mac_control = <0x20>; 728 slaves = <2>; 729 active_slave = <0>; 730 cpts_clock_mult = <0x80000000>; 731 cpts_clock_shift = <29>; 732 reg = <0x0 0x800 733 0x1200 0x100>; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 /* 737 * c0_rx_thresh_pend 738 * c0_rx_pend 739 * c0_tx_pend 740 * c0_misc_pend 741 */ 742 interrupts = <40>, <41>, <42>, <43>; 743 ranges = <0 0 0x8000>; 744 syscon = <&scm_conf>; 745 status = "disabled"; 746 747 davinci_mdio: mdio@1000 { 748 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 749 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 750 clock-names = "fck"; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 bus_freq = <1000000>; 754 reg = <0x1000 0x100>; 755 status = "disabled"; 756 }; 757 758 cpsw_emac0: slave@200 { 759 /* Filled in by U-Boot */ 760 mac-address = [ 00 00 00 00 00 00 ]; 761 phys = <&phy_gmii_sel 1 1>; 762 }; 763 764 cpsw_emac1: slave@300 { 765 /* Filled in by U-Boot */ 766 mac-address = [ 00 00 00 00 00 00 ]; 767 phys = <&phy_gmii_sel 2 1>; 768 }; 769 }; 770 771 mac_sw: switch@0 { 772 compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; 773 reg = <0x0 0x4000>; 774 ranges = <0 0 0x4000>; 775 clocks = <&cpsw_125mhz_gclk>; 776 clock-names = "fck"; 777 #address-cells = <1>; 778 #size-cells = <1>; 779 syscon = <&scm_conf>; 780 status = "disabled"; 781 782 interrupts = <40>, <41>, <42>, <43>; 783 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 784 785 ethernet-ports { 786 #address-cells = <1>; 787 #size-cells = <0>; 788 789 cpsw_port1: port@1 { 790 reg = <1>; 791 label = "port1"; 792 mac-address = [ 00 00 00 00 00 00 ]; 793 phys = <&phy_gmii_sel 1 1>; 794 }; 795 796 cpsw_port2: port@2 { 797 reg = <2>; 798 label = "port2"; 799 mac-address = [ 00 00 00 00 00 00 ]; 800 phys = <&phy_gmii_sel 2 1>; 801 }; 802 }; 803 804 davinci_mdio_sw: mdio@1000 { 805 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 806 clocks = <&cpsw_125mhz_gclk>; 807 clock-names = "fck"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 bus_freq = <1000000>; 811 reg = <0x1000 0x100>; 812 }; 813 814 cpts { 815 clocks = <&cpsw_cpts_rft_clk>; 816 clock-names = "cpts"; 817 }; 818 }; 819 }; 820 821 target-module@180000 { /* 0x4a180000, ap 5 10.0 */ 822 compatible = "ti,sysc"; 823 status = "disabled"; 824 #address-cells = <1>; 825 #size-cells = <1>; 826 ranges = <0x0 0x180000 0x20000>; 827 }; 828 829 target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 830 compatible = "ti,sysc"; 831 status = "disabled"; 832 #address-cells = <1>; 833 #size-cells = <1>; 834 ranges = <0x0 0x200000 0x80000>; 835 }; 836 837 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 838 compatible = "ti,sysc-pruss", "ti,sysc"; 839 reg = <0x326000 0x4>, 840 <0x326004 0x4>; 841 reg-names = "rev", "sysc"; 842 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 843 SYSC_PRUSS_SUB_MWAIT)>; 844 ti,sysc-midle = <SYSC_IDLE_FORCE>, 845 <SYSC_IDLE_NO>, 846 <SYSC_IDLE_SMART>; 847 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 848 <SYSC_IDLE_NO>, 849 <SYSC_IDLE_SMART>; 850 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; 851 clock-names = "fck"; 852 resets = <&prm_per 1>; 853 reset-names = "rstctrl"; 854 #address-cells = <1>; 855 #size-cells = <1>; 856 ranges = <0x0 0x300000 0x80000>; 857 status = "disabled"; 858 859 pruss: pruss@0 { 860 compatible = "ti,am3356-pruss"; 861 reg = <0x0 0x80000>; 862 #address-cells = <1>; 863 #size-cells = <1>; 864 ranges; 865 866 pruss_mem: memories@0 { 867 reg = <0x0 0x2000>, 868 <0x2000 0x2000>, 869 <0x10000 0x3000>; 870 reg-names = "dram0", "dram1", 871 "shrdram2"; 872 }; 873 874 pruss_cfg: cfg@26000 { 875 compatible = "ti,pruss-cfg", "syscon"; 876 reg = <0x26000 0x2000>; 877 #address-cells = <1>; 878 #size-cells = <1>; 879 ranges = <0x0 0x26000 0x2000>; 880 881 clocks { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 885 pruss_iepclk_mux: iepclk-mux@30 { 886 reg = <0x30>; 887 #clock-cells = <0>; 888 clocks = <&l3_gclk>, /* icss_iep_gclk */ 889 <&pruss_ocp_gclk>; /* icss_ocp_gclk */ 890 }; 891 }; 892 }; 893 894 pruss_mii_rt: mii-rt@32000 { 895 compatible = "ti,pruss-mii", "syscon"; 896 reg = <0x32000 0x58>; 897 }; 898 899 pruss_intc: interrupt-controller@20000 { 900 compatible = "ti,pruss-intc"; 901 reg = <0x20000 0x2000>; 902 interrupts = <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>; 903 interrupt-names = "host_intr0", "host_intr1", 904 "host_intr2", "host_intr3", 905 "host_intr4", "host_intr5", 906 "host_intr6", "host_intr7"; 907 interrupt-controller; 908 #interrupt-cells = <3>; 909 }; 910 911 pru0: pru@34000 { 912 compatible = "ti,am3356-pru"; 913 reg = <0x34000 0x2000>, 914 <0x22000 0x400>, 915 <0x22400 0x100>; 916 reg-names = "iram", "control", "debug"; 917 firmware-name = "am335x-pru0-fw"; 918 }; 919 920 pru1: pru@38000 { 921 compatible = "ti,am3356-pru"; 922 reg = <0x38000 0x2000>, 923 <0x24000 0x400>, 924 <0x24400 0x100>; 925 reg-names = "iram", "control", "debug"; 926 firmware-name = "am335x-pru1-fw"; 927 }; 928 929 pruss_mdio: mdio@32400 { 930 compatible = "ti,davinci_mdio"; 931 reg = <0x32400 0x90>; 932 clocks = <&dpll_core_m4_ck>; 933 clock-names = "fck"; 934 bus_freq = <1000000>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 status = "disabled"; 938 }; 939 }; 940 }; 941 }; 942}; 943 944&l4_mpuss { /* 0x4b140000 */ 945 compatible = "ti,am33xx-l4-mpuss", "simple-bus"; 946 reg = <0x4b144400 0x100>, 947 <0x4b144800 0x400>; 948 reg-names = "la", "ap"; 949 #address-cells = <1>; 950 #size-cells = <1>; 951 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ 952 953 segment@0 { /* 0x4b140000 */ 954 compatible = "simple-bus"; 955 #address-cells = <1>; 956 #size-cells = <1>; 957 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ 958 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 959 <0x00002000 0x00002000 0x001000>, /* ap 2 */ 960 <0x00004000 0x00004000 0x000400>, /* ap 3 */ 961 <0x00005000 0x00005000 0x000400>, /* ap 4 */ 962 <0x00000000 0x00000000 0x001000>, /* ap 5 */ 963 <0x00003000 0x00003000 0x001000>, /* ap 6 */ 964 <0x00000800 0x00000800 0x000800>; /* ap 7 */ 965 966 target-module@0 { /* 0x4b140000, ap 5 02.2 */ 967 compatible = "ti,sysc"; 968 status = "disabled"; 969 #address-cells = <1>; 970 #size-cells = <1>; 971 ranges = <0x00000000 0x00000000 0x00001000>, 972 <0x00001000 0x00001000 0x00001000>, 973 <0x00002000 0x00002000 0x00001000>; 974 }; 975 976 target-module@3000 { /* 0x4b143000, ap 6 04.0 */ 977 compatible = "ti,sysc"; 978 status = "disabled"; 979 #address-cells = <1>; 980 #size-cells = <1>; 981 ranges = <0x0 0x3000 0x1000>; 982 }; 983 }; 984}; 985 986&l4_per { /* 0x48000000 */ 987 compatible = "ti,am33xx-l4-per", "simple-pm-bus"; 988 power-domains = <&prm_per>; 989 clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; 990 clock-names = "fck"; 991 reg = <0x48000000 0x800>, 992 <0x48000800 0x800>, 993 <0x48001000 0x400>, 994 <0x48001400 0x400>, 995 <0x48001800 0x400>, 996 <0x48001c00 0x400>; 997 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 998 #address-cells = <1>; 999 #size-cells = <1>; 1000 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 1001 <0x00100000 0x48100000 0x100000>, /* segment 1 */ 1002 <0x00200000 0x48200000 0x100000>, /* segment 2 */ 1003 <0x00300000 0x48300000 0x100000>, /* segment 3 */ 1004 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 1005 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 1006 1007 segment@0 { /* 0x48000000 */ 1008 compatible = "simple-pm-bus"; 1009 #address-cells = <1>; 1010 #size-cells = <1>; 1011 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1012 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 1013 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 1014 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 1015 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 1016 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 1017 <0x00008000 0x00008000 0x001000>, /* ap 6 */ 1018 <0x00009000 0x00009000 0x001000>, /* ap 7 */ 1019 <0x00016000 0x00016000 0x001000>, /* ap 8 */ 1020 <0x00017000 0x00017000 0x001000>, /* ap 9 */ 1021 <0x00022000 0x00022000 0x001000>, /* ap 10 */ 1022 <0x00023000 0x00023000 0x001000>, /* ap 11 */ 1023 <0x00024000 0x00024000 0x001000>, /* ap 12 */ 1024 <0x00025000 0x00025000 0x001000>, /* ap 13 */ 1025 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ 1026 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ 1027 <0x00038000 0x00038000 0x002000>, /* ap 16 */ 1028 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ 1029 <0x00014000 0x00014000 0x001000>, /* ap 18 */ 1030 <0x00015000 0x00015000 0x001000>, /* ap 19 */ 1031 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ 1032 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 1033 <0x00040000 0x00040000 0x001000>, /* ap 22 */ 1034 <0x00041000 0x00041000 0x001000>, /* ap 23 */ 1035 <0x00042000 0x00042000 0x001000>, /* ap 24 */ 1036 <0x00043000 0x00043000 0x001000>, /* ap 25 */ 1037 <0x00044000 0x00044000 0x001000>, /* ap 26 */ 1038 <0x00045000 0x00045000 0x001000>, /* ap 27 */ 1039 <0x00046000 0x00046000 0x001000>, /* ap 28 */ 1040 <0x00047000 0x00047000 0x001000>, /* ap 29 */ 1041 <0x00048000 0x00048000 0x001000>, /* ap 30 */ 1042 <0x00049000 0x00049000 0x001000>, /* ap 31 */ 1043 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ 1044 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ 1045 <0x00050000 0x00050000 0x002000>, /* ap 34 */ 1046 <0x00052000 0x00052000 0x001000>, /* ap 35 */ 1047 <0x00060000 0x00060000 0x001000>, /* ap 36 */ 1048 <0x00061000 0x00061000 0x001000>, /* ap 37 */ 1049 <0x00080000 0x00080000 0x010000>, /* ap 38 */ 1050 <0x00090000 0x00090000 0x001000>, /* ap 39 */ 1051 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ 1052 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ 1053 <0x00030000 0x00030000 0x001000>, /* ap 77 */ 1054 <0x00031000 0x00031000 0x001000>, /* ap 78 */ 1055 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ 1056 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ 1057 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ 1058 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ 1059 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ 1060 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ 1061 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ 1062 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ 1063 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 1064 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 1065 1066 target-module@8000 { /* 0x48008000, ap 6 10.0 */ 1067 compatible = "ti,sysc"; 1068 status = "disabled"; 1069 #address-cells = <1>; 1070 #size-cells = <1>; 1071 ranges = <0x0 0x8000 0x1000>; 1072 }; 1073 1074 target-module@14000 { /* 0x48014000, ap 18 58.0 */ 1075 compatible = "ti,sysc"; 1076 status = "disabled"; 1077 #address-cells = <1>; 1078 #size-cells = <1>; 1079 ranges = <0x0 0x14000 0x1000>; 1080 }; 1081 1082 target-module@16000 { /* 0x48016000, ap 8 3c.0 */ 1083 compatible = "ti,sysc"; 1084 status = "disabled"; 1085 #address-cells = <1>; 1086 #size-cells = <1>; 1087 ranges = <0x0 0x16000 0x1000>; 1088 }; 1089 1090 target-module@22000 { /* 0x48022000, ap 10 12.0 */ 1091 compatible = "ti,sysc-omap2", "ti,sysc"; 1092 reg = <0x22050 0x4>, 1093 <0x22054 0x4>, 1094 <0x22058 0x4>; 1095 reg-names = "rev", "sysc", "syss"; 1096 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1097 SYSC_OMAP2_SOFTRESET | 1098 SYSC_OMAP2_AUTOIDLE)>; 1099 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1100 <SYSC_IDLE_NO>, 1101 <SYSC_IDLE_SMART>, 1102 <SYSC_IDLE_SMART_WKUP>; 1103 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1104 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; 1105 clock-names = "fck"; 1106 #address-cells = <1>; 1107 #size-cells = <1>; 1108 ranges = <0x0 0x22000 0x1000>; 1109 1110 uart1: serial@0 { 1111 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1112 clock-frequency = <48000000>; 1113 reg = <0x0 0x1000>; 1114 interrupts = <73>; 1115 status = "disabled"; 1116 dmas = <&edma 28 0>, <&edma 29 0>; 1117 dma-names = "tx", "rx"; 1118 }; 1119 }; 1120 1121 target-module@24000 { /* 0x48024000, ap 12 14.0 */ 1122 compatible = "ti,sysc-omap2", "ti,sysc"; 1123 reg = <0x24050 0x4>, 1124 <0x24054 0x4>, 1125 <0x24058 0x4>; 1126 reg-names = "rev", "sysc", "syss"; 1127 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1128 SYSC_OMAP2_SOFTRESET | 1129 SYSC_OMAP2_AUTOIDLE)>; 1130 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1131 <SYSC_IDLE_NO>, 1132 <SYSC_IDLE_SMART>, 1133 <SYSC_IDLE_SMART_WKUP>; 1134 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1135 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; 1136 clock-names = "fck"; 1137 #address-cells = <1>; 1138 #size-cells = <1>; 1139 ranges = <0x0 0x24000 0x1000>; 1140 1141 uart2: serial@0 { 1142 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1143 clock-frequency = <48000000>; 1144 reg = <0x0 0x1000>; 1145 interrupts = <74>; 1146 status = "disabled"; 1147 dmas = <&edma 30 0>, <&edma 31 0>; 1148 dma-names = "tx", "rx"; 1149 }; 1150 }; 1151 1152 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ 1153 compatible = "ti,sysc-omap2", "ti,sysc"; 1154 reg = <0x2a000 0x8>, 1155 <0x2a010 0x8>, 1156 <0x2a090 0x8>; 1157 reg-names = "rev", "sysc", "syss"; 1158 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1159 SYSC_OMAP2_ENAWAKEUP | 1160 SYSC_OMAP2_SOFTRESET | 1161 SYSC_OMAP2_AUTOIDLE)>; 1162 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1163 <SYSC_IDLE_NO>, 1164 <SYSC_IDLE_SMART>, 1165 <SYSC_IDLE_SMART_WKUP>; 1166 ti,syss-mask = <1>; 1167 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1168 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; 1169 clock-names = "fck"; 1170 #address-cells = <1>; 1171 #size-cells = <1>; 1172 ranges = <0x0 0x2a000 0x1000>; 1173 1174 i2c1: i2c@0 { 1175 compatible = "ti,omap4-i2c"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 reg = <0x0 0x1000>; 1179 interrupts = <71>; 1180 status = "disabled"; 1181 }; 1182 }; 1183 1184 target-module@30000 { /* 0x48030000, ap 77 08.0 */ 1185 compatible = "ti,sysc-omap2", "ti,sysc"; 1186 reg = <0x30000 0x4>, 1187 <0x30110 0x4>, 1188 <0x30114 0x4>; 1189 reg-names = "rev", "sysc", "syss"; 1190 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1191 SYSC_OMAP2_SOFTRESET | 1192 SYSC_OMAP2_AUTOIDLE)>; 1193 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1194 <SYSC_IDLE_NO>, 1195 <SYSC_IDLE_SMART>; 1196 ti,syss-mask = <1>; 1197 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1198 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; 1199 clock-names = "fck"; 1200 #address-cells = <1>; 1201 #size-cells = <1>; 1202 ranges = <0x0 0x30000 0x1000>; 1203 1204 spi0: spi@0 { 1205 compatible = "ti,omap4-mcspi"; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 reg = <0x0 0x400>; 1209 interrupts = <65>; 1210 ti,spi-num-cs = <2>; 1211 dmas = <&edma 16 0 1212 &edma 17 0 1213 &edma 18 0 1214 &edma 19 0>; 1215 dma-names = "tx0", "rx0", "tx1", "rx1"; 1216 status = "disabled"; 1217 }; 1218 }; 1219 1220 target-module@38000 { /* 0x48038000, ap 16 02.0 */ 1221 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1222 reg = <0x38000 0x4>, 1223 <0x38004 0x4>; 1224 reg-names = "rev", "sysc"; 1225 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1226 <SYSC_IDLE_NO>, 1227 <SYSC_IDLE_SMART>; 1228 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1229 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; 1230 clock-names = "fck"; 1231 #address-cells = <1>; 1232 #size-cells = <1>; 1233 ranges = <0x0 0x38000 0x2000>, 1234 <0x46000000 0x46000000 0x400000>; 1235 1236 mcasp0: mcasp@0 { 1237 compatible = "ti,am33xx-mcasp-audio"; 1238 reg = <0x0 0x2000>, 1239 <0x46000000 0x400000>; 1240 reg-names = "mpu", "dat"; 1241 interrupts = <80>, <81>; 1242 interrupt-names = "tx", "rx"; 1243 status = "disabled"; 1244 dmas = <&edma 8 2>, 1245 <&edma 9 2>; 1246 dma-names = "tx", "rx"; 1247 }; 1248 }; 1249 1250 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ 1251 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1252 reg = <0x3c000 0x4>, 1253 <0x3c004 0x4>; 1254 reg-names = "rev", "sysc"; 1255 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1256 <SYSC_IDLE_NO>, 1257 <SYSC_IDLE_SMART>; 1258 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1259 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; 1260 clock-names = "fck"; 1261 #address-cells = <1>; 1262 #size-cells = <1>; 1263 ranges = <0x0 0x3c000 0x2000>, 1264 <0x46400000 0x46400000 0x400000>; 1265 1266 mcasp1: mcasp@0 { 1267 compatible = "ti,am33xx-mcasp-audio"; 1268 reg = <0x0 0x2000>, 1269 <0x46400000 0x400000>; 1270 reg-names = "mpu", "dat"; 1271 interrupts = <82>, <83>; 1272 interrupt-names = "tx", "rx"; 1273 status = "disabled"; 1274 dmas = <&edma 10 2>, 1275 <&edma 11 2>; 1276 dma-names = "tx", "rx"; 1277 }; 1278 }; 1279 1280 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ 1281 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1282 reg = <0x40000 0x4>, 1283 <0x40010 0x4>, 1284 <0x40014 0x4>; 1285 reg-names = "rev", "sysc", "syss"; 1286 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1287 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1288 <SYSC_IDLE_NO>, 1289 <SYSC_IDLE_SMART>, 1290 <SYSC_IDLE_SMART_WKUP>; 1291 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1292 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; 1293 clock-names = "fck"; 1294 #address-cells = <1>; 1295 #size-cells = <1>; 1296 ranges = <0x0 0x40000 0x1000>; 1297 1298 timer2: timer@0 { 1299 compatible = "ti,am335x-timer"; 1300 reg = <0x0 0x400>; 1301 interrupts = <68>; 1302 clocks = <&timer2_fck>; 1303 clock-names = "fck"; 1304 }; 1305 }; 1306 1307 target-module@42000 { /* 0x48042000, ap 24 1c.0 */ 1308 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1309 reg = <0x42000 0x4>, 1310 <0x42010 0x4>, 1311 <0x42014 0x4>; 1312 reg-names = "rev", "sysc", "syss"; 1313 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1314 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1315 <SYSC_IDLE_NO>, 1316 <SYSC_IDLE_SMART>, 1317 <SYSC_IDLE_SMART_WKUP>; 1318 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1319 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; 1320 clock-names = "fck"; 1321 #address-cells = <1>; 1322 #size-cells = <1>; 1323 ranges = <0x0 0x42000 0x1000>; 1324 1325 timer3: timer@0 { 1326 compatible = "ti,am335x-timer"; 1327 reg = <0x0 0x400>; 1328 interrupts = <69>; 1329 clocks = <&timer3_fck>; 1330 clock-names = "fck"; 1331 }; 1332 }; 1333 1334 target-module@44000 { /* 0x48044000, ap 26 26.0 */ 1335 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1336 reg = <0x44000 0x4>, 1337 <0x44010 0x4>, 1338 <0x44014 0x4>; 1339 reg-names = "rev", "sysc", "syss"; 1340 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1341 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1342 <SYSC_IDLE_NO>, 1343 <SYSC_IDLE_SMART>, 1344 <SYSC_IDLE_SMART_WKUP>; 1345 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1346 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; 1347 clock-names = "fck"; 1348 #address-cells = <1>; 1349 #size-cells = <1>; 1350 ranges = <0x0 0x44000 0x1000>; 1351 1352 timer4: timer@0 { 1353 compatible = "ti,am335x-timer"; 1354 reg = <0x0 0x400>; 1355 interrupts = <92>; 1356 ti,timer-pwm; 1357 clocks = <&timer4_fck>; 1358 clock-names = "fck"; 1359 }; 1360 }; 1361 1362 target-module@46000 { /* 0x48046000, ap 28 28.0 */ 1363 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1364 reg = <0x46000 0x4>, 1365 <0x46010 0x4>, 1366 <0x46014 0x4>; 1367 reg-names = "rev", "sysc", "syss"; 1368 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1369 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1370 <SYSC_IDLE_NO>, 1371 <SYSC_IDLE_SMART>, 1372 <SYSC_IDLE_SMART_WKUP>; 1373 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1374 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; 1375 clock-names = "fck"; 1376 #address-cells = <1>; 1377 #size-cells = <1>; 1378 ranges = <0x0 0x46000 0x1000>; 1379 1380 timer5: timer@0 { 1381 compatible = "ti,am335x-timer"; 1382 reg = <0x0 0x400>; 1383 interrupts = <93>; 1384 ti,timer-pwm; 1385 clocks = <&timer5_fck>; 1386 clock-names = "fck"; 1387 }; 1388 }; 1389 1390 target-module@48000 { /* 0x48048000, ap 30 22.0 */ 1391 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1392 reg = <0x48000 0x4>, 1393 <0x48010 0x4>, 1394 <0x48014 0x4>; 1395 reg-names = "rev", "sysc", "syss"; 1396 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1397 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1398 <SYSC_IDLE_NO>, 1399 <SYSC_IDLE_SMART>, 1400 <SYSC_IDLE_SMART_WKUP>; 1401 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1402 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; 1403 clock-names = "fck"; 1404 #address-cells = <1>; 1405 #size-cells = <1>; 1406 ranges = <0x0 0x48000 0x1000>; 1407 1408 timer6: timer@0 { 1409 compatible = "ti,am335x-timer"; 1410 reg = <0x0 0x400>; 1411 interrupts = <94>; 1412 ti,timer-pwm; 1413 clocks = <&timer6_fck>; 1414 clock-names = "fck"; 1415 }; 1416 }; 1417 1418 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ 1419 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1420 reg = <0x4a000 0x4>, 1421 <0x4a010 0x4>, 1422 <0x4a014 0x4>; 1423 reg-names = "rev", "sysc", "syss"; 1424 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1425 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1426 <SYSC_IDLE_NO>, 1427 <SYSC_IDLE_SMART>, 1428 <SYSC_IDLE_SMART_WKUP>; 1429 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1430 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; 1431 clock-names = "fck"; 1432 #address-cells = <1>; 1433 #size-cells = <1>; 1434 ranges = <0x0 0x4a000 0x1000>; 1435 1436 timer7: timer@0 { 1437 compatible = "ti,am335x-timer"; 1438 reg = <0x0 0x400>; 1439 interrupts = <95>; 1440 ti,timer-pwm; 1441 clocks = <&timer7_fck>; 1442 clock-names = "fck"; 1443 }; 1444 }; 1445 1446 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ 1447 compatible = "ti,sysc-omap2", "ti,sysc"; 1448 reg = <0x4c000 0x4>, 1449 <0x4c010 0x4>, 1450 <0x4c114 0x4>; 1451 reg-names = "rev", "sysc", "syss"; 1452 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1453 SYSC_OMAP2_SOFTRESET | 1454 SYSC_OMAP2_AUTOIDLE)>; 1455 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1456 <SYSC_IDLE_NO>, 1457 <SYSC_IDLE_SMART>, 1458 <SYSC_IDLE_SMART_WKUP>; 1459 ti,syss-mask = <1>; 1460 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1461 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, 1462 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; 1463 clock-names = "fck", "dbclk"; 1464 #address-cells = <1>; 1465 #size-cells = <1>; 1466 ranges = <0x0 0x4c000 0x1000>; 1467 1468 gpio1: gpio@0 { 1469 compatible = "ti,omap4-gpio"; 1470 gpio-ranges = <&am33xx_pinmux 0 0 8>, 1471 <&am33xx_pinmux 8 90 4>, 1472 <&am33xx_pinmux 12 12 16>, 1473 <&am33xx_pinmux 28 30 4>; 1474 gpio-controller; 1475 #gpio-cells = <2>; 1476 interrupt-controller; 1477 #interrupt-cells = <2>; 1478 reg = <0x0 0x1000>; 1479 interrupts = <98>; 1480 }; 1481 }; 1482 1483 target-module@50000 { /* 0x48050000, ap 34 2c.0 */ 1484 compatible = "ti,sysc"; 1485 status = "disabled"; 1486 #address-cells = <1>; 1487 #size-cells = <1>; 1488 ranges = <0x0 0x50000 0x2000>; 1489 }; 1490 1491 target-module@60000 { /* 0x48060000, ap 36 0c.0 */ 1492 compatible = "ti,sysc-omap2", "ti,sysc"; 1493 reg = <0x602fc 0x4>, 1494 <0x60110 0x4>, 1495 <0x60114 0x4>; 1496 reg-names = "rev", "sysc", "syss"; 1497 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1498 SYSC_OMAP2_ENAWAKEUP | 1499 SYSC_OMAP2_SOFTRESET | 1500 SYSC_OMAP2_AUTOIDLE)>; 1501 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1502 <SYSC_IDLE_NO>, 1503 <SYSC_IDLE_SMART>; 1504 ti,syss-mask = <1>; 1505 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1506 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; 1507 clock-names = "fck"; 1508 #address-cells = <1>; 1509 #size-cells = <1>; 1510 ranges = <0x0 0x60000 0x1000>; 1511 1512 mmc1: mmc@0 { 1513 compatible = "ti,am335-sdhci"; 1514 ti,needs-special-reset; 1515 dmas = <&edma 24 0>, <&edma 25 0>; 1516 dma-names = "tx", "rx"; 1517 interrupts = <64>; 1518 reg = <0x0 0x1000>; 1519 status = "disabled"; 1520 }; 1521 }; 1522 1523 target-module@80000 { /* 0x48080000, ap 38 18.0 */ 1524 compatible = "ti,sysc-omap2", "ti,sysc"; 1525 reg = <0x80000 0x4>, 1526 <0x80010 0x4>, 1527 <0x80014 0x4>; 1528 reg-names = "rev", "sysc", "syss"; 1529 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1530 SYSC_OMAP2_SOFTRESET | 1531 SYSC_OMAP2_AUTOIDLE)>; 1532 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1533 <SYSC_IDLE_NO>, 1534 <SYSC_IDLE_SMART>; 1535 ti,syss-mask = <1>; 1536 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1537 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; 1538 clock-names = "fck"; 1539 #address-cells = <1>; 1540 #size-cells = <1>; 1541 ranges = <0x0 0x80000 0x10000>; 1542 1543 elm: elm@0 { 1544 compatible = "ti,am3352-elm"; 1545 reg = <0x0 0x2000>; 1546 interrupts = <4>; 1547 status = "disabled"; 1548 }; 1549 }; 1550 1551 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ 1552 compatible = "ti,sysc"; 1553 status = "disabled"; 1554 #address-cells = <1>; 1555 #size-cells = <1>; 1556 ranges = <0x0 0xa0000 0x10000>; 1557 }; 1558 1559 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ 1560 compatible = "ti,sysc-omap4", "ti,sysc"; 1561 reg = <0xc8000 0x4>, 1562 <0xc8010 0x4>; 1563 reg-names = "rev", "sysc"; 1564 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1565 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1566 <SYSC_IDLE_NO>, 1567 <SYSC_IDLE_SMART>; 1568 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1569 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; 1570 clock-names = "fck"; 1571 #address-cells = <1>; 1572 #size-cells = <1>; 1573 ranges = <0x0 0xc8000 0x1000>; 1574 1575 mailbox: mailbox@0 { 1576 compatible = "ti,omap4-mailbox"; 1577 reg = <0x0 0x200>; 1578 interrupts = <77>; 1579 #mbox-cells = <1>; 1580 ti,mbox-num-users = <4>; 1581 ti,mbox-num-fifos = <8>; 1582 mbox_wkupm3: mbox-wkup-m3 { 1583 ti,mbox-send-noirq; 1584 ti,mbox-tx = <0 0 0>; 1585 ti,mbox-rx = <0 0 3>; 1586 }; 1587 }; 1588 }; 1589 1590 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ 1591 compatible = "ti,sysc-omap2", "ti,sysc"; 1592 reg = <0xca000 0x4>, 1593 <0xca010 0x4>, 1594 <0xca014 0x4>; 1595 reg-names = "rev", "sysc", "syss"; 1596 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1597 SYSC_OMAP2_ENAWAKEUP | 1598 SYSC_OMAP2_SOFTRESET | 1599 SYSC_OMAP2_AUTOIDLE)>; 1600 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1601 <SYSC_IDLE_NO>, 1602 <SYSC_IDLE_SMART>; 1603 ti,syss-mask = <1>; 1604 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1605 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; 1606 clock-names = "fck"; 1607 #address-cells = <1>; 1608 #size-cells = <1>; 1609 ranges = <0x0 0xca000 0x1000>; 1610 1611 hwspinlock: spinlock@0 { 1612 compatible = "ti,omap4-hwspinlock"; 1613 reg = <0x0 0x1000>; 1614 #hwlock-cells = <1>; 1615 }; 1616 }; 1617 1618 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ 1619 compatible = "ti,sysc"; 1620 status = "disabled"; 1621 #address-cells = <1>; 1622 #size-cells = <1>; 1623 ranges = <0x0 0xcc000 0x1000>; 1624 }; 1625 }; 1626 1627 segment@100000 { /* 0x48100000 */ 1628 compatible = "simple-pm-bus"; 1629 #address-cells = <1>; 1630 #size-cells = <1>; 1631 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ 1632 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ 1633 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ 1634 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ 1635 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ 1636 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ 1637 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ 1638 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ 1639 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ 1640 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ 1641 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ 1642 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ 1643 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ 1644 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ 1645 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ 1646 <0x000af000 0x001af000 0x001000>, /* ap 57 */ 1647 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ 1648 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ 1649 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ 1650 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ 1651 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ 1652 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ 1653 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ 1654 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ 1655 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ 1656 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ 1657 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ 1658 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ 1659 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ 1660 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ 1661 1662 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ 1663 compatible = "ti,sysc"; 1664 status = "disabled"; 1665 #address-cells = <1>; 1666 #size-cells = <1>; 1667 ranges = <0x0 0x8c000 0x1000>; 1668 }; 1669 1670 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ 1671 compatible = "ti,sysc"; 1672 status = "disabled"; 1673 #address-cells = <1>; 1674 #size-cells = <1>; 1675 ranges = <0x0 0x8e000 0x1000>; 1676 }; 1677 1678 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ 1679 compatible = "ti,sysc-omap2", "ti,sysc"; 1680 reg = <0x9c000 0x8>, 1681 <0x9c010 0x8>, 1682 <0x9c090 0x8>; 1683 reg-names = "rev", "sysc", "syss"; 1684 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1685 SYSC_OMAP2_ENAWAKEUP | 1686 SYSC_OMAP2_SOFTRESET | 1687 SYSC_OMAP2_AUTOIDLE)>; 1688 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1689 <SYSC_IDLE_NO>, 1690 <SYSC_IDLE_SMART>, 1691 <SYSC_IDLE_SMART_WKUP>; 1692 ti,syss-mask = <1>; 1693 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1694 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; 1695 clock-names = "fck"; 1696 #address-cells = <1>; 1697 #size-cells = <1>; 1698 ranges = <0x0 0x9c000 0x1000>; 1699 1700 i2c2: i2c@0 { 1701 compatible = "ti,omap4-i2c"; 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 reg = <0x0 0x1000>; 1705 interrupts = <30>; 1706 status = "disabled"; 1707 }; 1708 }; 1709 1710 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ 1711 compatible = "ti,sysc-omap2", "ti,sysc"; 1712 reg = <0xa0000 0x4>, 1713 <0xa0110 0x4>, 1714 <0xa0114 0x4>; 1715 reg-names = "rev", "sysc", "syss"; 1716 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1717 SYSC_OMAP2_SOFTRESET | 1718 SYSC_OMAP2_AUTOIDLE)>; 1719 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1720 <SYSC_IDLE_NO>, 1721 <SYSC_IDLE_SMART>; 1722 ti,syss-mask = <1>; 1723 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1724 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; 1725 clock-names = "fck"; 1726 #address-cells = <1>; 1727 #size-cells = <1>; 1728 ranges = <0x0 0xa0000 0x1000>; 1729 1730 spi1: spi@0 { 1731 compatible = "ti,omap4-mcspi"; 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 reg = <0x0 0x400>; 1735 interrupts = <125>; 1736 ti,spi-num-cs = <2>; 1737 dmas = <&edma 42 0 1738 &edma 43 0 1739 &edma 44 0 1740 &edma 45 0>; 1741 dma-names = "tx0", "rx0", "tx1", "rx1"; 1742 status = "disabled"; 1743 }; 1744 }; 1745 1746 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ 1747 compatible = "ti,sysc"; 1748 status = "disabled"; 1749 #address-cells = <1>; 1750 #size-cells = <1>; 1751 ranges = <0x0 0xa2000 0x1000>; 1752 }; 1753 1754 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ 1755 compatible = "ti,sysc"; 1756 status = "disabled"; 1757 #address-cells = <1>; 1758 #size-cells = <1>; 1759 ranges = <0x0 0xa4000 0x1000>; 1760 }; 1761 1762 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ 1763 compatible = "ti,sysc-omap2", "ti,sysc"; 1764 reg = <0xa6050 0x4>, 1765 <0xa6054 0x4>, 1766 <0xa6058 0x4>; 1767 reg-names = "rev", "sysc", "syss"; 1768 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1769 SYSC_OMAP2_SOFTRESET | 1770 SYSC_OMAP2_AUTOIDLE)>; 1771 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1772 <SYSC_IDLE_NO>, 1773 <SYSC_IDLE_SMART>, 1774 <SYSC_IDLE_SMART_WKUP>; 1775 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1776 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; 1777 clock-names = "fck"; 1778 #address-cells = <1>; 1779 #size-cells = <1>; 1780 ranges = <0x0 0xa6000 0x1000>; 1781 1782 uart3: serial@0 { 1783 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1784 clock-frequency = <48000000>; 1785 reg = <0x0 0x1000>; 1786 interrupts = <44>; 1787 status = "disabled"; 1788 }; 1789 }; 1790 1791 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ 1792 compatible = "ti,sysc-omap2", "ti,sysc"; 1793 reg = <0xa8050 0x4>, 1794 <0xa8054 0x4>, 1795 <0xa8058 0x4>; 1796 reg-names = "rev", "sysc", "syss"; 1797 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1798 SYSC_OMAP2_SOFTRESET | 1799 SYSC_OMAP2_AUTOIDLE)>; 1800 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1801 <SYSC_IDLE_NO>, 1802 <SYSC_IDLE_SMART>, 1803 <SYSC_IDLE_SMART_WKUP>; 1804 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1805 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; 1806 clock-names = "fck"; 1807 #address-cells = <1>; 1808 #size-cells = <1>; 1809 ranges = <0x0 0xa8000 0x1000>; 1810 1811 uart4: serial@0 { 1812 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1813 clock-frequency = <48000000>; 1814 reg = <0x0 0x1000>; 1815 interrupts = <45>; 1816 status = "disabled"; 1817 }; 1818 }; 1819 1820 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ 1821 compatible = "ti,sysc-omap2", "ti,sysc"; 1822 reg = <0xaa050 0x4>, 1823 <0xaa054 0x4>, 1824 <0xaa058 0x4>; 1825 reg-names = "rev", "sysc", "syss"; 1826 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1827 SYSC_OMAP2_SOFTRESET | 1828 SYSC_OMAP2_AUTOIDLE)>; 1829 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1830 <SYSC_IDLE_NO>, 1831 <SYSC_IDLE_SMART>, 1832 <SYSC_IDLE_SMART_WKUP>; 1833 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1834 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; 1835 clock-names = "fck"; 1836 #address-cells = <1>; 1837 #size-cells = <1>; 1838 ranges = <0x0 0xaa000 0x1000>; 1839 1840 uart5: serial@0 { 1841 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1842 clock-frequency = <48000000>; 1843 reg = <0x0 0x1000>; 1844 interrupts = <46>; 1845 status = "disabled"; 1846 }; 1847 }; 1848 1849 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ 1850 compatible = "ti,sysc-omap2", "ti,sysc"; 1851 reg = <0xac000 0x4>, 1852 <0xac010 0x4>, 1853 <0xac114 0x4>; 1854 reg-names = "rev", "sysc", "syss"; 1855 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1856 SYSC_OMAP2_SOFTRESET | 1857 SYSC_OMAP2_AUTOIDLE)>; 1858 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1859 <SYSC_IDLE_NO>, 1860 <SYSC_IDLE_SMART>, 1861 <SYSC_IDLE_SMART_WKUP>; 1862 ti,syss-mask = <1>; 1863 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1864 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, 1865 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; 1866 clock-names = "fck", "dbclk"; 1867 #address-cells = <1>; 1868 #size-cells = <1>; 1869 ranges = <0x0 0xac000 0x1000>; 1870 1871 gpio2: gpio@0 { 1872 compatible = "ti,omap4-gpio"; 1873 gpio-ranges = <&am33xx_pinmux 0 34 18>, 1874 <&am33xx_pinmux 18 77 4>, 1875 <&am33xx_pinmux 22 56 10>; 1876 gpio-controller; 1877 #gpio-cells = <2>; 1878 interrupt-controller; 1879 #interrupt-cells = <2>; 1880 reg = <0x0 0x1000>; 1881 interrupts = <32>; 1882 }; 1883 }; 1884 1885 gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ 1886 compatible = "ti,sysc-omap2", "ti,sysc"; 1887 reg = <0xae000 0x4>, 1888 <0xae010 0x4>, 1889 <0xae114 0x4>; 1890 reg-names = "rev", "sysc", "syss"; 1891 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1892 SYSC_OMAP2_SOFTRESET | 1893 SYSC_OMAP2_AUTOIDLE)>; 1894 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1895 <SYSC_IDLE_NO>, 1896 <SYSC_IDLE_SMART>, 1897 <SYSC_IDLE_SMART_WKUP>; 1898 ti,syss-mask = <1>; 1899 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1900 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, 1901 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; 1902 clock-names = "fck", "dbclk"; 1903 #address-cells = <1>; 1904 #size-cells = <1>; 1905 ranges = <0x0 0xae000 0x1000>; 1906 1907 gpio3: gpio@0 { 1908 compatible = "ti,omap4-gpio"; 1909 gpio-ranges = <&am33xx_pinmux 0 66 5>, 1910 <&am33xx_pinmux 5 98 2>, 1911 <&am33xx_pinmux 7 75 2>, 1912 <&am33xx_pinmux 13 141 1>, 1913 <&am33xx_pinmux 14 100 8>; 1914 gpio-controller; 1915 #gpio-cells = <2>; 1916 interrupt-controller; 1917 #interrupt-cells = <2>; 1918 reg = <0x0 0x1000>; 1919 interrupts = <62>; 1920 }; 1921 }; 1922 1923 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ 1924 compatible = "ti,sysc"; 1925 status = "disabled"; 1926 #address-cells = <1>; 1927 #size-cells = <1>; 1928 ranges = <0x0 0xb0000 0x10000>; 1929 }; 1930 1931 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1932 compatible = "ti,sysc-omap4", "ti,sysc"; 1933 reg = <0xcc020 0x4>; 1934 reg-names = "rev"; 1935 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1936 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, 1937 <&dcan0_fck>; 1938 clock-names = "fck", "osc"; 1939 #address-cells = <1>; 1940 #size-cells = <1>; 1941 ranges = <0x0 0xcc000 0x2000>; 1942 1943 dcan0: can@0 { 1944 compatible = "ti,am3352-d_can"; 1945 reg = <0x0 0x2000>; 1946 clocks = <&dcan0_fck>; 1947 clock-names = "fck"; 1948 syscon-raminit = <&scm_conf 0x644 0>; 1949 interrupts = <52>; 1950 status = "disabled"; 1951 }; 1952 }; 1953 1954 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1955 compatible = "ti,sysc-omap4", "ti,sysc"; 1956 reg = <0xd0020 0x4>; 1957 reg-names = "rev"; 1958 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1959 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, 1960 <&dcan1_fck>; 1961 clock-names = "fck", "osc"; 1962 #address-cells = <1>; 1963 #size-cells = <1>; 1964 ranges = <0x0 0xd0000 0x2000>; 1965 1966 dcan1: can@0 { 1967 compatible = "ti,am3352-d_can"; 1968 reg = <0x0 0x2000>; 1969 clocks = <&dcan1_fck>; 1970 clock-names = "fck"; 1971 syscon-raminit = <&scm_conf 0x644 1>; 1972 interrupts = <55>; 1973 status = "disabled"; 1974 }; 1975 }; 1976 1977 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ 1978 compatible = "ti,sysc-omap2", "ti,sysc"; 1979 reg = <0xd82fc 0x4>, 1980 <0xd8110 0x4>, 1981 <0xd8114 0x4>; 1982 reg-names = "rev", "sysc", "syss"; 1983 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1984 SYSC_OMAP2_ENAWAKEUP | 1985 SYSC_OMAP2_SOFTRESET | 1986 SYSC_OMAP2_AUTOIDLE)>; 1987 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1988 <SYSC_IDLE_NO>, 1989 <SYSC_IDLE_SMART>; 1990 ti,syss-mask = <1>; 1991 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1992 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; 1993 clock-names = "fck"; 1994 #address-cells = <1>; 1995 #size-cells = <1>; 1996 ranges = <0x0 0xd8000 0x1000>; 1997 1998 mmc2: mmc@0 { 1999 compatible = "ti,am335-sdhci"; 2000 ti,needs-special-reset; 2001 dmas = <&edma 2 0 2002 &edma 3 0>; 2003 dma-names = "tx", "rx"; 2004 interrupts = <28>; 2005 reg = <0x0 0x1000>; 2006 status = "disabled"; 2007 }; 2008 }; 2009 }; 2010 2011 segment@200000 { /* 0x48200000 */ 2012 compatible = "simple-pm-bus"; 2013 #address-cells = <1>; 2014 #size-cells = <1>; 2015 ranges = <0x00000000 0x00200000 0x010000>; 2016 2017 target-module@0 { 2018 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 2019 power-domains = <&prm_mpu>; 2020 clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; 2021 clock-names = "fck"; 2022 ti,no-idle; 2023 #address-cells = <1>; 2024 #size-cells = <1>; 2025 ranges = <0 0 0x10000>; 2026 2027 mpu@0 { 2028 compatible = "ti,omap3-mpu"; 2029 pm-sram = <&pm_sram_code 2030 &pm_sram_data>; 2031 }; 2032 }; 2033 }; 2034 2035 segment@300000 { /* 0x48300000 */ 2036 compatible = "simple-pm-bus"; 2037 #address-cells = <1>; 2038 #size-cells = <1>; 2039 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ 2040 <0x00001000 0x00301000 0x001000>, /* ap 67 */ 2041 <0x00002000 0x00302000 0x001000>, /* ap 68 */ 2042 <0x00003000 0x00303000 0x001000>, /* ap 69 */ 2043 <0x00004000 0x00304000 0x001000>, /* ap 70 */ 2044 <0x00005000 0x00305000 0x001000>, /* ap 71 */ 2045 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ 2046 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ 2047 <0x00018000 0x00318000 0x004000>, /* ap 74 */ 2048 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ 2049 <0x00010000 0x00310000 0x002000>, /* ap 76 */ 2050 <0x00012000 0x00312000 0x001000>, /* ap 93 */ 2051 <0x00015000 0x00315000 0x001000>, /* ap 94 */ 2052 <0x00016000 0x00316000 0x001000>, /* ap 95 */ 2053 <0x00017000 0x00317000 0x001000>, /* ap 96 */ 2054 <0x00013000 0x00313000 0x001000>, /* ap 97 */ 2055 <0x00014000 0x00314000 0x001000>, /* ap 98 */ 2056 <0x00020000 0x00320000 0x001000>, /* ap 99 */ 2057 <0x00021000 0x00321000 0x001000>, /* ap 100 */ 2058 <0x00022000 0x00322000 0x001000>, /* ap 101 */ 2059 <0x00023000 0x00323000 0x001000>, /* ap 102 */ 2060 <0x00024000 0x00324000 0x001000>, /* ap 103 */ 2061 <0x00025000 0x00325000 0x001000>; /* ap 104 */ 2062 2063 target-module@0 { /* 0x48300000, ap 66 48.0 */ 2064 compatible = "ti,sysc-omap4", "ti,sysc"; 2065 reg = <0x0 0x4>, 2066 <0x4 0x4>; 2067 reg-names = "rev", "sysc"; 2068 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2069 <SYSC_IDLE_NO>, 2070 <SYSC_IDLE_SMART>, 2071 <SYSC_IDLE_SMART_WKUP>; 2072 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2073 <SYSC_IDLE_NO>, 2074 <SYSC_IDLE_SMART>, 2075 <SYSC_IDLE_SMART_WKUP>; 2076 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2077 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; 2078 clock-names = "fck"; 2079 #address-cells = <1>; 2080 #size-cells = <1>; 2081 ranges = <0x0 0x0 0x1000>; 2082 2083 epwmss0: epwmss@0 { 2084 compatible = "ti,am33xx-pwmss"; 2085 reg = <0x0 0x10>; 2086 #address-cells = <1>; 2087 #size-cells = <1>; 2088 status = "disabled"; 2089 ranges = <0 0 0x1000>; 2090 2091 ecap0: pwm@100 { 2092 compatible = "ti,am3352-ecap"; 2093 #pwm-cells = <3>; 2094 reg = <0x100 0x80>; 2095 clocks = <&l4ls_gclk>; 2096 clock-names = "fck"; 2097 status = "disabled"; 2098 }; 2099 2100 eqep0: counter@180 { 2101 compatible = "ti,am3352-eqep"; 2102 reg = <0x180 0x80>; 2103 clocks = <&l4ls_gclk>; 2104 clock-names = "sysclkout"; 2105 interrupts = <79>; 2106 status = "disabled"; 2107 }; 2108 2109 ehrpwm0: pwm@200 { 2110 compatible = "ti,am3352-ehrpwm"; 2111 #pwm-cells = <3>; 2112 reg = <0x200 0x80>; 2113 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 2114 clock-names = "tbclk", "fck"; 2115 status = "disabled"; 2116 }; 2117 }; 2118 }; 2119 2120 target-module@2000 { /* 0x48302000, ap 68 52.0 */ 2121 compatible = "ti,sysc-omap4", "ti,sysc"; 2122 reg = <0x2000 0x4>, 2123 <0x2004 0x4>; 2124 reg-names = "rev", "sysc"; 2125 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2126 <SYSC_IDLE_NO>, 2127 <SYSC_IDLE_SMART>, 2128 <SYSC_IDLE_SMART_WKUP>; 2129 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2130 <SYSC_IDLE_NO>, 2131 <SYSC_IDLE_SMART>, 2132 <SYSC_IDLE_SMART_WKUP>; 2133 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2134 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; 2135 clock-names = "fck"; 2136 #address-cells = <1>; 2137 #size-cells = <1>; 2138 ranges = <0x0 0x2000 0x1000>; 2139 2140 epwmss1: epwmss@0 { 2141 compatible = "ti,am33xx-pwmss"; 2142 reg = <0x0 0x10>; 2143 #address-cells = <1>; 2144 #size-cells = <1>; 2145 status = "disabled"; 2146 ranges = <0 0 0x1000>; 2147 2148 ecap1: pwm@100 { 2149 compatible = "ti,am3352-ecap"; 2150 #pwm-cells = <3>; 2151 reg = <0x100 0x80>; 2152 clocks = <&l4ls_gclk>; 2153 clock-names = "fck"; 2154 status = "disabled"; 2155 }; 2156 2157 eqep1: counter@180 { 2158 compatible = "ti,am3352-eqep"; 2159 reg = <0x180 0x80>; 2160 clocks = <&l4ls_gclk>; 2161 clock-names = "sysclkout"; 2162 interrupts = <88>; 2163 status = "disabled"; 2164 }; 2165 2166 ehrpwm1: pwm@200 { 2167 compatible = "ti,am3352-ehrpwm"; 2168 #pwm-cells = <3>; 2169 reg = <0x200 0x80>; 2170 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 2171 clock-names = "tbclk", "fck"; 2172 status = "disabled"; 2173 }; 2174 }; 2175 }; 2176 2177 target-module@4000 { /* 0x48304000, ap 70 44.0 */ 2178 compatible = "ti,sysc-omap4", "ti,sysc"; 2179 reg = <0x4000 0x4>, 2180 <0x4004 0x4>; 2181 reg-names = "rev", "sysc"; 2182 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2183 <SYSC_IDLE_NO>, 2184 <SYSC_IDLE_SMART>, 2185 <SYSC_IDLE_SMART_WKUP>; 2186 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2187 <SYSC_IDLE_NO>, 2188 <SYSC_IDLE_SMART>, 2189 <SYSC_IDLE_SMART_WKUP>; 2190 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2191 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; 2192 clock-names = "fck"; 2193 #address-cells = <1>; 2194 #size-cells = <1>; 2195 ranges = <0x0 0x4000 0x1000>; 2196 2197 epwmss2: epwmss@0 { 2198 compatible = "ti,am33xx-pwmss"; 2199 reg = <0x0 0x10>; 2200 #address-cells = <1>; 2201 #size-cells = <1>; 2202 status = "disabled"; 2203 ranges = <0 0 0x1000>; 2204 2205 ecap2: pwm@100 { 2206 compatible = "ti,am3352-ecap"; 2207 #pwm-cells = <3>; 2208 reg = <0x100 0x80>; 2209 clocks = <&l4ls_gclk>; 2210 clock-names = "fck"; 2211 status = "disabled"; 2212 }; 2213 2214 eqep2: counter@180 { 2215 compatible = "ti,am3352-eqep"; 2216 reg = <0x180 0x80>; 2217 clocks = <&l4ls_gclk>; 2218 clock-names = "sysclkout"; 2219 interrupts = <89>; 2220 status = "disabled"; 2221 }; 2222 2223 ehrpwm2: pwm@200 { 2224 compatible = "ti,am3352-ehrpwm"; 2225 #pwm-cells = <3>; 2226 reg = <0x200 0x80>; 2227 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 2228 clock-names = "tbclk", "fck"; 2229 status = "disabled"; 2230 }; 2231 }; 2232 }; 2233 2234 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ 2235 compatible = "ti,sysc-omap4", "ti,sysc"; 2236 reg = <0xe000 0x4>, 2237 <0xe054 0x4>; 2238 reg-names = "rev", "sysc"; 2239 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2240 <SYSC_IDLE_NO>, 2241 <SYSC_IDLE_SMART>; 2242 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2243 <SYSC_IDLE_NO>, 2244 <SYSC_IDLE_SMART>; 2245 /* Domains (P, C): per_pwrdm, lcdc_clkdm */ 2246 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; 2247 clock-names = "fck"; 2248 #address-cells = <1>; 2249 #size-cells = <1>; 2250 ranges = <0x0 0xe000 0x1000>; 2251 2252 lcdc: lcdc@0 { 2253 compatible = "ti,am33xx-tilcdc"; 2254 reg = <0x0 0x1000>; 2255 interrupts = <36>; 2256 status = "disabled"; 2257 }; 2258 }; 2259 2260 target-module@10000 { /* 0x48310000, ap 76 4e.1 */ 2261 compatible = "ti,sysc-omap2", "ti,sysc"; 2262 reg = <0x11fe0 0x4>, 2263 <0x11fe4 0x4>; 2264 reg-names = "rev", "sysc"; 2265 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 2266 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2267 <SYSC_IDLE_NO>; 2268 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2269 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; 2270 clock-names = "fck"; 2271 #address-cells = <1>; 2272 #size-cells = <1>; 2273 ranges = <0x0 0x10000 0x2000>; 2274 2275 rng: rng@0 { 2276 compatible = "ti,omap4-rng"; 2277 reg = <0x0 0x2000>; 2278 interrupts = <111>; 2279 }; 2280 }; 2281 2282 target-module@13000 { /* 0x48313000, ap 97 62.0 */ 2283 compatible = "ti,sysc"; 2284 status = "disabled"; 2285 #address-cells = <1>; 2286 #size-cells = <1>; 2287 ranges = <0x0 0x13000 0x1000>; 2288 }; 2289 2290 target-module@15000 { /* 0x48315000, ap 94 56.0 */ 2291 compatible = "ti,sysc"; 2292 status = "disabled"; 2293 #address-cells = <1>; 2294 #size-cells = <1>; 2295 ranges = <0x00000000 0x00015000 0x00001000>, 2296 <0x00001000 0x00016000 0x00001000>; 2297 }; 2298 2299 target-module@18000 { /* 0x48318000, ap 74 4c.0 */ 2300 compatible = "ti,sysc"; 2301 status = "disabled"; 2302 #address-cells = <1>; 2303 #size-cells = <1>; 2304 ranges = <0x0 0x18000 0x4000>; 2305 }; 2306 2307 target-module@20000 { /* 0x48320000, ap 99 34.0 */ 2308 compatible = "ti,sysc"; 2309 status = "disabled"; 2310 #address-cells = <1>; 2311 #size-cells = <1>; 2312 ranges = <0x0 0x20000 0x1000>; 2313 }; 2314 2315 target-module@22000 { /* 0x48322000, ap 101 3e.0 */ 2316 compatible = "ti,sysc"; 2317 status = "disabled"; 2318 #address-cells = <1>; 2319 #size-cells = <1>; 2320 ranges = <0x0 0x22000 0x1000>; 2321 }; 2322 2323 target-module@24000 { /* 0x48324000, ap 103 68.0 */ 2324 compatible = "ti,sysc"; 2325 status = "disabled"; 2326 #address-cells = <1>; 2327 #size-cells = <1>; 2328 ranges = <0x0 0x24000 0x1000>; 2329 }; 2330 }; 2331}; 2332 2333