xref: /freebsd/sys/contrib/device-tree/src/arm/st/stm32mp15x-mecio1-io.dtsi (revision b2d2a78ad80ec68d4a17f5aef97d21686cb1e29b)

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) Protonic Holland
 * Author: David Jander <david@protonic.nl>
 */

#include "stm32mp15xc.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	chosen {
		stdout-path = "serial0:1500000n8";
	};

	aliases {
		serial0 = &uart4;
		ethernet0 = &ethernet0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
		spi5 = &spi5;
		spi6 = &spi6;
	};

	memory@c0000000 {
		device_type = "memory";
		reg = <0xC0000000 0x10000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mcuram2: mcuram2@10000000 {
			compatible = "shared-dma-pool";
			reg = <0x10000000 0x40000>;
			no-map;
		};

		vdev0vring0: vdev0vring0@10040000 {
			compatible = "shared-dma-pool";
			reg = <0x10040000 0x1000>;
			no-map;
		};

		vdev0vring1: vdev0vring1@10041000 {
			compatible = "shared-dma-pool";
			reg = <0x10041000 0x1000>;
			no-map;
		};

		vdev0buffer: vdev0buffer@10042000 {
			compatible = "shared-dma-pool";
			reg = <0x10042000 0x4000>;
			no-map;
		};

		mcuram: mcuram@30000000 {
			compatible = "shared-dma-pool";
			reg = <0x30000000 0x40000>;
			no-map;
		};

		retram: retram@38000000 {
			compatible = "shared-dma-pool";
			reg = <0x38000000 0x10000>;
			no-map;
		};
	};

	v3v3: regulator-v3v3 {
		compatible = "regulator-fixed";
		regulator-name = "v3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	v5v: regulator-v5v {
		compatible = "regulator-fixed";
		regulator-name = "v5v";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};
};

&adc {
	/* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
	pinctrl-0 = <&adc12_pins_mecsbc>;
	pinctrl-names = "default";
	vdd-supply = <&v3v3>;
	vdda-supply = <&v3v3>;
	vref-supply = <&v3v3>;
	status = "okay";
};

&adc1 {
	status = "okay";

	channel@0 {
		reg = <0>;
		/* 16.5 ck_cycles sampling time */
		st,min-sample-time-ns = <5000>;
		label = "p24v_stp";
	};

	channel@1 {
		reg = <1>;
		st,min-sample-time-ns = <5000>;
		label = "p24v_hpdcm";
	};

	channel@2 {
		reg = <2>;
		st,min-sample-time-ns = <5000>;
		label = "ain0";
	};

	channel@3 {
		reg = <3>;
		st,min-sample-time-ns = <5000>;
		label = "hpdcm1_i2";
	};

	channel@5 {
		reg = <5>;
		st,min-sample-time-ns = <5000>;
		label = "hpout1_i";
	};

	channel@6 {
		reg = <6>;
		st,min-sample-time-ns = <5000>;
		label = "ain1";
	};

	channel@9 {
		reg = <9>;
		st,min-sample-time-ns = <5000>;
		label = "hpout0_i";
	};

	channel@10 {
		reg = <10>;
		st,min-sample-time-ns = <5000>;
		label = "phint0_ain";
	};

	channel@13 {
		reg = <13>;
		st,min-sample-time-ns = <5000>;
		label = "phint1_ain";
	};

	channel@15 {
		reg = <15>;
		st,min-sample-time-ns = <5000>;
		label = "hpdcm0_i1";
	};

	channel@16 {
		reg = <16>;
		st,min-sample-time-ns = <5000>;
		label = "lsin";
	};

	channel@18 {
		reg = <18>;
		st,min-sample-time-ns = <5000>;
		label = "hpdcm0_i2";
	};

	channel@19 {
		reg = <19>;
		st,min-sample-time-ns = <5000>;
		label = "hpdcm1_i1";
	};
};

&adc2 {
	status = "okay";

	channel@2 {
		reg = <2>;
		/* 16.5 ck_cycles sampling time */
		st,min-sample-time-ns = <5000>;
		label = "ain2";
	};

	channel@6 {
		reg = <6>;
		st,min-sample-time-ns = <5000>;
		label = "ain3";
	};
};

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_x>;
	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_x>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy0>;
	st,eth-clk-sel;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@8 {
			reg = <8>;
			interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpiog 10 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10>;
			reset-deassert-us = <35>;
		};
	};
};

&gpiod {
	gpio-line-names = "", "", "", "",
			  "", "", "", "",
			  "", "", "", "",
			  "STP_RESETN", "STP_ENABLEN", "HPOUT0", "HPOUT0_ALERTN";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_d_mecsbc>;
};

&gpioe {
	gpio-line-names = "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "",
			  "", "", "HPOUT1_RESETN",
			  "LPOUT0", "LPOUT0_ALERTN", "GPOUT0_RESETN",
			  "LPOUT1", "LPOUT1_ALERTN", "GPOUT1_RESETN",
			  "LPOUT2", "LPOUT2_ALERTN", "GPOUT2_RESETN";
};

&gpiof {
	gpio-line-names = "LPOUT3", "LPOUT3_ALERTN", "GPOUT3_RESETN",
			  "LPOUT4", "LPOUT4_ALERTN", "GPOUT4_RESETN",
			  "", "",
			  "", "", "", "",
			  "", "", "", "";
};

&gpiog {
	gpio-line-names = "LPOUT5", "LPOUT5_ALERTN", "", "LPOUT5_RESETN",
			  "", "", "", "",
			  "", "", "", "",
			  "", "", "", "";
};

&gpioh {
	gpio-line-names = "", "", "", "",
			  "", "", "", "",
			  "GPIO0_RESETN", "", "", "",
			  "", "", "", "";
};

&gpioi {
	gpio-line-names = "", "", "", "",
			  "", "", "", "",
			  "HPDCM0_SLEEPN", "HPDCM1_SLEEPN", "GPIO1_RESETN", "",
			  "", "", "", "";
};

&gpioj {
	gpio-line-names = "HSIN10", "HSIN11", "HSIN12", "HSIN13",
			  "HSIN14", "HSIN15", "", "",
			  "", "", "", "",
			  "", "RTD_RESETN", "", "";
};

&gpiok {
	gpio-line-names = "", "", "HSIN0", "HSIN1",
			  "HSIN2", "HSIN3", "HSIN4", "HSIN5";
};

&gpioz {
	gpio-line-names = "", "", "", "HSIN6",
			  "HSIN7", "HSIN8", "HSIN9", "";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins_a>;
	pinctrl-1 = <&i2c2_sleep_pins_a>;
	status = "okay";

	gpio0: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS",
				  "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL",
				  "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN9_BIAS",
				  "", "", "", "";
	};

	gpio1: gpio@21 {
		compatible = "ti,tca6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BIAS",
				  "", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL",
				  "HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS",
				  "", "", "LSIN8_BIAS", "LSIN9_BIAS";
	};
};

&qspi {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&qspi_clk_pins_a
		     &qspi_bk1_pins_a
		     &qspi_cs1_pins_a>;
	pinctrl-1 = <&qspi_clk_sleep_pins_a
		     &qspi_bk1_sleep_pins_a
		     &qspi_cs1_sleep_pins_a>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <104000000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&{qspi_bk1_pins_a/pins} {
	pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
		 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
		 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
		 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
	/delete-property/ bias-disable;
	bias-pull-up;
};

&timers1 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "okay";

	hpdcm0_pwm: pwm {
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pwm1_pins_mecio1>;
		pinctrl-1 = <&pwm1_sleep_pins_mecio1>;
		status = "okay";
	};
};

&timers8 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "okay";

	hpdcm1_pwm: pwm {
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pwm8_pins_mecio1>;
		pinctrl-1 = <&pwm8_sleep_pins_mecio1>;
		status = "okay";
	};
};

&uart4 {
	pinctrl-names = "default", "sleep", "idle";
	pinctrl-0 = <&uart4_pins_a>;
	pinctrl-1 = <&uart4_sleep_pins_a>;
	pinctrl-2 = <&uart4_idle_pins_a>;
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "okay";
};

&{uart4_pins_a/pins1} {
	pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
};

&{uart4_pins_a/pins2} {
	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
	/delete-property/ bias-disable;
	bias-pull-up;
};

&usbotg_hs {
	dr_mode = "host";
	pinctrl-0 = <&usbotg_hs_pins_a>;
	pinctrl-names = "default";
	phys = <&usbphyc_port1 0>;
	phy-names = "usb2-phy";
	vbus-supply = <&v5v>;
	status = "okay";
};

&usbphyc {
	status = "okay";
};

&usbphyc_port0 {
	phy-supply = <&v3v3>;
};

&usbphyc_port1 {
	phy-supply = <&v3v3>;
};

&pinctrl {
	adc12_pins_mecsbc: adc12-ain-mecsbc-0 {
		pins {
			pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
				 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1_INP6 */
				 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2_INP2 */
				 <STM32_PINMUX('F', 14, ANALOG)>, /* ADC2_INP6 */
				 <STM32_PINMUX('A', 0, ANALOG)>, /* ADC1_INP16 */
				 <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */
				 <STM32_PINMUX('A', 4, ANALOG)>, /* ADC1_INP18 */
				 <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP19 */
				 <STM32_PINMUX('A', 6, ANALOG)>, /* ADC1_INP3 */
				 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
				 <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
				 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
				 <STM32_PINMUX('C', 3, ANALOG)>; /* ADC1_INP13 */
		};
	};

	pinctrl_hog_d_mecsbc: hog-d-0 {
		pins {
			pinmux = <STM32_PINMUX('D', 12, GPIO)>; /* STP_RESETn */
			bias-pull-up;
			drive-push-pull;
			slew-rate = <0>;
		};
	};

	pwm1_pins_mecio1: pwm1-mecio1-0 {
		pins {
			pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
				 <STM32_PINMUX('A', 8, AF1)>; /* TIM1_CH2 */
			bias-pull-down;
			drive-push-pull;
			slew-rate = <0>;
		};
	};

	pwm1_sleep_pins_mecio1: pwm1-sleep-mecio1-0 {
		pins {
			pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* TIM1_CH1 */
				 <STM32_PINMUX('A', 8, ANALOG)>; /* TIM1_CH2 */
		};
	};

	pwm8_pins_mecio1: pwm8-mecio1-0 {
		pins {
			pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
				 <STM32_PINMUX('I', 6, AF3)>; /* TIM8_CH2 */
			bias-pull-down;
			drive-push-pull;
			slew-rate = <0>;
		};
	};

	pwm8_sleep_pins_mecio1: pwm8-sleep-mecio1-0 {
		pins {
			pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
				 <STM32_PINMUX('I', 6, ANALOG)>; /* TIM8_CH2 */
		};
	};

	ethernet0_rgmii_pins_x: rgmii-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
				 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
				 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
				 <STM32_PINMUX('B', 13, AF11)>, /* ETH_RGMII_TXD1 */
				 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
				 <STM32_PINMUX('B', 8, AF11)>, /* ETH_RGMII_TXD3 */
				 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
				 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
			bias-disable;
			drive-push-pull;
			slew-rate = <3>;
		};
		pins2 {
			pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
			bias-disable;
			drive-push-pull;
			slew-rate = <0>;
		};
		pins3 {
			pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
				 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
				 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
				 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
				 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
			bias-disable;
		};
	};

	ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
				 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
				 <STM32_PINMUX('B', 13, ANALOG)>, /* ETH_RGMII_TXD1 */
				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
				 <STM32_PINMUX('B', 8, ANALOG)>, /* ETH_RGMII_TXD3 */
				 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
				 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
				 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
				 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
				 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
				 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
		};
	};
};