xref: /freebsd/sys/contrib/device-tree/src/arm/st/stm32mp151a-prtt1l.dtsi (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) Protonic Holland
4 * Author: David Jander <david@protonic.nl>
5 */
6/dts-v1/;
7
8#include "stm32mp151.dtsi"
9#include "stm32mp15-pinctrl.dtsi"
10#include "stm32mp15xxad-pinctrl.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/leds/common.h>
14
15/ {
16	aliases {
17		ethernet0 = &ethernet0;
18		mdio-gpio0 = &mdio0;
19		serial0 = &uart4;
20	};
21
22	led-controller-0 {
23		compatible = "gpio-leds";
24
25		led-0 {
26			color = <LED_COLOR_ID_RED>;
27			function = LED_FUNCTION_INDICATOR;
28			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
29		};
30
31		led-1 {
32			color = <LED_COLOR_ID_GREEN>;
33			function = LED_FUNCTION_INDICATOR;
34			gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
35			linux,default-trigger = "heartbeat";
36		};
37	};
38
39
40	/* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce
41	 * stmmac MDC clock without reducing system bus rate, we need to use
42	 * gpio based MDIO bus.
43	 */
44	mdio0: mdio {
45		compatible = "virtual,mdio-gpio";
46		#address-cells = <1>;
47		#size-cells = <0>;
48		gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
49			 &gpioa 2 GPIO_ACTIVE_HIGH>;
50	};
51
52	reg_3v3: regulator-3v3 {
53		compatible = "regulator-fixed";
54		regulator-name = "3v3";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57	};
58};
59
60&dts {
61	status = "okay";
62};
63
64&ethernet0 {
65	pinctrl-0 = <&ethernet0_rmii_pins_a>;
66	pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
67	pinctrl-names = "default", "sleep";
68	phy-mode = "rmii";
69	status = "okay";
70};
71
72&ethernet0_rmii_pins_a {
73	pins1 {
74		pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
75			 <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
76			 <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
77	};
78	pins2 {
79		pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */
80			 <STM32_PINMUX('C', 5, AF11)>,  /* ETH1_RMII_RXD1 */
81			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK input */
82			 <STM32_PINMUX('A', 7, AF11)>;  /* ETH1_RMII_CRS_DV */
83	};
84};
85
86&ethernet0_rmii_sleep_pins_a {
87	pins1 {
88		pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */
89			 <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */
90			 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
91			 <STM32_PINMUX('C', 4, ANALOG)>,  /* ETH1_RMII_RXD0 */
92			 <STM32_PINMUX('C', 5, ANALOG)>,  /* ETH1_RMII_RXD1 */
93			 <STM32_PINMUX('A', 1, ANALOG)>,  /* ETH1_RMII_REF_CLK */
94			 <STM32_PINMUX('A', 7, ANALOG)>;  /* ETH1_RMII_CRS_DV */
95	};
96};
97
98&iwdg2 {
99	status = "okay";
100};
101
102&qspi {
103	pinctrl-names = "default", "sleep";
104	pinctrl-0 = <&qspi_clk_pins_a
105		     &qspi_bk1_pins_a
106		     &qspi_cs1_pins_a>;
107	pinctrl-1 = <&qspi_clk_sleep_pins_a
108		     &qspi_bk1_sleep_pins_a
109		     &qspi_cs1_sleep_pins_a>;
110	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
111	#address-cells = <1>;
112	#size-cells = <0>;
113	status = "okay";
114
115	flash@0 {
116		compatible = "spi-nand";
117		reg = <0>;
118		spi-rx-bus-width = <4>;
119		spi-max-frequency = <104000000>;
120		#address-cells = <1>;
121		#size-cells = <1>;
122	};
123};
124
125&qspi_bk1_pins_a {
126	pins1 {
127		bias-pull-up;
128		drive-push-pull;
129		slew-rate = <1>;
130	};
131};
132
133&rng1 {
134	status = "okay";
135};
136
137&sdmmc1 {
138	pinctrl-names = "default", "opendrain", "sleep";
139	pinctrl-0 = <&sdmmc1_b4_pins_a>;
140	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
141	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
142	broken-cd;
143	st,neg-edge;
144	bus-width = <4>;
145	vmmc-supply = <&reg_3v3>;
146	vqmmc-supply = <&reg_3v3>;
147	status = "okay";
148};
149
150&sdmmc1_b4_od_pins_a {
151	pins1 {
152		bias-pull-up;
153	};
154	pins2 {
155		bias-pull-up;
156	};
157};
158
159&sdmmc1_b4_pins_a {
160	pins1 {
161		bias-pull-up;
162	};
163	pins2 {
164		bias-pull-up;
165	};
166};
167
168&uart4 {
169	pinctrl-names = "default", "sleep", "idle";
170	pinctrl-0 = <&uart4_pins_a>;
171	pinctrl-1 = <&uart4_sleep_pins_a>;
172	pinctrl-2 = <&uart4_idle_pins_a>;
173	/delete-property/dmas;
174	/delete-property/dma-names;
175	status = "okay";
176};
177
178&uart4_idle_pins_a {
179	pins1 {
180		pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */
181	};
182	pins2 {
183		pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
184		bias-pull-up;
185	};
186};
187
188&uart4_pins_a {
189	pins1 {
190		pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
191		bias-disable;
192		drive-push-pull;
193		slew-rate = <0>;
194	};
195	pins2 {
196		pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
197		bias-pull-up;
198	};
199};
200
201&uart4_sleep_pins_a {
202	pins {
203		pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */
204			<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
205	};
206};
207
208&usbh_ehci {
209	status = "okay";
210};
211
212&usbotg_hs {
213	dr_mode = "host";
214	pinctrl-0 = <&usbotg_hs_pins_a>;
215	pinctrl-names = "default";
216	phys = <&usbphyc_port1 0>;
217	phy-names = "usb2-phy";
218	status = "okay";
219};
220
221&usbphyc {
222	status = "okay";
223};
224
225&usbphyc_port0 {
226	phy-supply = <&reg_3v3>;
227};
228
229&usbphyc_port1 {
230	phy-supply = <&reg_3v3>;
231};
232