xref: /freebsd/sys/contrib/device-tree/src/arm/st/stm32f7-pinctrl.dtsi (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0) 
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/pinctrl/stm32-pinfunc.h>
8#include <dt-bindings/mfd/stm32f7-rcc.h>
9
10/ {
11	soc {
12		pinctrl: pinctrl@40020000 {
13			#address-cells = <1>;
14			#size-cells = <1>;
15			ranges = <0 0x40020000 0x3000>;
16			interrupt-parent = <&exti>;
17			st,syscfg = <&syscfg 0x8>;
18
19			gpioa: gpio@40020000 {
20				gpio-controller;
21				#gpio-cells = <2>;
22				interrupt-controller;
23				#interrupt-cells = <2>;
24				reg = <0x0 0x400>;
25				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
26				st,bank-name = "GPIOA";
27			};
28
29			gpiob: gpio@40020400 {
30				gpio-controller;
31				#gpio-cells = <2>;
32				interrupt-controller;
33				#interrupt-cells = <2>;
34				reg = <0x400 0x400>;
35				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
36				st,bank-name = "GPIOB";
37			};
38
39			gpioc: gpio@40020800 {
40				gpio-controller;
41				#gpio-cells = <2>;
42				interrupt-controller;
43				#interrupt-cells = <2>;
44				reg = <0x800 0x400>;
45				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
46				st,bank-name = "GPIOC";
47			};
48
49			gpiod: gpio@40020c00 {
50				gpio-controller;
51				#gpio-cells = <2>;
52				interrupt-controller;
53				#interrupt-cells = <2>;
54				reg = <0xc00 0x400>;
55				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
56				st,bank-name = "GPIOD";
57			};
58
59			gpioe: gpio@40021000 {
60				gpio-controller;
61				#gpio-cells = <2>;
62				interrupt-controller;
63				#interrupt-cells = <2>;
64				reg = <0x1000 0x400>;
65				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
66				st,bank-name = "GPIOE";
67			};
68
69			gpiof: gpio@40021400 {
70				gpio-controller;
71				#gpio-cells = <2>;
72				interrupt-controller;
73				#interrupt-cells = <2>;
74				reg = <0x1400 0x400>;
75				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
76				st,bank-name = "GPIOF";
77			};
78
79			gpiog: gpio@40021800 {
80				gpio-controller;
81				#gpio-cells = <2>;
82				interrupt-controller;
83				#interrupt-cells = <2>;
84				reg = <0x1800 0x400>;
85				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
86				st,bank-name = "GPIOG";
87			};
88
89			gpioh: gpio@40021c00 {
90				gpio-controller;
91				#gpio-cells = <2>;
92				interrupt-controller;
93				#interrupt-cells = <2>;
94				reg = <0x1c00 0x400>;
95				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
96				st,bank-name = "GPIOH";
97			};
98
99			gpioi: gpio@40022000 {
100				gpio-controller;
101				#gpio-cells = <2>;
102				interrupt-controller;
103				#interrupt-cells = <2>;
104				reg = <0x2000 0x400>;
105				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
106				st,bank-name = "GPIOI";
107			};
108
109			gpioj: gpio@40022400 {
110				gpio-controller;
111				#gpio-cells = <2>;
112				interrupt-controller;
113				#interrupt-cells = <2>;
114				reg = <0x2400 0x400>;
115				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
116				st,bank-name = "GPIOJ";
117			};
118
119			gpiok: gpio@40022800 {
120				gpio-controller;
121				#gpio-cells = <2>;
122				interrupt-controller;
123				#interrupt-cells = <2>;
124				reg = <0x2800 0x400>;
125				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
126				st,bank-name = "GPIOK";
127			};
128
129			cec_pins_a: cec-0 {
130				pins {
131					pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
132					slew-rate = <0>;
133					drive-open-drain;
134					bias-disable;
135				};
136			};
137
138			usart1_pins_a: usart1-0 {
139				pins1 {
140					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
141					bias-disable;
142					drive-push-pull;
143					slew-rate = <0>;
144				};
145				pins2 {
146					pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
147					bias-disable;
148				};
149			};
150
151			usart1_pins_b: usart1-1 {
152				pins1 {
153					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
154					bias-disable;
155					drive-push-pull;
156					slew-rate = <0>;
157				};
158				pins2 {
159					pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
160					bias-disable;
161				};
162			};
163
164			i2c1_pins_b: i2c1-0 {
165				pins {
166					pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
167						 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
168					bias-disable;
169					drive-open-drain;
170					slew-rate = <0>;
171				};
172			};
173
174			i2c3_pins_a: i2c3-0 {
175				pins {
176					pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
177						 <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
178					bias-disable;
179					drive-open-drain;
180					slew-rate = <0>;
181				};
182			};
183
184			usbotg_hs_pins_a: usbotg-hs-0 {
185				pins {
186					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
187						 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
188						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
189						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
190						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
191						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
192						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
193						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
194						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
195						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
196						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
197						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
198					bias-disable;
199					drive-push-pull;
200					slew-rate = <2>;
201				};
202			};
203
204			usbotg_hs_pins_b: usbotg-hs-1 {
205				pins {
206					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
207						 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
208						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
209						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
210						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
211						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
212						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
213						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
214						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
215						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
216						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
217						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
218					bias-disable;
219					drive-push-pull;
220					slew-rate = <2>;
221				};
222			};
223
224			usbotg_fs_pins_a: usbotg-fs-0 {
225				pins {
226					pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
227						 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
228						 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
229					bias-disable;
230					drive-push-pull;
231					slew-rate = <2>;
232				};
233			};
234
235			sdio_pins_a: sdio-pins-a-0 {
236				pins {
237					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
238						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
239						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
240						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
241						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
242						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
243					drive-push-pull;
244					slew-rate = <2>;
245				};
246			};
247
248			sdio_pins_od_a: sdio-pins-od-a-0 {
249				pins1 {
250					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
251						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
252						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
253						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
254						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
255					drive-push-pull;
256					slew-rate = <2>;
257				};
258
259				pins2 {
260					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
261					drive-open-drain;
262					slew-rate = <2>;
263				};
264			};
265
266			sdio_pins_sleep_a: sdio-pins-sleep-a-0 {
267				pins {
268					pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1 D0 */
269						 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1 D1 */
270						 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1 D2 */
271						 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1 D3 */
272						 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */
273						 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1 CMD */
274				};
275			};
276
277			sdio_pins_b: sdio-pins-b-0 {
278				pins {
279					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
280						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
281						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
282						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
283						 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
284						 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
285					drive-push-pull;
286					slew-rate = <2>;
287				};
288			};
289
290			sdio_pins_od_b: sdio-pins-od-b-0 {
291				pins1 {
292					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
293						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
294						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
295						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
296						 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
297					drive-push-pull;
298					slew-rate = <2>;
299				};
300
301				pins2 {
302					pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
303					drive-open-drain;
304					slew-rate = <2>;
305				};
306			};
307
308			sdio_pins_sleep_b: sdio-pins-sleep-b-0 {
309				pins {
310					pinmux = <STM32_PINMUX('G', 9, ANALOG)>, /* SDMMC2 D0 */
311						 <STM32_PINMUX('G', 10, ANALOG)>, /* SDMMC2 D1 */
312						 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2 D2 */
313						 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2 D3 */
314						 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */
315						 <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC2 CMD */
316				};
317			};
318
319			can1_pins_a: can1-0 {
320				pins1 {
321					pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
322				};
323				pins2 {
324					pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
325					bias-pull-up;
326				};
327			};
328
329			can1_pins_b: can1-1 {
330				pins1 {
331					pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
332				};
333				pins2 {
334					pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
335					bias-pull-up;
336				};
337			};
338
339			can1_pins_c: can1-2 {
340				pins1 {
341					pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
342				};
343				pins2 {
344					pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
345					bias-pull-up;
346
347				};
348			};
349
350			can1_pins_d: can1-3 {
351				pins1 {
352					pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
353				};
354				pins2 {
355					pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
356					bias-pull-up;
357
358				};
359			};
360
361			can2_pins_a: can2-0 {
362				pins1 {
363					pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
364				};
365				pins2 {
366					pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
367					bias-pull-up;
368				};
369			};
370
371			can2_pins_b: can2-1 {
372				pins1 {
373					pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
374				};
375				pins2 {
376					pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
377					bias-pull-up;
378				};
379			};
380
381			can3_pins_a: can3-0 {
382				pins1 {
383					pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
384				};
385				pins2 {
386					pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
387					bias-pull-up;
388				};
389			};
390
391			can3_pins_b: can3-1 {
392				pins1 {
393					pinmux = <STM32_PINMUX('B', 4, AF11)>;  /* CAN3_TX */
394				};
395				pins2 {
396					pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
397					bias-pull-up;
398				};
399			};
400
401			ltdc_pins_a: ltdc-0 {
402				pins {
403					pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
404						 <STM32_PINMUX('G',12, AF9)>,  /* LCD_B4 */
405						 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
406						 <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
407						 <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
408						 <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
409						 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
410						 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
411						 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
412						 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
413						 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
414						 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
415						 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
416						 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
417						 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
418						 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
419						 <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
420						 <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
421						 <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
422						 <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
423						 <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
424						 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
425						 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
426						 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
427						 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
428						 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
429						 <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
430						 <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
431					slew-rate = <2>;
432				};
433			};
434		};
435	};
436};
437