xref: /freebsd/sys/contrib/device-tree/src/arm/st/stm32f7-pinctrl.dtsi (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/pinctrl/stm32-pinfunc.h>
8#include <dt-bindings/mfd/stm32f7-rcc.h>
9
10/ {
11	soc {
12		pinctrl: pinctrl@40020000 {
13			#address-cells = <1>;
14			#size-cells = <1>;
15			ranges = <0 0x40020000 0x3000>;
16			interrupt-parent = <&exti>;
17			st,syscfg = <&syscfg 0x8>;
18
19			gpioa: gpio@40020000 {
20				gpio-controller;
21				#gpio-cells = <2>;
22				interrupt-controller;
23				#interrupt-cells = <2>;
24				reg = <0x0 0x400>;
25				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
26				st,bank-name = "GPIOA";
27			};
28
29			gpiob: gpio@40020400 {
30				gpio-controller;
31				#gpio-cells = <2>;
32				interrupt-controller;
33				#interrupt-cells = <2>;
34				reg = <0x400 0x400>;
35				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
36				st,bank-name = "GPIOB";
37			};
38
39			gpioc: gpio@40020800 {
40				gpio-controller;
41				#gpio-cells = <2>;
42				interrupt-controller;
43				#interrupt-cells = <2>;
44				reg = <0x800 0x400>;
45				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
46				st,bank-name = "GPIOC";
47			};
48
49			gpiod: gpio@40020c00 {
50				gpio-controller;
51				#gpio-cells = <2>;
52				interrupt-controller;
53				#interrupt-cells = <2>;
54				reg = <0xc00 0x400>;
55				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
56				st,bank-name = "GPIOD";
57			};
58
59			gpioe: gpio@40021000 {
60				gpio-controller;
61				#gpio-cells = <2>;
62				interrupt-controller;
63				#interrupt-cells = <2>;
64				reg = <0x1000 0x400>;
65				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
66				st,bank-name = "GPIOE";
67			};
68
69			gpiof: gpio@40021400 {
70				gpio-controller;
71				#gpio-cells = <2>;
72				interrupt-controller;
73				#interrupt-cells = <2>;
74				reg = <0x1400 0x400>;
75				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
76				st,bank-name = "GPIOF";
77			};
78
79			gpiog: gpio@40021800 {
80				gpio-controller;
81				#gpio-cells = <2>;
82				interrupt-controller;
83				#interrupt-cells = <2>;
84				reg = <0x1800 0x400>;
85				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
86				st,bank-name = "GPIOG";
87			};
88
89			gpioh: gpio@40021c00 {
90				gpio-controller;
91				#gpio-cells = <2>;
92				interrupt-controller;
93				#interrupt-cells = <2>;
94				reg = <0x1c00 0x400>;
95				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
96				st,bank-name = "GPIOH";
97			};
98
99			gpioi: gpio@40022000 {
100				gpio-controller;
101				#gpio-cells = <2>;
102				interrupt-controller;
103				#interrupt-cells = <2>;
104				reg = <0x2000 0x400>;
105				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
106				st,bank-name = "GPIOI";
107			};
108
109			gpioj: gpio@40022400 {
110				gpio-controller;
111				#gpio-cells = <2>;
112				interrupt-controller;
113				#interrupt-cells = <2>;
114				reg = <0x2400 0x400>;
115				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
116				st,bank-name = "GPIOJ";
117			};
118
119			gpiok: gpio@40022800 {
120				gpio-controller;
121				#gpio-cells = <2>;
122				interrupt-controller;
123				#interrupt-cells = <2>;
124				reg = <0x2800 0x400>;
125				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
126				st,bank-name = "GPIOK";
127			};
128
129			cec_pins_a: cec-0 {
130				pins {
131					pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
132					slew-rate = <0>;
133					drive-open-drain;
134					bias-disable;
135				};
136			};
137
138			usart1_pins_a: usart1-0 {
139				pins1 {
140					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
141					bias-disable;
142					drive-push-pull;
143					slew-rate = <0>;
144				};
145				pins2 {
146					pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
147					bias-disable;
148				};
149			};
150
151			usart1_pins_b: usart1-1 {
152				pins1 {
153					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
154					bias-disable;
155					drive-push-pull;
156					slew-rate = <0>;
157				};
158				pins2 {
159					pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
160					bias-disable;
161				};
162			};
163
164			i2c1_pins_b: i2c1-0 {
165				pins {
166					pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
167						 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
168					bias-disable;
169					drive-open-drain;
170					slew-rate = <0>;
171				};
172			};
173
174			usbotg_hs_pins_a: usbotg-hs-0 {
175				pins {
176					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
177						 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
178						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
179						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
180						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
181						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
182						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
183						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
184						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
185						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
186						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
187						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
188					bias-disable;
189					drive-push-pull;
190					slew-rate = <2>;
191				};
192			};
193
194			usbotg_hs_pins_b: usbotg-hs-1 {
195				pins {
196					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
197						 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
198						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
199						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
200						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
201						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
202						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
203						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
204						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
205						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
206						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
207						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
208					bias-disable;
209					drive-push-pull;
210					slew-rate = <2>;
211				};
212			};
213
214			usbotg_fs_pins_a: usbotg-fs-0 {
215				pins {
216					pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
217						 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
218						 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
219					bias-disable;
220					drive-push-pull;
221					slew-rate = <2>;
222				};
223			};
224
225			sdio_pins_a: sdio-pins-a-0 {
226				pins {
227					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
228						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
229						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
230						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
231						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
232						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
233					drive-push-pull;
234					slew-rate = <2>;
235				};
236			};
237
238			sdio_pins_od_a: sdio-pins-od-a-0 {
239				pins1 {
240					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
241						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
242						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
243						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
244						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
245					drive-push-pull;
246					slew-rate = <2>;
247				};
248
249				pins2 {
250					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
251					drive-open-drain;
252					slew-rate = <2>;
253				};
254			};
255
256			sdio_pins_b: sdio-pins-b-0 {
257				pins {
258					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
259						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
260						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
261						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
262						 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
263						 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
264					drive-push-pull;
265					slew-rate = <2>;
266				};
267			};
268
269			sdio_pins_od_b: sdio-pins-od-b-0 {
270				pins1 {
271					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
272						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
273						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
274						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
275						 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
276					drive-push-pull;
277					slew-rate = <2>;
278				};
279
280				pins2 {
281					pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
282					drive-open-drain;
283					slew-rate = <2>;
284				};
285			};
286
287			can1_pins_a: can1-0 {
288				pins1 {
289					pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
290				};
291				pins2 {
292					pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
293					bias-pull-up;
294				};
295			};
296
297			can1_pins_b: can1-1 {
298				pins1 {
299					pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
300				};
301				pins2 {
302					pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
303					bias-pull-up;
304				};
305			};
306
307			can1_pins_c: can1-2 {
308				pins1 {
309					pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
310				};
311				pins2 {
312					pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
313					bias-pull-up;
314
315				};
316			};
317
318			can1_pins_d: can1-3 {
319				pins1 {
320					pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
321				};
322				pins2 {
323					pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
324					bias-pull-up;
325
326				};
327			};
328
329			can2_pins_a: can2-0 {
330				pins1 {
331					pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
332				};
333				pins2 {
334					pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
335					bias-pull-up;
336				};
337			};
338
339			can2_pins_b: can2-1 {
340				pins1 {
341					pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
342				};
343				pins2 {
344					pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
345					bias-pull-up;
346				};
347			};
348
349			can3_pins_a: can3-0 {
350				pins1 {
351					pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
352				};
353				pins2 {
354					pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
355					bias-pull-up;
356				};
357			};
358
359			can3_pins_b: can3-1 {
360				pins1 {
361					pinmux = <STM32_PINMUX('B', 4, AF11)>;  /* CAN3_TX */
362				};
363				pins2 {
364					pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
365					bias-pull-up;
366				};
367			};
368		};
369	};
370};
371