1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014 STMicroelectronics Limited. 4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 5 */ 6#include "st-pincfg.h" 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8/ { 9 10 aliases { 11 /* 0-5: PIO_SBC */ 12 gpio0 = &pio0; 13 gpio1 = &pio1; 14 gpio2 = &pio2; 15 gpio3 = &pio3; 16 gpio4 = &pio4; 17 gpio5 = &pio5; 18 /* 10-19: PIO_FRONT0 */ 19 gpio6 = &pio10; 20 gpio7 = &pio11; 21 gpio8 = &pio12; 22 gpio9 = &pio13; 23 gpio10 = &pio14; 24 gpio11 = &pio15; 25 gpio12 = &pio16; 26 gpio13 = &pio17; 27 gpio14 = &pio18; 28 gpio15 = &pio19; 29 /* 20: PIO_FRONT1 */ 30 gpio16 = &pio20; 31 /* 30-35: PIO_REAR */ 32 gpio17 = &pio30; 33 gpio18 = &pio31; 34 gpio19 = &pio32; 35 gpio20 = &pio33; 36 gpio21 = &pio34; 37 gpio22 = &pio35; 38 /* 40-42: PIO_FLASH */ 39 gpio23 = &pio40; 40 gpio24 = &pio41; 41 gpio25 = &pio42; 42 }; 43 44 soc { 45 pin-controller-sbc@961f080 { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 compatible = "st,stih407-sbc-pinctrl"; 49 st,syscfg = <&syscfg_sbc>; 50 reg = <0x0961f080 0x4>; 51 reg-names = "irqmux"; 52 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 53 interrupt-names = "irqmux"; 54 ranges = <0 0x09610000 0x6000>; 55 56 pio0: gpio@9610000 { 57 gpio-controller; 58 #gpio-cells = <2>; 59 interrupt-controller; 60 #interrupt-cells = <2>; 61 reg = <0x0 0x100>; 62 st,bank-name = "PIO0"; 63 }; 64 pio1: gpio@9611000 { 65 gpio-controller; 66 #gpio-cells = <2>; 67 interrupt-controller; 68 #interrupt-cells = <2>; 69 reg = <0x1000 0x100>; 70 st,bank-name = "PIO1"; 71 }; 72 pio2: gpio@9612000 { 73 gpio-controller; 74 #gpio-cells = <2>; 75 interrupt-controller; 76 #interrupt-cells = <2>; 77 reg = <0x2000 0x100>; 78 st,bank-name = "PIO2"; 79 }; 80 pio3: gpio@9613000 { 81 gpio-controller; 82 #gpio-cells = <2>; 83 interrupt-controller; 84 #interrupt-cells = <2>; 85 reg = <0x3000 0x100>; 86 st,bank-name = "PIO3"; 87 }; 88 pio4: gpio@9614000 { 89 gpio-controller; 90 #gpio-cells = <2>; 91 interrupt-controller; 92 #interrupt-cells = <2>; 93 reg = <0x4000 0x100>; 94 st,bank-name = "PIO4"; 95 }; 96 97 pio5: gpio@9615000 { 98 gpio-controller; 99 #gpio-cells = <2>; 100 interrupt-controller; 101 #interrupt-cells = <2>; 102 reg = <0x5000 0x100>; 103 st,bank-name = "PIO5"; 104 st,retime-pin-mask = <0x3f>; 105 }; 106 107 cec0 { 108 pinctrl_cec0_default: cec0-default { 109 st,pins { 110 hdmi_cec = <&pio2 4 ALT1 BIDIR>; 111 }; 112 }; 113 }; 114 115 rc { 116 pinctrl_ir: ir0 { 117 st,pins { 118 ir = <&pio4 0 ALT2 IN>; 119 }; 120 }; 121 122 pinctrl_uhf: uhf0 { 123 st,pins { 124 ir = <&pio4 1 ALT2 IN>; 125 }; 126 }; 127 128 pinctrl_tx: tx0 { 129 st,pins { 130 tx = <&pio4 2 ALT2 OUT>; 131 }; 132 }; 133 134 pinctrl_tx_od: tx_od0 { 135 st,pins { 136 tx_od = <&pio4 3 ALT2 OUT>; 137 }; 138 }; 139 }; 140 141 /* SBC_ASC0 - UART10 */ 142 sbc_serial0 { 143 pinctrl_sbc_serial0: sbc_serial0-0 { 144 st,pins { 145 tx = <&pio3 4 ALT1 OUT>; 146 rx = <&pio3 5 ALT1 IN>; 147 }; 148 }; 149 }; 150 /* SBC_ASC1 - UART11 */ 151 sbc_serial1 { 152 pinctrl_sbc_serial1: sbc_serial1-0 { 153 st,pins { 154 tx = <&pio2 6 ALT3 OUT>; 155 rx = <&pio2 7 ALT3 IN>; 156 }; 157 }; 158 }; 159 160 i2c10 { 161 pinctrl_i2c10_default: i2c10-default { 162 st,pins { 163 sda = <&pio4 6 ALT1 BIDIR>; 164 scl = <&pio4 5 ALT1 BIDIR>; 165 }; 166 }; 167 }; 168 169 i2c11 { 170 pinctrl_i2c11_default: i2c11-default { 171 st,pins { 172 sda = <&pio5 1 ALT1 BIDIR>; 173 scl = <&pio5 0 ALT1 BIDIR>; 174 }; 175 }; 176 }; 177 178 keyscan { 179 pinctrl_keyscan: keyscan { 180 st,pins { 181 keyin0 = <&pio4 0 ALT6 IN>; 182 keyin1 = <&pio4 5 ALT4 IN>; 183 keyin2 = <&pio0 4 ALT2 IN>; 184 keyin3 = <&pio2 6 ALT2 IN>; 185 186 keyout0 = <&pio4 6 ALT4 OUT>; 187 keyout1 = <&pio1 7 ALT2 OUT>; 188 keyout2 = <&pio0 6 ALT2 OUT>; 189 keyout3 = <&pio2 7 ALT2 OUT>; 190 }; 191 }; 192 }; 193 194 gmac1 { 195 /* 196 * Almost all the boards based on STiH407 SoC have an embedded 197 * switch where the mdio/mdc have been used for managing the SMI 198 * iface via I2C. For this reason these lines can be allocated 199 * by using dedicated configuration (in case of there will be a 200 * standard PHY transceiver on-board). 201 */ 202 pinctrl_rgmii1: rgmii1-0 { 203 st,pins { 204 205 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; 206 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; 207 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; 208 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; 209 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; 210 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; 211 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; 212 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; 213 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; 214 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; 215 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; 216 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; 217 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; 218 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; 219 }; 220 }; 221 222 pinctrl_rgmii1_mdio: rgmii1-mdio { 223 st,pins { 224 mdio = <&pio1 0 ALT1 OUT BYPASS 0>; 225 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 226 mdint = <&pio1 3 ALT1 IN BYPASS 0>; 227 }; 228 }; 229 230 pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { 231 st,pins { 232 mdio = <&pio1 0 ALT1 OUT BYPASS 0>; 233 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 234 }; 235 }; 236 237 pinctrl_mii1: mii1 { 238 st,pins { 239 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 240 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 241 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 242 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 243 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 244 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 245 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; 246 col = <&pio0 7 ALT1 IN BYPASS 1000>; 247 248 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; 249 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 250 crs = <&pio1 2 ALT1 IN BYPASS 1000>; 251 mdint = <&pio1 3 ALT1 IN BYPASS 0>; 252 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 253 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 254 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 255 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 256 257 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 258 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 259 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; 260 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; 261 }; 262 }; 263 264 pinctrl_rmii1: rmii1-0 { 265 st,pins { 266 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 267 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 268 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 269 mdio = <&pio1 0 ALT1 OUT BYPASS 0>; 270 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 271 mdint = <&pio1 3 ALT1 IN BYPASS 0>; 272 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; 273 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; 274 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; 275 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 276 }; 277 }; 278 279 pinctrl_rmii1_phyclk: rmii1_phyclk { 280 st,pins { 281 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; 282 }; 283 }; 284 285 pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { 286 st,pins { 287 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; 288 }; 289 }; 290 }; 291 292 pwm1 { 293 pinctrl_pwm1_chan0_default: pwm1-0-default { 294 st,pins { 295 pwm-out = <&pio3 0 ALT1 OUT>; 296 pwm-capturein = <&pio3 2 ALT1 IN>; 297 }; 298 }; 299 pinctrl_pwm1_chan1_default: pwm1-1-default { 300 st,pins { 301 pwm-capturein = <&pio4 3 ALT1 IN>; 302 pwm-out = <&pio4 4 ALT1 OUT>; 303 }; 304 }; 305 pinctrl_pwm1_chan2_default: pwm1-2-default { 306 st,pins { 307 pwm-out = <&pio4 6 ALT3 OUT>; 308 }; 309 }; 310 pinctrl_pwm1_chan3_default: pwm1-3-default { 311 st,pins { 312 pwm-out = <&pio4 7 ALT3 OUT>; 313 }; 314 }; 315 }; 316 317 spi10 { 318 pinctrl_spi10_default: spi10-4w-alt1-0 { 319 st,pins { 320 mtsr = <&pio4 6 ALT1 OUT>; 321 mrst = <&pio4 7 ALT1 IN>; 322 scl = <&pio4 5 ALT1 OUT>; 323 }; 324 }; 325 326 pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { 327 st,pins { 328 mtsr = <&pio4 6 ALT1 BIDIR_PU>; 329 scl = <&pio4 5 ALT1 OUT>; 330 }; 331 }; 332 }; 333 334 spi11 { 335 pinctrl_spi11_default: spi11-4w-alt2-0 { 336 st,pins { 337 mtsr = <&pio3 1 ALT2 OUT>; 338 mrst = <&pio3 0 ALT2 IN>; 339 scl = <&pio3 2 ALT2 OUT>; 340 }; 341 }; 342 343 pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { 344 st,pins { 345 mtsr = <&pio3 1 ALT2 BIDIR_PU>; 346 scl = <&pio3 2 ALT2 OUT>; 347 }; 348 }; 349 }; 350 351 spi12 { 352 pinctrl_spi12_default: spi12-4w-alt2-0 { 353 st,pins { 354 mtsr = <&pio3 6 ALT2 OUT>; 355 mrst = <&pio3 4 ALT2 IN>; 356 scl = <&pio3 7 ALT2 OUT>; 357 }; 358 }; 359 360 pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { 361 st,pins { 362 mtsr = <&pio3 6 ALT2 BIDIR_PU>; 363 scl = <&pio3 7 ALT2 OUT>; 364 }; 365 }; 366 }; 367 }; 368 369 pin-controller-front0@920f080 { 370 #address-cells = <1>; 371 #size-cells = <1>; 372 compatible = "st,stih407-front-pinctrl"; 373 st,syscfg = <&syscfg_front>; 374 reg = <0x0920f080 0x4>; 375 reg-names = "irqmux"; 376 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 377 interrupt-names = "irqmux"; 378 ranges = <0 0x09200000 0x10000>; 379 380 pio10: pio@9200000 { 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 reg = <0x0 0x100>; 386 st,bank-name = "PIO10"; 387 }; 388 pio11: pio@9201000 { 389 gpio-controller; 390 #gpio-cells = <2>; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 reg = <0x1000 0x100>; 394 st,bank-name = "PIO11"; 395 }; 396 pio12: pio@9202000 { 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 reg = <0x2000 0x100>; 402 st,bank-name = "PIO12"; 403 }; 404 pio13: pio@9203000 { 405 gpio-controller; 406 #gpio-cells = <2>; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 reg = <0x3000 0x100>; 410 st,bank-name = "PIO13"; 411 }; 412 pio14: pio@9204000 { 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 reg = <0x4000 0x100>; 418 st,bank-name = "PIO14"; 419 }; 420 pio15: pio@9205000 { 421 gpio-controller; 422 #gpio-cells = <2>; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 reg = <0x5000 0x100>; 426 st,bank-name = "PIO15"; 427 }; 428 pio16: pio@9206000 { 429 gpio-controller; 430 #gpio-cells = <2>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 reg = <0x6000 0x100>; 434 st,bank-name = "PIO16"; 435 }; 436 pio17: pio@9207000 { 437 gpio-controller; 438 #gpio-cells = <2>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 reg = <0x7000 0x100>; 442 st,bank-name = "PIO17"; 443 }; 444 pio18: pio@9208000 { 445 gpio-controller; 446 #gpio-cells = <2>; 447 interrupt-controller; 448 #interrupt-cells = <2>; 449 reg = <0x8000 0x100>; 450 st,bank-name = "PIO18"; 451 }; 452 pio19: pio@9209000 { 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 reg = <0x9000 0x100>; 458 st,bank-name = "PIO19"; 459 }; 460 461 /* Comms */ 462 serial0 { 463 pinctrl_serial0: serial0-0 { 464 st,pins { 465 tx = <&pio17 0 ALT1 OUT>; 466 rx = <&pio17 1 ALT1 IN>; 467 }; 468 }; 469 pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { 470 st,pins { 471 tx = <&pio17 0 ALT1 OUT>; 472 rx = <&pio17 1 ALT1 IN>; 473 cts = <&pio17 2 ALT1 IN>; 474 rts = <&pio17 3 ALT1 OUT>; 475 }; 476 }; 477 }; 478 479 serial1 { 480 pinctrl_serial1: serial1-0 { 481 st,pins { 482 tx = <&pio16 0 ALT1 OUT>; 483 rx = <&pio16 1 ALT1 IN>; 484 }; 485 }; 486 }; 487 488 serial2 { 489 pinctrl_serial2: serial2-0 { 490 st,pins { 491 tx = <&pio15 0 ALT1 OUT>; 492 rx = <&pio15 1 ALT1 IN>; 493 }; 494 }; 495 }; 496 497 mmc1 { 498 pinctrl_sd1: sd1-0 { 499 st,pins { 500 sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; 501 sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; 502 sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; 503 sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; 504 sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; 505 sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; 506 sd_led = <&pio16 6 ALT6 OUT>; 507 sd_pwren = <&pio16 7 ALT6 OUT>; 508 sd_cd = <&pio19 0 ALT6 IN>; 509 sd_wp = <&pio19 1 ALT6 IN>; 510 }; 511 }; 512 }; 513 514 515 i2c0 { 516 pinctrl_i2c0_default: i2c0-default { 517 st,pins { 518 sda = <&pio10 6 ALT2 BIDIR>; 519 scl = <&pio10 5 ALT2 BIDIR>; 520 }; 521 }; 522 }; 523 524 i2c1 { 525 pinctrl_i2c1_default: i2c1-default { 526 st,pins { 527 sda = <&pio11 1 ALT2 BIDIR>; 528 scl = <&pio11 0 ALT2 BIDIR>; 529 }; 530 }; 531 }; 532 533 i2c2 { 534 pinctrl_i2c2_default: i2c2-default { 535 st,pins { 536 sda = <&pio15 6 ALT2 BIDIR>; 537 scl = <&pio15 5 ALT2 BIDIR>; 538 }; 539 }; 540 541 pinctrl_i2c2_alt2_1: i2c2-alt2-1 { 542 st,pins { 543 sda = <&pio12 6 ALT2 BIDIR>; 544 scl = <&pio12 5 ALT2 BIDIR>; 545 }; 546 }; 547 }; 548 549 i2c3 { 550 pinctrl_i2c3_default: i2c3-alt1-0 { 551 st,pins { 552 sda = <&pio18 6 ALT1 BIDIR>; 553 scl = <&pio18 5 ALT1 BIDIR>; 554 }; 555 }; 556 pinctrl_i2c3_alt1_1: i2c3-alt1-1 { 557 st,pins { 558 sda = <&pio17 7 ALT1 BIDIR>; 559 scl = <&pio17 6 ALT1 BIDIR>; 560 }; 561 }; 562 pinctrl_i2c3_alt3_0: i2c3-alt3-0 { 563 st,pins { 564 sda = <&pio13 6 ALT3 BIDIR>; 565 scl = <&pio13 5 ALT3 BIDIR>; 566 }; 567 }; 568 }; 569 570 spi0 { 571 pinctrl_spi0_default: spi0-4w-alt2-0 { 572 st,pins { 573 mtsr = <&pio10 6 ALT2 OUT>; 574 mrst = <&pio10 7 ALT2 IN>; 575 scl = <&pio10 5 ALT2 OUT>; 576 }; 577 }; 578 579 pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { 580 st,pins { 581 mtsr = <&pio10 6 ALT2 BIDIR_PU>; 582 scl = <&pio10 5 ALT2 OUT>; 583 }; 584 }; 585 586 pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { 587 st,pins { 588 mtsr = <&pio19 7 ALT1 OUT>; 589 mrst = <&pio19 5 ALT1 IN>; 590 scl = <&pio19 6 ALT1 OUT>; 591 }; 592 }; 593 594 pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { 595 st,pins { 596 mtsr = <&pio19 7 ALT1 BIDIR_PU>; 597 scl = <&pio19 6 ALT1 OUT>; 598 }; 599 }; 600 }; 601 602 spi1 { 603 pinctrl_spi1_default: spi1-4w-alt2-0 { 604 st,pins { 605 mtsr = <&pio11 1 ALT2 OUT>; 606 mrst = <&pio11 2 ALT2 IN>; 607 scl = <&pio11 0 ALT2 OUT>; 608 }; 609 }; 610 611 pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { 612 st,pins { 613 mtsr = <&pio11 1 ALT2 BIDIR_PU>; 614 scl = <&pio11 0 ALT2 OUT>; 615 }; 616 }; 617 618 pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { 619 st,pins { 620 mtsr = <&pio14 3 ALT1 OUT>; 621 mrst = <&pio14 4 ALT1 IN>; 622 scl = <&pio14 2 ALT1 OUT>; 623 }; 624 }; 625 626 pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { 627 st,pins { 628 mtsr = <&pio14 3 ALT1 BIDIR_PU>; 629 scl = <&pio14 2 ALT1 OUT>; 630 }; 631 }; 632 }; 633 634 spi2 { 635 pinctrl_spi2_default: spi2-4w-alt2-0 { 636 st,pins { 637 mtsr = <&pio12 6 ALT2 OUT>; 638 mrst = <&pio12 7 ALT2 IN>; 639 scl = <&pio12 5 ALT2 OUT>; 640 }; 641 }; 642 643 pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { 644 st,pins { 645 mtsr = <&pio12 6 ALT2 BIDIR_PU>; 646 scl = <&pio12 5 ALT2 OUT>; 647 }; 648 }; 649 650 pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { 651 st,pins { 652 mtsr = <&pio14 6 ALT1 OUT>; 653 mrst = <&pio14 7 ALT1 IN>; 654 scl = <&pio14 5 ALT1 OUT>; 655 }; 656 }; 657 658 pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { 659 st,pins { 660 mtsr = <&pio14 6 ALT1 BIDIR_PU>; 661 scl = <&pio14 5 ALT1 OUT>; 662 }; 663 }; 664 665 pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { 666 st,pins { 667 mtsr = <&pio15 6 ALT2 OUT>; 668 mrst = <&pio15 7 ALT2 IN>; 669 scl = <&pio15 5 ALT2 OUT>; 670 }; 671 }; 672 673 pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { 674 st,pins { 675 mtsr = <&pio15 6 ALT2 BIDIR_PU>; 676 scl = <&pio15 5 ALT2 OUT>; 677 }; 678 }; 679 }; 680 681 spi3 { 682 pinctrl_spi3_default: spi3-4w-alt3-0 { 683 st,pins { 684 mtsr = <&pio13 6 ALT3 OUT>; 685 mrst = <&pio13 7 ALT3 IN>; 686 scl = <&pio13 5 ALT3 OUT>; 687 }; 688 }; 689 690 pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { 691 st,pins { 692 mtsr = <&pio13 6 ALT3 BIDIR_PU>; 693 scl = <&pio13 5 ALT3 OUT>; 694 }; 695 }; 696 697 pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { 698 st,pins { 699 mtsr = <&pio17 7 ALT1 OUT>; 700 mrst = <&pio17 5 ALT1 IN>; 701 scl = <&pio17 6 ALT1 OUT>; 702 }; 703 }; 704 705 pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { 706 st,pins { 707 mtsr = <&pio17 7 ALT1 BIDIR_PU>; 708 scl = <&pio17 6 ALT1 OUT>; 709 }; 710 }; 711 712 pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { 713 st,pins { 714 mtsr = <&pio18 6 ALT1 OUT>; 715 mrst = <&pio18 7 ALT1 IN>; 716 scl = <&pio18 5 ALT1 OUT>; 717 }; 718 }; 719 720 pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { 721 st,pins { 722 mtsr = <&pio18 6 ALT1 BIDIR_PU>; 723 scl = <&pio18 5 ALT1 OUT>; 724 }; 725 }; 726 }; 727 728 tsin0 { 729 pinctrl_tsin0_parallel: tsin0_parallel { 730 st,pins { 731 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 732 DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 733 DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 734 DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 735 DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 736 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 737 DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 738 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; 739 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; 740 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 741 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 742 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 743 }; 744 }; 745 pinctrl_tsin0_serial: tsin0_serial { 746 st,pins { 747 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 748 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; 749 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 750 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 751 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 752 }; 753 }; 754 }; 755 756 tsin1 { 757 pinctrl_tsin1_parallel: tsin1_parallel { 758 st,pins { 759 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 760 DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 761 DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 762 DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; 763 DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 764 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 765 DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 766 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 767 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; 768 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 769 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 770 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 771 }; 772 }; 773 pinctrl_tsin1_serial: tsin1_serial { 774 st,pins { 775 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 776 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; 777 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 778 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 779 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 780 }; 781 }; 782 }; 783 784 tsin2 { 785 pinctrl_tsin2_parallel: tsin2_parallel { 786 st,pins { 787 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 788 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; 789 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; 790 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; 791 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 792 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; 793 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 794 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 795 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; 796 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 797 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 798 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 799 }; 800 }; 801 pinctrl_tsin2_serial: tsin2_serial { 802 st,pins { 803 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 804 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; 805 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 806 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 807 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 808 }; 809 }; 810 }; 811 812 tsin3 { 813 pinctrl_tsin3_serial: tsin3_serial { 814 st,pins { 815 DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 816 CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; 817 VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 818 ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 819 PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 820 }; 821 }; 822 }; 823 824 tsin4 { 825 pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { 826 st,pins { 827 DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; 828 CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; 829 VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; 830 ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; 831 PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; 832 }; 833 }; 834 }; 835 836 tsin5 { 837 pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { 838 st,pins { 839 DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 840 CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; 841 VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 842 ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 843 PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 844 }; 845 }; 846 pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { 847 st,pins { 848 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; 849 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; 850 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 851 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 852 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 853 }; 854 }; 855 }; 856 857 tsout0 { 858 pinctrl_tsout0_parallel: tsout0_parallel { 859 st,pins { 860 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 861 DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 862 DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 863 DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 864 DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 865 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 866 DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 867 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 868 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; 869 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 870 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 871 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 872 }; 873 }; 874 pinctrl_tsout0_serial: tsout0_serial { 875 st,pins { 876 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 877 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; 878 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 879 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 880 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; 881 }; 882 }; 883 }; 884 885 tsout1 { 886 pinctrl_tsout1_serial: tsout1_serial { 887 st,pins { 888 DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 889 CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; 890 VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 891 ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 892 PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 893 }; 894 }; 895 }; 896 897 mtsin0 { 898 pinctrl_mtsin0_parallel: mtsin0_parallel { 899 st,pins { 900 DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; 901 DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; 902 DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; 903 DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; 904 DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; 905 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; 906 DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; 907 DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; 908 CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; 909 VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; 910 ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; 911 PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; 912 }; 913 }; 914 }; 915 916 systrace { 917 pinctrl_systrace_default: systrace-default { 918 st,pins { 919 trc_data0 = <&pio11 3 ALT5 OUT>; 920 trc_data1 = <&pio11 4 ALT5 OUT>; 921 trc_data2 = <&pio11 5 ALT5 OUT>; 922 trc_data3 = <&pio11 6 ALT5 OUT>; 923 trc_clk = <&pio11 7 ALT5 OUT>; 924 }; 925 }; 926 }; 927 }; 928 929 pin-controller-front1@921f080 { 930 #address-cells = <1>; 931 #size-cells = <1>; 932 compatible = "st,stih407-front-pinctrl"; 933 st,syscfg = <&syscfg_front>; 934 reg = <0x0921f080 0x4>; 935 reg-names = "irqmux"; 936 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "irqmux"; 938 ranges = <0 0x09210000 0x10000>; 939 940 pio20: pio@9210000 { 941 gpio-controller; 942 #gpio-cells = <2>; 943 interrupt-controller; 944 #interrupt-cells = <2>; 945 reg = <0x0 0x100>; 946 st,bank-name = "PIO20"; 947 }; 948 949 tsin4 { 950 pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { 951 st,pins { 952 DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 953 CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; 954 VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 955 ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 956 PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; 957 }; 958 }; 959 }; 960 }; 961 962 pin-controller-rear@922f080 { 963 #address-cells = <1>; 964 #size-cells = <1>; 965 compatible = "st,stih407-rear-pinctrl"; 966 st,syscfg = <&syscfg_rear>; 967 reg = <0x0922f080 0x4>; 968 reg-names = "irqmux"; 969 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 970 interrupt-names = "irqmux"; 971 ranges = <0 0x09220000 0x6000>; 972 973 pio30: gpio@9220000 { 974 gpio-controller; 975 #gpio-cells = <2>; 976 interrupt-controller; 977 #interrupt-cells = <2>; 978 reg = <0x0 0x100>; 979 st,bank-name = "PIO30"; 980 }; 981 pio31: gpio@9221000 { 982 gpio-controller; 983 #gpio-cells = <2>; 984 interrupt-controller; 985 #interrupt-cells = <2>; 986 reg = <0x1000 0x100>; 987 st,bank-name = "PIO31"; 988 }; 989 pio32: gpio@9222000 { 990 gpio-controller; 991 #gpio-cells = <2>; 992 interrupt-controller; 993 #interrupt-cells = <2>; 994 reg = <0x2000 0x100>; 995 st,bank-name = "PIO32"; 996 }; 997 pio33: gpio@9223000 { 998 gpio-controller; 999 #gpio-cells = <2>; 1000 interrupt-controller; 1001 #interrupt-cells = <2>; 1002 reg = <0x3000 0x100>; 1003 st,bank-name = "PIO33"; 1004 }; 1005 pio34: gpio@9224000 { 1006 gpio-controller; 1007 #gpio-cells = <2>; 1008 interrupt-controller; 1009 #interrupt-cells = <2>; 1010 reg = <0x4000 0x100>; 1011 st,bank-name = "PIO34"; 1012 }; 1013 pio35: gpio@9225000 { 1014 gpio-controller; 1015 #gpio-cells = <2>; 1016 interrupt-controller; 1017 #interrupt-cells = <2>; 1018 reg = <0x5000 0x100>; 1019 st,bank-name = "PIO35"; 1020 st,retime-pin-mask = <0x7f>; 1021 }; 1022 1023 i2c4 { 1024 pinctrl_i2c4_default: i2c4-default { 1025 st,pins { 1026 sda = <&pio30 1 ALT1 BIDIR>; 1027 scl = <&pio30 0 ALT1 BIDIR>; 1028 }; 1029 }; 1030 }; 1031 1032 i2c5 { 1033 pinctrl_i2c5_default: i2c5-default { 1034 st,pins { 1035 sda = <&pio34 4 ALT1 BIDIR>; 1036 scl = <&pio34 3 ALT1 BIDIR>; 1037 }; 1038 }; 1039 }; 1040 1041 usb3 { 1042 pinctrl_usb3: usb3-2 { 1043 st,pins { 1044 usb-oc-detect = <&pio35 4 ALT1 IN>; 1045 usb-pwr-enable = <&pio35 5 ALT1 OUT>; 1046 usb-vbus-valid = <&pio35 6 ALT1 IN>; 1047 }; 1048 }; 1049 }; 1050 1051 pwm0 { 1052 pinctrl_pwm0_chan0_default: pwm0-0-default { 1053 st,pins { 1054 pwm-capturein = <&pio31 0 ALT1 IN>; 1055 pwm-out = <&pio31 1 ALT1 OUT>; 1056 }; 1057 }; 1058 }; 1059 1060 spi4 { 1061 pinctrl_spi4_default: spi4-4w-alt1-0 { 1062 st,pins { 1063 mtsr = <&pio30 1 ALT1 OUT>; 1064 mrst = <&pio30 2 ALT1 IN>; 1065 scl = <&pio30 0 ALT1 OUT>; 1066 }; 1067 }; 1068 1069 pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { 1070 st,pins { 1071 mtsr = <&pio30 1 ALT1 BIDIR_PU>; 1072 scl = <&pio30 0 ALT1 OUT>; 1073 }; 1074 }; 1075 1076 pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { 1077 st,pins { 1078 mtsr = <&pio34 1 ALT3 OUT>; 1079 mrst = <&pio34 2 ALT3 IN>; 1080 scl = <&pio34 0 ALT3 OUT>; 1081 }; 1082 }; 1083 1084 pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { 1085 st,pins { 1086 mtsr = <&pio34 1 ALT3 BIDIR_PU>; 1087 scl = <&pio34 0 ALT3 OUT>; 1088 }; 1089 }; 1090 }; 1091 1092 i2s_out { 1093 pinctrl_i2s_8ch_out: i2s_8ch_out { 1094 st,pins { 1095 mclk = <&pio33 5 ALT1 OUT>; 1096 lrclk = <&pio33 7 ALT1 OUT>; 1097 sclk = <&pio33 6 ALT1 OUT>; 1098 data0 = <&pio33 4 ALT1 OUT>; 1099 data1 = <&pio34 0 ALT1 OUT>; 1100 data2 = <&pio34 1 ALT1 OUT>; 1101 data3 = <&pio34 2 ALT1 OUT>; 1102 }; 1103 }; 1104 1105 pinctrl_i2s_2ch_out: i2s_2ch_out { 1106 st,pins { 1107 mclk = <&pio33 5 ALT1 OUT>; 1108 lrclk = <&pio33 7 ALT1 OUT>; 1109 sclk = <&pio33 6 ALT1 OUT>; 1110 data0 = <&pio33 4 ALT1 OUT>; 1111 }; 1112 }; 1113 }; 1114 1115 i2s_in { 1116 pinctrl_i2s_8ch_in: i2s_8ch_in { 1117 st,pins { 1118 mclk = <&pio32 5 ALT1 IN>; 1119 lrclk = <&pio32 7 ALT1 IN>; 1120 sclk = <&pio32 6 ALT1 IN>; 1121 data0 = <&pio32 4 ALT1 IN>; 1122 data1 = <&pio33 0 ALT1 IN>; 1123 data2 = <&pio33 1 ALT1 IN>; 1124 data3 = <&pio33 2 ALT1 IN>; 1125 data4 = <&pio33 3 ALT1 IN>; 1126 }; 1127 }; 1128 1129 pinctrl_i2s_2ch_in: i2s_2ch_in { 1130 st,pins { 1131 mclk = <&pio32 5 ALT1 IN>; 1132 lrclk = <&pio32 7 ALT1 IN>; 1133 sclk = <&pio32 6 ALT1 IN>; 1134 data0 = <&pio32 4 ALT1 IN>; 1135 }; 1136 }; 1137 }; 1138 1139 spdif_out { 1140 pinctrl_spdif_out: spdif_out { 1141 st,pins { 1142 spdif_out = <&pio34 7 ALT1 OUT>; 1143 }; 1144 }; 1145 }; 1146 1147 serial3 { 1148 pinctrl_serial3: serial3-0 { 1149 st,pins { 1150 tx = <&pio31 3 ALT1 OUT>; 1151 rx = <&pio31 4 ALT1 IN>; 1152 }; 1153 }; 1154 }; 1155 }; 1156 1157 pin-controller-flash@923f080 { 1158 #address-cells = <1>; 1159 #size-cells = <1>; 1160 compatible = "st,stih407-flash-pinctrl"; 1161 st,syscfg = <&syscfg_flash>; 1162 reg = <0x0923f080 0x4>; 1163 reg-names = "irqmux"; 1164 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "irqmux"; 1166 ranges = <0 0x09230000 0x3000>; 1167 1168 pio40: gpio@9230000 { 1169 gpio-controller; 1170 #gpio-cells = <2>; 1171 interrupt-controller; 1172 #interrupt-cells = <2>; 1173 reg = <0 0x100>; 1174 st,bank-name = "PIO40"; 1175 }; 1176 pio41: gpio@9231000 { 1177 gpio-controller; 1178 #gpio-cells = <2>; 1179 interrupt-controller; 1180 #interrupt-cells = <2>; 1181 reg = <0x1000 0x100>; 1182 st,bank-name = "PIO41"; 1183 }; 1184 pio42: gpio@9232000 { 1185 gpio-controller; 1186 #gpio-cells = <2>; 1187 interrupt-controller; 1188 #interrupt-cells = <2>; 1189 reg = <0x2000 0x100>; 1190 st,bank-name = "PIO42"; 1191 }; 1192 1193 mmc0 { 1194 pinctrl_mmc0: mmc0-0 { 1195 st,pins { 1196 emmc_clk = <&pio40 6 ALT1 BIDIR>; 1197 emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; 1198 emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; 1199 emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; 1200 emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; 1201 emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; 1202 emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; 1203 emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; 1204 emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; 1205 emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; 1206 }; 1207 }; 1208 pinctrl_sd0: sd0-0 { 1209 st,pins { 1210 sd_clk = <&pio40 6 ALT1 BIDIR>; 1211 sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; 1212 sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; 1213 sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; 1214 sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; 1215 sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; 1216 sd_led = <&pio42 0 ALT2 OUT>; 1217 sd_pwren = <&pio42 2 ALT2 OUT>; 1218 sd_vsel = <&pio42 3 ALT2 OUT>; 1219 sd_cd = <&pio42 4 ALT2 IN>; 1220 sd_wp = <&pio42 5 ALT2 IN>; 1221 }; 1222 }; 1223 }; 1224 1225 fsm { 1226 pinctrl_fsm: fsm { 1227 st,pins { 1228 spi-fsm-clk = <&pio40 1 ALT1 OUT>; 1229 spi-fsm-cs = <&pio40 0 ALT1 OUT>; 1230 spi-fsm-mosi = <&pio40 2 ALT1 OUT>; 1231 spi-fsm-miso = <&pio40 3 ALT1 IN>; 1232 spi-fsm-hol = <&pio40 5 ALT1 OUT>; 1233 spi-fsm-wp = <&pio40 4 ALT1 OUT>; 1234 }; 1235 }; 1236 }; 1237 1238 nand { 1239 pinctrl_nand: nand { 1240 st,pins { 1241 nand_cs1 = <&pio40 6 ALT3 OUT>; 1242 nand_cs0 = <&pio40 7 ALT3 OUT>; 1243 nand_d0 = <&pio41 0 ALT3 BIDIR>; 1244 nand_d1 = <&pio41 1 ALT3 BIDIR>; 1245 nand_d2 = <&pio41 2 ALT3 BIDIR>; 1246 nand_d3 = <&pio41 3 ALT3 BIDIR>; 1247 nand_d4 = <&pio41 4 ALT3 BIDIR>; 1248 nand_d5 = <&pio41 5 ALT3 BIDIR>; 1249 nand_d6 = <&pio41 6 ALT3 BIDIR>; 1250 nand_d7 = <&pio41 7 ALT3 BIDIR>; 1251 nand_we = <&pio42 0 ALT3 OUT>; 1252 nand_dqs = <&pio42 1 ALT3 OUT>; 1253 nand_ale = <&pio42 2 ALT3 OUT>; 1254 nand_cle = <&pio42 3 ALT3 OUT>; 1255 nand_rnb = <&pio42 4 ALT3 IN>; 1256 nand_oe = <&pio42 5 ALT3 OUT>; 1257 }; 1258 }; 1259 }; 1260 }; 1261 }; 1262}; 1263