1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014 STMicroelectronics Limited. 4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 5 */ 6#include "stih407-pinctrl.dtsi" 7#include <dt-bindings/mfd/st-lpc.h> 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/reset/stih407-resets.h> 10#include <dt-bindings/interrupt-controller/irq-st.h> 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 reserved-memory { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 ranges; 19 20 gp0_reserved: rproc@45000000 { 21 compatible = "shared-dma-pool"; 22 reg = <0x45000000 0x00400000>; 23 no-map; 24 }; 25 26 delta_reserved: rproc@44000000 { 27 compatible = "shared-dma-pool"; 28 reg = <0x44000000 0x01000000>; 29 no-map; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a9"; 39 reg = <0>; 40 41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 42 cpu-release-addr = <0x94100A4>; 43 44 /* kHz uV */ 45 operating-points = <1500000 0 46 1200000 0 47 800000 0 48 500000 0>; 49 50 clocks = <&clk_m_a9>; 51 clock-names = "cpu"; 52 clock-latency = <100000>; 53 cpu0-supply = <&pwm_regulator>; 54 st,syscfg = <&syscfg_core 0x8e0>; 55 }; 56 cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a9"; 59 reg = <1>; 60 61 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 62 cpu-release-addr = <0x94100A4>; 63 64 /* kHz uV */ 65 operating-points = <1500000 0 66 1200000 0 67 800000 0 68 500000 0>; 69 }; 70 }; 71 72 intc: interrupt-controller@8761000 { 73 compatible = "arm,cortex-a9-gic"; 74 #interrupt-cells = <3>; 75 interrupt-controller; 76 reg = <0x08761000 0x1000>, <0x08760100 0x100>; 77 }; 78 79 scu@8760000 { 80 compatible = "arm,cortex-a9-scu"; 81 reg = <0x08760000 0x1000>; 82 }; 83 84 timer@8760200 { 85 interrupt-parent = <&intc>; 86 compatible = "arm,cortex-a9-global-timer"; 87 reg = <0x08760200 0x100>; 88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&arm_periph_clk>; 90 }; 91 92 l2: cache-controller@8762000 { 93 compatible = "arm,pl310-cache"; 94 reg = <0x08762000 0x1000>; 95 arm,data-latency = <3 3 3>; 96 arm,tag-latency = <2 2 2>; 97 cache-unified; 98 cache-level = <2>; 99 }; 100 101 arm-pmu { 102 interrupt-parent = <&intc>; 103 compatible = "arm,cortex-a9-pmu"; 104 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 pwm_regulator: pwm-regulator { 108 compatible = "pwm-regulator"; 109 pwms = <&pwm1 3 8448>; 110 regulator-name = "CPU_1V0_AVS"; 111 regulator-min-microvolt = <784000>; 112 regulator-max-microvolt = <1299000>; 113 regulator-always-on; 114 status = "okay"; 115 }; 116 117 restart: restart-controller { 118 compatible = "st,stih407-restart"; 119 st,syscfg = <&syscfg_sbc_reg>; 120 status = "okay"; 121 }; 122 123 powerdown: powerdown-controller { 124 compatible = "st,stih407-powerdown"; 125 #reset-cells = <1>; 126 }; 127 128 softreset: softreset-controller { 129 compatible = "st,stih407-softreset"; 130 #reset-cells = <1>; 131 }; 132 133 picophyreset: picophyreset-controller { 134 compatible = "st,stih407-picophyreset"; 135 #reset-cells = <1>; 136 }; 137 138 irq-syscfg { 139 compatible = "st,stih407-irq-syscfg"; 140 st,syscfg = <&syscfg_core>; 141 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 142 <ST_IRQ_SYSCFG_PMU_1>; 143 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 144 <ST_IRQ_SYSCFG_DISABLED>; 145 }; 146 147 usb2_picophy0: phy1 { 148 compatible = "st,stih407-usb2-phy"; 149 #phy-cells = <0>; 150 st,syscfg = <&syscfg_core 0x100 0xf4>; 151 resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 152 <&picophyreset STIH407_PICOPHY2_RESET>; 153 reset-names = "global", "port"; 154 }; 155 156 miphy28lp_phy: miphy28lp { 157 compatible = "st,miphy28lp-phy"; 158 st,syscfg = <&syscfg_core>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 ranges; 162 163 phy_port0: port@9b22000 { 164 reg = <0x9b22000 0xff>, 165 <0x9b09000 0xff>, 166 <0x9b04000 0xff>; 167 reg-names = "sata-up", 168 "pcie-up", 169 "pipew"; 170 171 st,syscfg = <0x114 0x818 0xe0 0xec>; 172 #phy-cells = <1>; 173 174 reset-names = "miphy-sw-rst"; 175 resets = <&softreset STIH407_MIPHY0_SOFTRESET>; 176 }; 177 178 phy_port1: port@9b2a000 { 179 reg = <0x9b2a000 0xff>, 180 <0x9b19000 0xff>, 181 <0x9b14000 0xff>; 182 reg-names = "sata-up", 183 "pcie-up", 184 "pipew"; 185 186 st,syscfg = <0x118 0x81c 0xe4 0xf0>; 187 188 #phy-cells = <1>; 189 190 reset-names = "miphy-sw-rst"; 191 resets = <&softreset STIH407_MIPHY1_SOFTRESET>; 192 }; 193 194 phy_port2: port@8f95000 { 195 reg = <0x8f95000 0xff>, 196 <0x8f90000 0xff>; 197 reg-names = "pipew", 198 "usb3-up"; 199 200 st,syscfg = <0x11c 0x820>; 201 202 #phy-cells = <1>; 203 204 reset-names = "miphy-sw-rst"; 205 resets = <&softreset STIH407_MIPHY2_SOFTRESET>; 206 }; 207 }; 208 209 st231_gp0: st231-gp0 { 210 compatible = "st,st231-rproc"; 211 memory-region = <&gp0_reserved>; 212 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; 213 reset-names = "sw_reset"; 214 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; 215 clock-frequency = <600000000>; 216 st,syscfg = <&syscfg_core 0x22c>; 217 #mbox-cells = <1>; 218 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 219 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; 220 }; 221 222 st231_delta: st231-delta { 223 compatible = "st,st231-rproc"; 224 memory-region = <&delta_reserved>; 225 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; 226 reset-names = "sw_reset"; 227 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; 228 clock-frequency = <600000000>; 229 st,syscfg = <&syscfg_core 0x224>; 230 #mbox-cells = <1>; 231 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 232 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; 233 }; 234 235 delta0 { 236 compatible = "st,st-delta"; 237 clock-names = "delta", 238 "delta-st231", 239 "delta-flash-promip"; 240 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, 241 <&clk_s_c0_flexgen CLK_ST231_DMU>, 242 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 243 }; 244 245 soc { 246 #address-cells = <1>; 247 #size-cells = <1>; 248 interrupt-parent = <&intc>; 249 ranges; 250 compatible = "simple-bus"; 251 252 syscfg_sbc: sbc-syscfg@9620000 { 253 compatible = "st,stih407-sbc-syscfg", "syscon"; 254 reg = <0x9620000 0x1000>; 255 }; 256 257 syscfg_front: front-syscfg@9280000 { 258 compatible = "st,stih407-front-syscfg", "syscon"; 259 reg = <0x9280000 0x1000>; 260 }; 261 262 syscfg_rear: rear-syscfg@9290000 { 263 compatible = "st,stih407-rear-syscfg", "syscon"; 264 reg = <0x9290000 0x1000>; 265 }; 266 267 syscfg_flash: flash-syscfg@92a0000 { 268 compatible = "st,stih407-flash-syscfg", "syscon"; 269 reg = <0x92a0000 0x1000>; 270 }; 271 272 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { 273 compatible = "st,stih407-sbc-reg-syscfg", "syscon"; 274 reg = <0x9600000 0x1000>; 275 }; 276 277 syscfg_core: core-syscfg@92b0000 { 278 compatible = "st,stih407-core-syscfg", "syscon"; 279 reg = <0x92b0000 0x1000>; 280 281 sti_sasg_codec: sti-sasg-codec { 282 compatible = "st,stih407-sas-codec"; 283 #sound-dai-cells = <1>; 284 status = "disabled"; 285 st,syscfg = <&syscfg_core>; 286 }; 287 }; 288 289 syscfg_lpm: lpm-syscfg@94b5100 { 290 compatible = "st,stih407-lpm-syscfg", "syscon"; 291 reg = <0x94b5100 0x1000>; 292 }; 293 294 /* Display */ 295 vtg_main: sti-vtg-main@8d02800 { 296 compatible = "st,vtg"; 297 reg = <0x8d02800 0x200>; 298 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 299 }; 300 301 vtg_aux: sti-vtg-aux@8d00200 { 302 compatible = "st,vtg"; 303 reg = <0x8d00200 0x100>; 304 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 305 }; 306 307 serial@9830000 { 308 compatible = "st,asc"; 309 reg = <0x9830000 0x2c>; 310 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 312 /* Pinctrl moved out to a per-board configuration */ 313 314 status = "disabled"; 315 }; 316 317 serial@9831000 { 318 compatible = "st,asc"; 319 reg = <0x9831000 0x2c>; 320 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pinctrl_serial1>; 323 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 324 325 status = "disabled"; 326 }; 327 328 serial@9832000 { 329 compatible = "st,asc"; 330 reg = <0x9832000 0x2c>; 331 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_serial2>; 334 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 335 336 status = "disabled"; 337 }; 338 339 /* SBC_ASC0 - UART10 */ 340 sbc_serial0: serial@9530000 { 341 compatible = "st,asc"; 342 reg = <0x9530000 0x2c>; 343 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_sbc_serial0>; 346 clocks = <&clk_sysin>; 347 348 status = "disabled"; 349 }; 350 351 serial@9531000 { 352 compatible = "st,asc"; 353 reg = <0x9531000 0x2c>; 354 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_sbc_serial1>; 357 clocks = <&clk_sysin>; 358 359 status = "disabled"; 360 }; 361 362 i2c@9840000 { 363 compatible = "st,comms-ssc4-i2c"; 364 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 365 reg = <0x9840000 0x110>; 366 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 367 clock-names = "ssc"; 368 clock-frequency = <400000>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_i2c0_default>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 status = "disabled"; 375 }; 376 377 i2c@9841000 { 378 compatible = "st,comms-ssc4-i2c"; 379 reg = <0x9841000 0x110>; 380 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 382 clock-names = "ssc"; 383 clock-frequency = <400000>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_i2c1_default>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 389 status = "disabled"; 390 }; 391 392 i2c@9842000 { 393 compatible = "st,comms-ssc4-i2c"; 394 reg = <0x9842000 0x110>; 395 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 397 clock-names = "ssc"; 398 clock-frequency = <400000>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_i2c2_default>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 404 status = "disabled"; 405 }; 406 407 i2c@9843000 { 408 compatible = "st,comms-ssc4-i2c"; 409 reg = <0x9843000 0x110>; 410 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 412 clock-names = "ssc"; 413 clock-frequency = <400000>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pinctrl_i2c3_default>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 419 status = "disabled"; 420 }; 421 422 i2c@9844000 { 423 compatible = "st,comms-ssc4-i2c"; 424 reg = <0x9844000 0x110>; 425 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 427 clock-names = "ssc"; 428 clock-frequency = <400000>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_i2c4_default>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 status = "disabled"; 435 }; 436 437 i2c@9845000 { 438 compatible = "st,comms-ssc4-i2c"; 439 reg = <0x9845000 0x110>; 440 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 442 clock-names = "ssc"; 443 clock-frequency = <400000>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_i2c5_default>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 449 status = "disabled"; 450 }; 451 452 453 /* SSCs on SBC */ 454 i2c@9540000 { 455 compatible = "st,comms-ssc4-i2c"; 456 reg = <0x9540000 0x110>; 457 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clk_sysin>; 459 clock-names = "ssc"; 460 clock-frequency = <400000>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_i2c10_default>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 status = "disabled"; 467 }; 468 469 i2c@9541000 { 470 compatible = "st,comms-ssc4-i2c"; 471 reg = <0x9541000 0x110>; 472 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clk_sysin>; 474 clock-names = "ssc"; 475 clock-frequency = <400000>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_i2c11_default>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 481 status = "disabled"; 482 }; 483 484 spi@9840000 { 485 compatible = "st,comms-ssc4-spi"; 486 reg = <0x9840000 0x110>; 487 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 489 clock-names = "ssc"; 490 pinctrl-0 = <&pinctrl_spi0_default>; 491 pinctrl-names = "default"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 495 status = "disabled"; 496 }; 497 498 spi@9841000 { 499 compatible = "st,comms-ssc4-spi"; 500 reg = <0x9841000 0x110>; 501 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 503 clock-names = "ssc"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_spi1_default>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 509 status = "disabled"; 510 }; 511 512 spi@9842000 { 513 compatible = "st,comms-ssc4-spi"; 514 reg = <0x9842000 0x110>; 515 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 517 clock-names = "ssc"; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_spi2_default>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 status = "disabled"; 524 }; 525 526 spi@9843000 { 527 compatible = "st,comms-ssc4-spi"; 528 reg = <0x9843000 0x110>; 529 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 531 clock-names = "ssc"; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&pinctrl_spi3_default>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 537 status = "disabled"; 538 }; 539 540 spi@9844000 { 541 compatible = "st,comms-ssc4-spi"; 542 reg = <0x9844000 0x110>; 543 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 545 clock-names = "ssc"; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_spi4_default>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 551 status = "disabled"; 552 }; 553 554 /* SBC SSC */ 555 spi@9540000 { 556 compatible = "st,comms-ssc4-spi"; 557 reg = <0x9540000 0x110>; 558 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&clk_sysin>; 560 clock-names = "ssc"; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_spi10_default>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 status = "disabled"; 567 }; 568 569 spi@9541000 { 570 compatible = "st,comms-ssc4-spi"; 571 reg = <0x9541000 0x110>; 572 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&clk_sysin>; 574 clock-names = "ssc"; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pinctrl_spi11_default>; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 580 status = "disabled"; 581 }; 582 583 spi@9542000 { 584 compatible = "st,comms-ssc4-spi"; 585 reg = <0x9542000 0x110>; 586 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&clk_sysin>; 588 clock-names = "ssc"; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pinctrl_spi12_default>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 status = "disabled"; 595 }; 596 597 mmc0: sdhci@9060000 { 598 compatible = "st,sdhci-stih407", "st,sdhci"; 599 status = "disabled"; 600 reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 601 reg-names = "mmc", "top-mmc-delay"; 602 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 603 interrupt-names = "mmcirq"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_mmc0>; 606 clock-names = "mmc", "icn"; 607 clocks = <&clk_s_c0_flexgen CLK_MMC_0>, 608 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 609 bus-width = <8>; 610 }; 611 612 mmc1: sdhci@9080000 { 613 compatible = "st,sdhci-stih407", "st,sdhci"; 614 status = "disabled"; 615 reg = <0x09080000 0x7ff>; 616 reg-names = "mmc"; 617 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "mmcirq"; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_sd1>; 621 clock-names = "mmc", "icn"; 622 clocks = <&clk_s_c0_flexgen CLK_MMC_1>, 623 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 624 resets = <&softreset STIH407_MMC1_SOFTRESET>; 625 bus-width = <4>; 626 }; 627 628 /* Watchdog and Real-Time Clock */ 629 lpc@8787000 { 630 compatible = "st,stih407-lpc"; 631 reg = <0x8787000 0x1000>; 632 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; 633 clocks = <&clk_s_d3_flexgen CLK_LPC_0>; 634 timeout-sec = <120>; 635 st,syscfg = <&syscfg_core>; 636 st,lpc-mode = <ST_LPC_MODE_WDT>; 637 }; 638 639 lpc@8788000 { 640 compatible = "st,stih407-lpc"; 641 reg = <0x8788000 0x1000>; 642 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; 643 clocks = <&clk_s_d3_flexgen CLK_LPC_1>; 644 st,lpc-mode = <ST_LPC_MODE_CLKSRC>; 645 }; 646 647 spifsm: spifsm@9022000 { 648 compatible = "st,spi-fsm"; 649 reg = <0x9022000 0x1000>; 650 reg-names = "spi-fsm"; 651 clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 652 clock-names = "emi_clk"; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&pinctrl_fsm>; 655 st,syscfg = <&syscfg_core>; 656 st,boot-device-reg = <0x8c4>; 657 st,boot-device-spi = <0x68>; 658 659 status = "disabled"; 660 }; 661 662 sata0: sata@9b20000 { 663 compatible = "st,ahci"; 664 reg = <0x9b20000 0x1000>; 665 666 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "hostc"; 668 669 phys = <&phy_port0 PHY_TYPE_SATA>; 670 phy-names = "ahci_phy"; 671 672 resets = <&powerdown STIH407_SATA0_POWERDOWN>, 673 <&softreset STIH407_SATA0_SOFTRESET>, 674 <&softreset STIH407_SATA0_PWR_SOFTRESET>; 675 reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; 676 677 clock-names = "ahci_clk"; 678 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 679 680 ports-implemented = <0x1>; 681 682 status = "disabled"; 683 }; 684 685 sata1: sata@9b28000 { 686 compatible = "st,ahci"; 687 reg = <0x9b28000 0x1000>; 688 689 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "hostc"; 691 692 phys = <&phy_port1 PHY_TYPE_SATA>; 693 phy-names = "ahci_phy"; 694 695 resets = <&powerdown STIH407_SATA1_POWERDOWN>, 696 <&softreset STIH407_SATA1_SOFTRESET>, 697 <&softreset STIH407_SATA1_PWR_SOFTRESET>; 698 reset-names = "pwr-dwn", 699 "sw-rst", 700 "pwr-rst"; 701 702 clock-names = "ahci_clk"; 703 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 704 705 ports-implemented = <0x1>; 706 707 status = "disabled"; 708 }; 709 710 711 st_dwc3: dwc3@8f94000 { 712 compatible = "st,stih407-dwc3"; 713 reg = <0x08f94000 0x1000>, <0x110 0x4>; 714 reg-names = "reg-glue", "syscfg-reg"; 715 st,syscfg = <&syscfg_core>; 716 resets = <&powerdown STIH407_USB3_POWERDOWN>, 717 <&softreset STIH407_MIPHY2_SOFTRESET>; 718 reset-names = "powerdown", "softreset"; 719 #address-cells = <1>; 720 #size-cells = <1>; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&pinctrl_usb3>; 723 ranges; 724 725 status = "disabled"; 726 727 dwc3: usb@9900000 { 728 compatible = "snps,dwc3"; 729 reg = <0x09900000 0x100000>; 730 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 731 dr_mode = "host"; 732 phy-names = "usb2-phy", "usb3-phy"; 733 phys = <&usb2_picophy0>, 734 <&phy_port2 PHY_TYPE_USB3>; 735 snps,dis_u3_susphy_quirk; 736 }; 737 }; 738 739 /* COMMS PWM Module */ 740 pwm0: pwm@9810000 { 741 compatible = "st,sti-pwm"; 742 #pwm-cells = <2>; 743 reg = <0x9810000 0x68>; 744 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_pwm0_chan0_default>; 747 clock-names = "pwm"; 748 clocks = <&clk_sysin>; 749 st,pwm-num-chan = <1>; 750 751 status = "disabled"; 752 }; 753 754 /* SBC PWM Module */ 755 pwm1: pwm@9510000 { 756 compatible = "st,sti-pwm"; 757 #pwm-cells = <2>; 758 reg = <0x9510000 0x68>; 759 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&pinctrl_pwm1_chan0_default 762 &pinctrl_pwm1_chan1_default 763 &pinctrl_pwm1_chan2_default 764 &pinctrl_pwm1_chan3_default>; 765 clock-names = "pwm"; 766 clocks = <&clk_sysin>; 767 st,pwm-num-chan = <4>; 768 769 status = "disabled"; 770 }; 771 772 rng10: rng@8a89000 { 773 compatible = "st,rng"; 774 reg = <0x08a89000 0x1000>; 775 clocks = <&clk_sysin>; 776 status = "okay"; 777 }; 778 779 rng11: rng@8a8a000 { 780 compatible = "st,rng"; 781 reg = <0x08a8a000 0x1000>; 782 clocks = <&clk_sysin>; 783 status = "okay"; 784 }; 785 786 ethernet0: dwmac@9630000 { 787 device_type = "network"; 788 status = "disabled"; 789 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 790 reg = <0x9630000 0x8000>, <0x80 0x4>; 791 reg-names = "stmmaceth", "sti-ethconf"; 792 793 st,syscon = <&syscfg_sbc_reg 0x80>; 794 st,gmac_en; 795 resets = <&softreset STIH407_ETH1_SOFTRESET>; 796 reset-names = "stmmaceth"; 797 798 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 800 interrupt-names = "macirq", "eth_wake_irq"; 801 802 /* DMA Bus Mode */ 803 snps,pbl = <8>; 804 805 pinctrl-names = "default"; 806 pinctrl-0 = <&pinctrl_rgmii1>; 807 808 clock-names = "stmmaceth", "sti-ethclk"; 809 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, 810 <&clk_s_c0_flexgen CLK_ETH_PHY>; 811 }; 812 813 mailbox0: mailbox@8f00000 { 814 compatible = "st,stih407-mailbox"; 815 reg = <0x8f00000 0x1000>; 816 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 817 #mbox-cells = <2>; 818 mbox-name = "a9"; 819 status = "okay"; 820 }; 821 822 mailbox1: mailbox@8f01000 { 823 compatible = "st,stih407-mailbox"; 824 reg = <0x8f01000 0x1000>; 825 #mbox-cells = <2>; 826 mbox-name = "st231_gp_1"; 827 status = "okay"; 828 }; 829 830 mailbox2: mailbox@8f02000 { 831 compatible = "st,stih407-mailbox"; 832 reg = <0x8f02000 0x1000>; 833 #mbox-cells = <2>; 834 mbox-name = "st231_gp_0"; 835 status = "okay"; 836 }; 837 838 mailbox3: mailbox@8f03000 { 839 compatible = "st,stih407-mailbox"; 840 reg = <0x8f03000 0x1000>; 841 #mbox-cells = <2>; 842 mbox-name = "st231_audio_video"; 843 status = "okay"; 844 }; 845 846 /* fdma audio */ 847 fdma0: dma-controller@8e20000 { 848 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 849 reg = <0x8e20000 0x8000>, 850 <0x8e30000 0x3000>, 851 <0x8e37000 0x1000>, 852 <0x8e38000 0x8000>; 853 reg-names = "slimcore", "dmem", "peripherals", "imem"; 854 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 855 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 856 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 857 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 858 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 859 dma-channels = <16>; 860 #dma-cells = <3>; 861 }; 862 863 /* fdma app */ 864 fdma1: dma-controller@8e40000 { 865 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; 866 reg = <0x8e40000 0x8000>, 867 <0x8e50000 0x3000>, 868 <0x8e57000 0x1000>, 869 <0x8e58000 0x8000>; 870 reg-names = "slimcore", "dmem", "peripherals", "imem"; 871 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 872 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 873 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 874 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 875 876 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 877 dma-channels = <16>; 878 #dma-cells = <3>; 879 880 status = "disabled"; 881 }; 882 883 /* fdma free running */ 884 fdma2: dma-controller@8e60000 { 885 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; 886 reg = <0x8e60000 0x8000>, 887 <0x8e70000 0x3000>, 888 <0x8e77000 0x1000>, 889 <0x8e78000 0x8000>; 890 reg-names = "slimcore", "dmem", "peripherals", "imem"; 891 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 892 dma-channels = <16>; 893 #dma-cells = <3>; 894 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 895 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 896 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 897 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 898 899 status = "disabled"; 900 }; 901 902 sti_uni_player0: sti-uni-player@8d80000 { 903 compatible = "st,stih407-uni-player-hdmi"; 904 #sound-dai-cells = <0>; 905 st,syscfg = <&syscfg_core>; 906 clocks = <&clk_s_d0_flexgen CLK_PCM_0>; 907 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; 908 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; 909 assigned-clock-rates = <50000000>; 910 reg = <0x8d80000 0x158>; 911 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 912 dmas = <&fdma0 2 0 1>; 913 dma-names = "tx"; 914 915 status = "disabled"; 916 }; 917 918 sti_uni_player1: sti-uni-player@8d81000 { 919 compatible = "st,stih407-uni-player-pcm-out"; 920 #sound-dai-cells = <0>; 921 st,syscfg = <&syscfg_core>; 922 clocks = <&clk_s_d0_flexgen CLK_PCM_1>; 923 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; 924 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; 925 assigned-clock-rates = <50000000>; 926 reg = <0x8d81000 0x158>; 927 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 928 dmas = <&fdma0 3 0 1>; 929 dma-names = "tx"; 930 931 status = "disabled"; 932 }; 933 934 sti_uni_player2: sti-uni-player@8d82000 { 935 compatible = "st,stih407-uni-player-dac"; 936 #sound-dai-cells = <0>; 937 st,syscfg = <&syscfg_core>; 938 clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 939 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; 940 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; 941 assigned-clock-rates = <50000000>; 942 reg = <0x8d82000 0x158>; 943 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 944 dmas = <&fdma0 4 0 1>; 945 dma-names = "tx"; 946 947 status = "disabled"; 948 }; 949 950 sti_uni_player3: sti-uni-player@8d85000 { 951 compatible = "st,stih407-uni-player-spdif"; 952 #sound-dai-cells = <0>; 953 st,syscfg = <&syscfg_core>; 954 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; 955 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; 956 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; 957 assigned-clock-rates = <50000000>; 958 reg = <0x8d85000 0x158>; 959 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 960 dmas = <&fdma0 7 0 1>; 961 dma-names = "tx"; 962 963 status = "disabled"; 964 }; 965 966 sti_uni_reader0: sti-uni-reader@8d83000 { 967 compatible = "st,stih407-uni-reader-pcm_in"; 968 #sound-dai-cells = <0>; 969 st,syscfg = <&syscfg_core>; 970 reg = <0x8d83000 0x158>; 971 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 972 dmas = <&fdma0 5 0 1>; 973 dma-names = "rx"; 974 975 status = "disabled"; 976 }; 977 978 sti_uni_reader1: sti-uni-reader@8d84000 { 979 compatible = "st,stih407-uni-reader-hdmi"; 980 #sound-dai-cells = <0>; 981 st,syscfg = <&syscfg_core>; 982 reg = <0x8d84000 0x158>; 983 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 984 dmas = <&fdma0 6 0 1>; 985 dma-names = "rx"; 986 987 status = "disabled"; 988 }; 989 }; 990}; 991