1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014 STMicroelectronics R&D Limited 4 */ 5#include <dt-bindings/clock/stih407-clks.h> 6/ { 7 /* 8 * Fixed 30MHz oscillator inputs to SoC 9 */ 10 clk_sysin: clk-sysin { 11 #clock-cells = <0>; 12 compatible = "fixed-clock"; 13 clock-frequency = <30000000>; 14 }; 15 16 clk_tmdsout_hdmi: clk-tmdsout-hdmi { 17 #clock-cells = <0>; 18 compatible = "fixed-clock"; 19 clock-frequency = <0>; 20 }; 21 22 clocks { 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges; 26 27 /* 28 * A9 PLL. 29 */ 30 clockgen-a9@92b0000 { 31 compatible = "st,clkgen-c32"; 32 reg = <0x92b0000 0x10000>; 33 34 clockgen_a9_pll: clockgen-a9-pll { 35 #clock-cells = <1>; 36 compatible = "st,stih407-clkgen-plla9"; 37 38 clocks = <&clk_sysin>; 39 }; 40 41 clk_m_a9: clk-m-a9 { 42 #clock-cells = <0>; 43 compatible = "st,stih407-clkgen-a9-mux"; 44 45 clocks = <&clockgen_a9_pll 0>, 46 <&clockgen_a9_pll 0>, 47 <&clk_s_c0_flexgen 13>, 48 <&clk_m_a9_ext2f_div2>; 49 50 /* 51 * ARM Peripheral clock for timers 52 */ 53 arm_periph_clk: clk-m-a9-periphs { 54 #clock-cells = <0>; 55 compatible = "fixed-factor-clock"; 56 57 clocks = <&clk_m_a9>; 58 clock-div = <2>; 59 clock-mult = <1>; 60 }; 61 }; 62 }; 63 64 clockgen-a@90ff000 { 65 compatible = "st,clkgen-c32"; 66 reg = <0x90ff000 0x1000>; 67 68 clk_s_a0_pll: clk-s-a0-pll { 69 #clock-cells = <1>; 70 compatible = "st,clkgen-pll0-a0"; 71 72 clocks = <&clk_sysin>; 73 }; 74 75 clk_s_a0_flexgen: clk-s-a0-flexgen { 76 compatible = "st,flexgen", "st,flexgen-stih407-a0"; 77 78 #clock-cells = <1>; 79 80 clocks = <&clk_s_a0_pll 0>, 81 <&clk_sysin>; 82 }; 83 }; 84 85 clk_s_c0: clockgen-c@9103000 { 86 compatible = "st,clkgen-c32"; 87 reg = <0x9103000 0x1000>; 88 89 clk_s_c0_pll0: clk-s-c0-pll0 { 90 #clock-cells = <1>; 91 compatible = "st,clkgen-pll0-c0"; 92 93 clocks = <&clk_sysin>; 94 }; 95 96 clk_s_c0_pll1: clk-s-c0-pll1 { 97 #clock-cells = <1>; 98 compatible = "st,clkgen-pll1-c0"; 99 100 clocks = <&clk_sysin>; 101 }; 102 103 clk_s_c0_quadfs: clk-s-c0-quadfs { 104 #clock-cells = <1>; 105 compatible = "st,quadfs-pll"; 106 107 clocks = <&clk_sysin>; 108 }; 109 110 clk_s_c0_flexgen: clk-s-c0-flexgen { 111 #clock-cells = <1>; 112 compatible = "st,flexgen", "st,flexgen-stih407-c0"; 113 114 clocks = <&clk_s_c0_pll0 0>, 115 <&clk_s_c0_pll1 0>, 116 <&clk_s_c0_quadfs 0>, 117 <&clk_s_c0_quadfs 1>, 118 <&clk_s_c0_quadfs 2>, 119 <&clk_s_c0_quadfs 3>, 120 <&clk_sysin>; 121 122 /* 123 * ARM Peripheral clock for timers 124 */ 125 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 126 #clock-cells = <0>; 127 compatible = "fixed-factor-clock"; 128 129 clocks = <&clk_s_c0_flexgen 13>; 130 131 clock-output-names = "clk-m-a9-ext2f-div2"; 132 133 clock-div = <2>; 134 clock-mult = <1>; 135 }; 136 }; 137 }; 138 139 clockgen-d0@9104000 { 140 compatible = "st,clkgen-c32"; 141 reg = <0x9104000 0x1000>; 142 143 clk_s_d0_quadfs: clk-s-d0-quadfs { 144 #clock-cells = <1>; 145 compatible = "st,quadfs-d0"; 146 147 clocks = <&clk_sysin>; 148 }; 149 150 clk_s_d0_flexgen: clk-s-d0-flexgen { 151 #clock-cells = <1>; 152 compatible = "st,flexgen", "st,flexgen-stih407-d0"; 153 154 clocks = <&clk_s_d0_quadfs 0>, 155 <&clk_s_d0_quadfs 1>, 156 <&clk_s_d0_quadfs 2>, 157 <&clk_s_d0_quadfs 3>, 158 <&clk_sysin>; 159 }; 160 }; 161 162 clockgen-d2@9106000 { 163 compatible = "st,clkgen-c32"; 164 reg = <0x9106000 0x1000>; 165 166 clk_s_d2_quadfs: clk-s-d2-quadfs { 167 #clock-cells = <1>; 168 compatible = "st,quadfs-d2"; 169 170 clocks = <&clk_sysin>; 171 }; 172 173 clk_s_d2_flexgen: clk-s-d2-flexgen { 174 #clock-cells = <1>; 175 compatible = "st,flexgen", "st,flexgen-stih407-d2"; 176 177 clocks = <&clk_s_d2_quadfs 0>, 178 <&clk_s_d2_quadfs 1>, 179 <&clk_s_d2_quadfs 2>, 180 <&clk_s_d2_quadfs 3>, 181 <&clk_sysin>, 182 <&clk_sysin>, 183 <&clk_tmdsout_hdmi>; 184 }; 185 }; 186 187 clockgen-d3@9107000 { 188 compatible = "st,clkgen-c32"; 189 reg = <0x9107000 0x1000>; 190 191 clk_s_d3_quadfs: clk-s-d3-quadfs { 192 #clock-cells = <1>; 193 compatible = "st,quadfs-d3"; 194 195 clocks = <&clk_sysin>; 196 }; 197 198 clk_s_d3_flexgen: clk-s-d3-flexgen { 199 #clock-cells = <1>; 200 compatible = "st,flexgen", "st,flexgen-stih407-d3"; 201 202 clocks = <&clk_s_d3_quadfs 0>, 203 <&clk_s_d3_quadfs 1>, 204 <&clk_s_d3_quadfs 2>, 205 <&clk_s_d3_quadfs 3>, 206 <&clk_sysin>; 207 }; 208 }; 209 }; 210}; 211