1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2012 Linaro Ltd 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/ste-db8500-clkout.h> 9#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> 10#include <dt-bindings/mfd/dbx500-prcmu.h> 11#include <dt-bindings/arm/ux500_pm_domains.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 /* This stablilizes the device enumeration */ 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 spi0 = &spi0; 27 spi1 = &spi1; 28 spi2 = &spi2; 29 spi3 = &spi3; 30 serial0 = &serial0; 31 serial1 = &serial1; 32 serial2 = &serial2; 33 }; 34 35 chosen { 36 }; 37 38 cpus { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 enable-method = "ste,dbx500-smp"; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&CPU0>; 47 }; 48 core1 { 49 cpu = <&CPU1>; 50 }; 51 }; 52 }; 53 CPU0: cpu@300 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a9"; 56 reg = <0x300>; 57 clocks = <&prcmu_clk PRCMU_ARMSS>; 58 clock-names = "cpu"; 59 clock-latency = <20000>; 60 #cooling-cells = <2>; 61 }; 62 CPU1: cpu@301 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a9"; 65 reg = <0x301>; 66 }; 67 }; 68 69 thermal-zones { 70 /* 71 * Thermal zone for the SoC, using the thermal sensor in the 72 * PRCMU for temperature and the cpufreq driver for passive 73 * cooling. 74 */ 75 cpu_thermal: cpu-thermal { 76 polling-delay-passive = <250>; 77 /* 78 * This sensor fires interrupts to update the thermal 79 * zone, so no polling is needed. 80 */ 81 polling-delay = <0>; 82 83 thermal-sensors = <&thermal>; 84 85 trips { 86 cpu_alert: cpu-alert { 87 temperature = <70000>; 88 hysteresis = <2000>; 89 type = "passive"; 90 }; 91 cpu-crit { 92 temperature = <85000>; 93 hysteresis = <0>; 94 type = "critical"; 95 }; 96 }; 97 98 cooling-maps { 99 trip = <&cpu_alert>; 100 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 101 contribution = <100>; 102 }; 103 }; 104 }; 105 106 soc { 107 #address-cells = <1>; 108 #size-cells = <1>; 109 compatible = "stericsson,db8500", "simple-bus"; 110 interrupt-parent = <&intc>; 111 ranges; 112 113 /* 114 * 640KB ESRAM (embedded static random access memory), divided 115 * into 5 banks of 128 KB each. This is a fast memory usually 116 * used by different accelerators. We group these according to 117 * their power domains: ESRAM0 (always on) ESRAM 1+2 and 118 * ESRAM 3+4. 119 */ 120 sram@40000000 { 121 /* The first (always on) ESRAM 0, 128 KB */ 122 compatible = "mmio-sram"; 123 reg = <0x40000000 0x20000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0 0x40000000 0x20000>; 127 128 sram@0 { 129 compatible = "stericsson,u8500-esram"; 130 reg = <0x0 0x10000>; 131 pool; 132 }; 133 lcpa: sram@10000 { 134 /* 135 * This eSRAM is used by the DMA40 DMA controller 136 * for Logical Channel Paramers (LCP), the address 137 * where these parameters are stored is called "LCPA". 138 * This is addressed directly by the driver so no 139 * pool is used. 140 */ 141 compatible = "stericsson,u8500-esram"; 142 label = "DMA40-LCPA"; 143 reg = <0x10000 0x800>; 144 }; 145 sram@10800 { 146 compatible = "stericsson,u8500-esram"; 147 reg = <0x10800 0xf800>; 148 pool; 149 }; 150 }; 151 sram@40020000 { 152 /* ESRAM 1+2, 256 KB */ 153 compatible = "mmio-sram"; 154 reg = <0x40020000 0x40000>; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 ranges = <0 0x40020000 0x40000>; 158 }; 159 sram@40060000 { 160 /* ESRAM 3+4, 256 KB */ 161 compatible = "mmio-sram"; 162 reg = <0x40060000 0x40000>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0 0x40060000 0x40000>; 166 167 lcla: sram@20000 { 168 /* 169 * This eSRAM is used by the DMA40 DMA controller 170 * for Logical Channel Logical Addresses (LCLA), the address 171 * where these parameters are stored is called "LCLA". 172 * This is addressed directly by the driver so no 173 * pool is used. 174 */ 175 compatible = "stericsson,u8500-esram"; 176 label = "DMA40-LCLA"; 177 reg = <0x20000 0x2000>; 178 }; 179 }; 180 181 ptm@801ae000 { 182 compatible = "arm,coresight-etm3x", "arm,primecell"; 183 reg = <0x801ae000 0x1000>; 184 185 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 186 clock-names = "apb_pclk", "atclk"; 187 cpu = <&CPU0>; 188 out-ports { 189 port { 190 ptm0_out_port: endpoint { 191 remote-endpoint = <&funnel_in_port0>; 192 }; 193 }; 194 }; 195 }; 196 197 ptm@801af000 { 198 compatible = "arm,coresight-etm3x", "arm,primecell"; 199 reg = <0x801af000 0x1000>; 200 201 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 202 clock-names = "apb_pclk", "atclk"; 203 cpu = <&CPU1>; 204 out-ports { 205 port { 206 ptm1_out_port: endpoint { 207 remote-endpoint = <&funnel_in_port1>; 208 }; 209 }; 210 }; 211 }; 212 213 funnel@801a6000 { 214 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 215 reg = <0x801a6000 0x1000>; 216 217 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 218 clock-names = "apb_pclk", "atclk"; 219 out-ports { 220 port { 221 funnel_out_port: endpoint { 222 remote-endpoint = 223 <&replicator_in_port0>; 224 }; 225 }; 226 }; 227 228 in-ports { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 port@0 { 233 reg = <0>; 234 funnel_in_port0: endpoint { 235 remote-endpoint = <&ptm0_out_port>; 236 }; 237 }; 238 239 port@1 { 240 reg = <1>; 241 funnel_in_port1: endpoint { 242 remote-endpoint = <&ptm1_out_port>; 243 }; 244 }; 245 }; 246 }; 247 248 replicator { 249 compatible = "arm,coresight-static-replicator"; 250 clocks = <&prcmu_clk PRCMU_APEATCLK>; 251 clock-names = "atclk"; 252 253 out-ports { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 257 port@0 { 258 reg = <0>; 259 replicator_out_port0: endpoint { 260 remote-endpoint = <&tpiu_in_port>; 261 }; 262 }; 263 port@1 { 264 reg = <1>; 265 replicator_out_port1: endpoint { 266 remote-endpoint = <&etb_in_port>; 267 }; 268 }; 269 }; 270 271 in-ports { 272 port { 273 replicator_in_port0: endpoint { 274 remote-endpoint = <&funnel_out_port>; 275 }; 276 }; 277 }; 278 }; 279 280 tpiu@80190000 { 281 compatible = "arm,coresight-tpiu", "arm,primecell"; 282 reg = <0x80190000 0x1000>; 283 284 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 285 clock-names = "apb_pclk", "atclk"; 286 in-ports { 287 port { 288 tpiu_in_port: endpoint { 289 remote-endpoint = <&replicator_out_port0>; 290 }; 291 }; 292 }; 293 }; 294 295 etb@801a4000 { 296 compatible = "arm,coresight-etb10", "arm,primecell"; 297 reg = <0x801a4000 0x1000>; 298 299 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 300 clock-names = "apb_pclk", "atclk"; 301 in-ports { 302 port { 303 etb_in_port: endpoint { 304 remote-endpoint = <&replicator_out_port1>; 305 }; 306 }; 307 }; 308 }; 309 310 intc: interrupt-controller@a0411000 { 311 compatible = "arm,cortex-a9-gic"; 312 #interrupt-cells = <3>; 313 #address-cells = <1>; 314 interrupt-controller; 315 reg = <0xa0411000 0x1000>, 316 <0xa0410100 0x100>; 317 }; 318 319 scu@a0410000 { 320 compatible = "arm,cortex-a9-scu"; 321 reg = <0xa0410000 0x100>; 322 }; 323 324 /* 325 * The backup RAM is used for retention during sleep 326 * and various things like spin tables 327 */ 328 backupram@80150000 { 329 compatible = "ste,dbx500-backupram"; 330 reg = <0x80150000 0x2000>; 331 }; 332 333 L2: cache-controller { 334 compatible = "arm,pl310-cache"; 335 reg = <0xa0412000 0x1000>; 336 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 337 cache-unified; 338 cache-level = <2>; 339 }; 340 341 pmu { 342 compatible = "arm,cortex-a9-pmu"; 343 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 344 }; 345 346 pm_domains: pm_domains0 { 347 compatible = "stericsson,ux500-pm-domains"; 348 #power-domain-cells = <1>; 349 }; 350 351 clocks { 352 compatible = "stericsson,u8500-clks"; 353 /* 354 * Registers for the CLKRST block on peripheral 355 * groups 1, 2, 3, 5, 6, 356 */ 357 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, 358 <0x8000f000 0x1000>, <0xa03ff000 0x1000>, 359 <0xa03cf000 0x1000>; 360 361 prcmu_clk: prcmu-clock { 362 #clock-cells = <1>; 363 }; 364 365 prcc_pclk: prcc-periph-clock { 366 #clock-cells = <2>; 367 }; 368 369 prcc_kclk: prcc-kernel-clock { 370 #clock-cells = <2>; 371 }; 372 373 prcc_reset: prcc-reset-controller { 374 #reset-cells = <2>; 375 }; 376 377 rtc_clk: rtc32k-clock { 378 #clock-cells = <0>; 379 }; 380 381 smp_twd_clk: smp-twd-clock { 382 #clock-cells = <0>; 383 }; 384 385 clkout_clk: clkout-clock { 386 /* Cell 1 id, cell 2 source, cell 3 div */ 387 #clock-cells = <3>; 388 }; 389 }; 390 391 mtu@a03c6000 { 392 /* Nomadik System Timer */ 393 compatible = "st,nomadik-mtu"; 394 reg = <0xa03c6000 0x1000>; 395 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 396 397 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; 398 clock-names = "timclk", "apb_pclk"; 399 }; 400 401 timer@a0410600 { 402 compatible = "arm,cortex-a9-twd-timer"; 403 reg = <0xa0410600 0x20>; 404 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 405 406 clocks = <&smp_twd_clk>; 407 }; 408 409 watchdog@a0410620 { 410 compatible = "arm,cortex-a9-twd-wdt"; 411 reg = <0xa0410620 0x20>; 412 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 413 clocks = <&smp_twd_clk>; 414 }; 415 416 rtc@80154000 { 417 compatible = "arm,pl031", "arm,primecell"; 418 reg = <0x80154000 0x1000>; 419 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 420 421 clocks = <&rtc_clk>; 422 clock-names = "apb_pclk"; 423 }; 424 425 gpio0: gpio@8012e000 { 426 compatible = "stericsson,db8500-gpio", 427 "st,nomadik-gpio"; 428 reg = <0x8012e000 0x80>; 429 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 st,supports-sleepmode; 433 gpio-controller; 434 #gpio-cells = <2>; 435 gpio-bank = <0>; 436 gpio-ranges = <&pinctrl 0 0 32>; 437 clocks = <&prcc_pclk 1 9>; 438 }; 439 440 gpio1: gpio@8012e080 { 441 compatible = "stericsson,db8500-gpio", 442 "st,nomadik-gpio"; 443 reg = <0x8012e080 0x80>; 444 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 st,supports-sleepmode; 448 gpio-controller; 449 #gpio-cells = <2>; 450 gpio-bank = <1>; 451 gpio-ranges = <&pinctrl 0 32 5>; 452 clocks = <&prcc_pclk 1 9>; 453 }; 454 455 gpio2: gpio@8000e000 { 456 compatible = "stericsson,db8500-gpio", 457 "st,nomadik-gpio"; 458 reg = <0x8000e000 0x80>; 459 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 st,supports-sleepmode; 463 gpio-controller; 464 #gpio-cells = <2>; 465 gpio-bank = <2>; 466 gpio-ranges = <&pinctrl 0 64 32>; 467 clocks = <&prcc_pclk 3 8>; 468 }; 469 470 gpio3: gpio@8000e080 { 471 compatible = "stericsson,db8500-gpio", 472 "st,nomadik-gpio"; 473 reg = <0x8000e080 0x80>; 474 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 st,supports-sleepmode; 478 gpio-controller; 479 #gpio-cells = <2>; 480 gpio-bank = <3>; 481 gpio-ranges = <&pinctrl 0 96 2>; 482 clocks = <&prcc_pclk 3 8>; 483 }; 484 485 gpio4: gpio@8000e100 { 486 compatible = "stericsson,db8500-gpio", 487 "st,nomadik-gpio"; 488 reg = <0x8000e100 0x80>; 489 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 st,supports-sleepmode; 493 gpio-controller; 494 #gpio-cells = <2>; 495 gpio-bank = <4>; 496 gpio-ranges = <&pinctrl 0 128 32>; 497 clocks = <&prcc_pclk 3 8>; 498 }; 499 500 gpio5: gpio@8000e180 { 501 compatible = "stericsson,db8500-gpio", 502 "st,nomadik-gpio"; 503 reg = <0x8000e180 0x80>; 504 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 st,supports-sleepmode; 508 gpio-controller; 509 #gpio-cells = <2>; 510 gpio-bank = <5>; 511 gpio-ranges = <&pinctrl 0 160 12>; 512 clocks = <&prcc_pclk 3 8>; 513 }; 514 515 gpio6: gpio@8011e000 { 516 compatible = "stericsson,db8500-gpio", 517 "st,nomadik-gpio"; 518 reg = <0x8011e000 0x80>; 519 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 st,supports-sleepmode; 523 gpio-controller; 524 #gpio-cells = <2>; 525 gpio-bank = <6>; 526 gpio-ranges = <&pinctrl 0 192 32>; 527 clocks = <&prcc_pclk 2 11>; 528 }; 529 530 gpio7: gpio@8011e080 { 531 compatible = "stericsson,db8500-gpio", 532 "st,nomadik-gpio"; 533 reg = <0x8011e080 0x80>; 534 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 st,supports-sleepmode; 538 gpio-controller; 539 #gpio-cells = <2>; 540 gpio-bank = <7>; 541 gpio-ranges = <&pinctrl 0 224 7>; 542 clocks = <&prcc_pclk 2 11>; 543 }; 544 545 gpio8: gpio@a03fe000 { 546 compatible = "stericsson,db8500-gpio", 547 "st,nomadik-gpio"; 548 reg = <0xa03fe000 0x80>; 549 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 st,supports-sleepmode; 553 gpio-controller; 554 #gpio-cells = <2>; 555 gpio-bank = <8>; 556 gpio-ranges = <&pinctrl 0 256 12>; 557 clocks = <&prcc_pclk 5 1>; 558 }; 559 560 pinctrl: pinctrl { 561 compatible = "stericsson,db8500-pinctrl"; 562 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, 563 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, 564 <&gpio8>; 565 prcm = <&prcmu>; 566 }; 567 568 usb_per5@a03e0000 { 569 compatible = "stericsson,db8500-musb"; 570 reg = <0xa03e0000 0x10000>; 571 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 572 interrupt-names = "mc"; 573 574 dr_mode = "otg"; 575 576 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ 577 <&dma 38 0 0x0>, /* Logical - MemToDev */ 578 <&dma 37 0 0x2>, /* Logical - DevToMem */ 579 <&dma 37 0 0x0>, /* Logical - MemToDev */ 580 <&dma 36 0 0x2>, /* Logical - DevToMem */ 581 <&dma 36 0 0x0>, /* Logical - MemToDev */ 582 <&dma 19 0 0x2>, /* Logical - DevToMem */ 583 <&dma 19 0 0x0>, /* Logical - MemToDev */ 584 <&dma 18 0 0x2>, /* Logical - DevToMem */ 585 <&dma 18 0 0x0>, /* Logical - MemToDev */ 586 <&dma 17 0 0x2>, /* Logical - DevToMem */ 587 <&dma 17 0 0x0>, /* Logical - MemToDev */ 588 <&dma 16 0 0x2>, /* Logical - DevToMem */ 589 <&dma 16 0 0x0>, /* Logical - MemToDev */ 590 <&dma 39 0 0x2>, /* Logical - DevToMem */ 591 <&dma 39 0 0x0>; /* Logical - MemToDev */ 592 593 dma-names = "iep_1_9", "oep_1_9", 594 "iep_2_10", "oep_2_10", 595 "iep_3_11", "oep_3_11", 596 "iep_4_12", "oep_4_12", 597 "iep_5_13", "oep_5_13", 598 "iep_6_14", "oep_6_14", 599 "iep_7_15", "oep_7_15", 600 "iep_8", "oep_8"; 601 602 clocks = <&prcc_pclk 5 0>; 603 }; 604 605 dma: dma-controller@801C0000 { 606 compatible = "stericsson,db8500-dma40", "stericsson,dma40"; 607 reg = <0x801C0000 0x1000>; 608 reg-names = "base"; 609 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 610 sram = <&lcpa>, <&lcla>; 611 612 #dma-cells = <3>; 613 memcpy-channels = <56 57 58 59 60>; 614 615 clocks = <&prcmu_clk PRCMU_DMACLK>; 616 }; 617 618 prcmu: prcmu@80157000 { 619 compatible = "stericsson,db8500-prcmu", "syscon"; 620 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; 621 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; 622 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 623 #address-cells = <1>; 624 #size-cells = <1>; 625 interrupt-controller; 626 #interrupt-cells = <2>; 627 ranges; 628 629 prcmu-timer-4@80157450 { 630 compatible = "stericsson,db8500-prcmu-timer-4"; 631 reg = <0x80157450 0xC>; 632 }; 633 634 thermal: thermal@801573c0 { 635 compatible = "stericsson,db8500-thermal"; 636 reg = <0x801573c0 0x40>; 637 interrupt-parent = <&prcmu>; 638 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, 639 <22 IRQ_TYPE_LEVEL_HIGH>; 640 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; 641 #thermal-sensor-cells = <0>; 642 }; 643 644 db8500-prcmu-regulators { 645 compatible = "stericsson,db8500-prcmu-regulator"; 646 647 // DB8500_REGULATOR_VAPE 648 db8500_vape_reg: db8500_vape { 649 regulator-always-on; 650 }; 651 652 // DB8500_REGULATOR_VARM 653 db8500_varm_reg: db8500_varm { 654 }; 655 656 // DB8500_REGULATOR_VMODEM 657 db8500_vmodem_reg: db8500_vmodem { 658 }; 659 660 // DB8500_REGULATOR_VPLL 661 db8500_vpll_reg: db8500_vpll { 662 }; 663 664 // DB8500_REGULATOR_VSMPS1 665 db8500_vsmps1_reg: db8500_vsmps1 { 666 }; 667 668 // DB8500_REGULATOR_VSMPS2 669 db8500_vsmps2_reg: db8500_vsmps2 { 670 }; 671 672 // DB8500_REGULATOR_VSMPS3 673 db8500_vsmps3_reg: db8500_vsmps3 { 674 }; 675 676 // DB8500_REGULATOR_VRF1 677 db8500_vrf1_reg: db8500_vrf1 { 678 }; 679 680 // DB8500_REGULATOR_SWITCH_SVAMMDSP 681 db8500_sva_mmdsp_reg: db8500_sva_mmdsp { 682 }; 683 684 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET 685 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { 686 }; 687 688 // DB8500_REGULATOR_SWITCH_SVAPIPE 689 db8500_sva_pipe_reg: db8500_sva_pipe { 690 }; 691 692 // DB8500_REGULATOR_SWITCH_SIAMMDSP 693 db8500_sia_mmdsp_reg: db8500_sia_mmdsp { 694 }; 695 696 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET 697 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { 698 }; 699 700 // DB8500_REGULATOR_SWITCH_SIAPIPE 701 db8500_sia_pipe_reg: db8500_sia_pipe { 702 }; 703 704 // DB8500_REGULATOR_SWITCH_SGA 705 db8500_sga_reg: db8500_sga { 706 vin-supply = <&db8500_vape_reg>; 707 }; 708 709 // DB8500_REGULATOR_SWITCH_B2R2_MCDE 710 db8500_b2r2_mcde_reg: db8500_b2r2_mcde { 711 vin-supply = <&db8500_vape_reg>; 712 }; 713 714 // DB8500_REGULATOR_SWITCH_ESRAM12 715 db8500_esram12_reg: db8500_esram12 { 716 }; 717 718 // DB8500_REGULATOR_SWITCH_ESRAM12RET 719 db8500_esram12_ret_reg: db8500_esram12_ret { 720 }; 721 722 // DB8500_REGULATOR_SWITCH_ESRAM34 723 db8500_esram34_reg: db8500_esram34 { 724 }; 725 726 // DB8500_REGULATOR_SWITCH_ESRAM34RET 727 db8500_esram34_ret_reg: db8500_esram34_ret { 728 }; 729 }; 730 }; 731 732 i2c0: i2c@80004000 { 733 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 734 reg = <0x80004000 0x1000>; 735 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 736 737 #address-cells = <1>; 738 #size-cells = <0>; 739 740 clock-frequency = <400000>; 741 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; 742 clock-names = "i2cclk", "apb_pclk"; 743 power-domains = <&pm_domains DOMAIN_VAPE>; 744 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; 745 746 status = "disabled"; 747 }; 748 749 i2c1: i2c@80122000 { 750 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 751 reg = <0x80122000 0x1000>; 752 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 753 754 #address-cells = <1>; 755 #size-cells = <0>; 756 757 clock-frequency = <400000>; 758 759 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; 760 clock-names = "i2cclk", "apb_pclk"; 761 power-domains = <&pm_domains DOMAIN_VAPE>; 762 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; 763 764 status = "disabled"; 765 }; 766 767 i2c2: i2c@80128000 { 768 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 769 reg = <0x80128000 0x1000>; 770 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 771 772 #address-cells = <1>; 773 #size-cells = <0>; 774 775 clock-frequency = <400000>; 776 777 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; 778 clock-names = "i2cclk", "apb_pclk"; 779 power-domains = <&pm_domains DOMAIN_VAPE>; 780 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; 781 782 status = "disabled"; 783 }; 784 785 i2c3: i2c@80110000 { 786 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 787 reg = <0x80110000 0x1000>; 788 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 789 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 clock-frequency = <400000>; 794 795 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; 796 clock-names = "i2cclk", "apb_pclk"; 797 power-domains = <&pm_domains DOMAIN_VAPE>; 798 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; 799 800 status = "disabled"; 801 }; 802 803 i2c4: i2c@8012a000 { 804 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 805 reg = <0x8012a000 0x1000>; 806 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 807 808 #address-cells = <1>; 809 #size-cells = <0>; 810 811 clock-frequency = <400000>; 812 813 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; 814 clock-names = "i2cclk", "apb_pclk"; 815 power-domains = <&pm_domains DOMAIN_VAPE>; 816 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; 817 818 status = "disabled"; 819 }; 820 821 ssp0: spi@80002000 { 822 compatible = "arm,pl022", "arm,primecell"; 823 reg = <0x80002000 0x1000>; 824 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; 828 clock-names = "sspclk", "apb_pclk"; 829 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ 830 <&dma 8 0 0x0>; /* Logical - MemToDev */ 831 dma-names = "rx", "tx"; 832 power-domains = <&pm_domains DOMAIN_VAPE>; 833 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; 834 835 status = "disabled"; 836 }; 837 838 ssp1: spi@80003000 { 839 compatible = "arm,pl022", "arm,primecell"; 840 reg = <0x80003000 0x1000>; 841 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; 845 clock-names = "sspclk", "apb_pclk"; 846 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ 847 <&dma 9 0 0x0>; /* Logical - MemToDev */ 848 dma-names = "rx", "tx"; 849 power-domains = <&pm_domains DOMAIN_VAPE>; 850 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; 851 852 status = "disabled"; 853 }; 854 855 spi0: spi@8011a000 { 856 compatible = "arm,pl022", "arm,primecell"; 857 reg = <0x8011a000 0x1000>; 858 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 /* Same clock wired to kernel and pclk */ 862 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; 863 clock-names = "sspclk", "apb_pclk"; 864 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ 865 <&dma 0 0 0x0>; /* Logical - MemToDev */ 866 dma-names = "rx", "tx"; 867 power-domains = <&pm_domains DOMAIN_VAPE>; 868 869 status = "disabled"; 870 }; 871 872 spi1: spi@80112000 { 873 compatible = "arm,pl022", "arm,primecell"; 874 reg = <0x80112000 0x1000>; 875 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 /* Same clock wired to kernel and pclk */ 879 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; 880 clock-names = "sspclk", "apb_pclk"; 881 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ 882 <&dma 35 0 0x0>; /* Logical - MemToDev */ 883 dma-names = "rx", "tx"; 884 power-domains = <&pm_domains DOMAIN_VAPE>; 885 886 status = "disabled"; 887 }; 888 889 spi2: spi@80111000 { 890 compatible = "arm,pl022", "arm,primecell"; 891 reg = <0x80111000 0x1000>; 892 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 /* Same clock wired to kernel and pclk */ 896 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; 897 clock-names = "sspclk", "apb_pclk"; 898 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ 899 <&dma 33 0 0x0>; /* Logical - MemToDev */ 900 dma-names = "rx", "tx"; 901 power-domains = <&pm_domains DOMAIN_VAPE>; 902 903 status = "disabled"; 904 }; 905 906 spi3: spi@80129000 { 907 compatible = "arm,pl022", "arm,primecell"; 908 reg = <0x80129000 0x1000>; 909 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 /* Same clock wired to kernel and pclk */ 913 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; 914 clock-names = "sspclk", "apb_pclk"; 915 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ 916 <&dma 40 0 0x0>; /* Logical - MemToDev */ 917 dma-names = "rx", "tx"; 918 power-domains = <&pm_domains DOMAIN_VAPE>; 919 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; 920 921 status = "disabled"; 922 }; 923 924 serial0: serial@80120000 { 925 compatible = "arm,pl011", "arm,primecell"; 926 reg = <0x80120000 0x1000>; 927 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 928 929 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ 930 <&dma 13 0 0x0>; /* Logical - MemToDev */ 931 dma-names = "rx", "tx"; 932 933 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; 934 clock-names = "uart", "apb_pclk"; 935 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; 936 937 status = "disabled"; 938 }; 939 940 serial1: serial@80121000 { 941 compatible = "arm,pl011", "arm,primecell"; 942 reg = <0x80121000 0x1000>; 943 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 944 945 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ 946 <&dma 12 0 0x0>; /* Logical - MemToDev */ 947 dma-names = "rx", "tx"; 948 949 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; 950 clock-names = "uart", "apb_pclk"; 951 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; 952 953 status = "disabled"; 954 }; 955 956 serial2: serial@80007000 { 957 compatible = "arm,pl011", "arm,primecell"; 958 reg = <0x80007000 0x1000>; 959 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 960 961 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ 962 <&dma 11 0 0x0>; /* Logical - MemToDev */ 963 dma-names = "rx", "tx"; 964 965 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; 966 clock-names = "uart", "apb_pclk"; 967 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; 968 969 status = "disabled"; 970 }; 971 972 mmc@80126000 { 973 compatible = "arm,pl18x", "arm,primecell"; 974 reg = <0x80126000 0x1000>; 975 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 976 977 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ 978 <&dma 29 0 0x0>; /* Logical - MemToDev */ 979 dma-names = "rx", "tx"; 980 981 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; 982 clock-names = "sdi", "apb_pclk"; 983 power-domains = <&pm_domains DOMAIN_VAPE>; 984 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; 985 986 status = "disabled"; 987 }; 988 989 mmc@80118000 { 990 compatible = "arm,pl18x", "arm,primecell"; 991 reg = <0x80118000 0x1000>; 992 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 993 994 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ 995 <&dma 32 0 0x0>; /* Logical - MemToDev */ 996 dma-names = "rx", "tx"; 997 998 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; 999 clock-names = "sdi", "apb_pclk"; 1000 power-domains = <&pm_domains DOMAIN_VAPE>; 1001 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; 1002 1003 status = "disabled"; 1004 }; 1005 1006 mmc@80005000 { 1007 compatible = "arm,pl18x", "arm,primecell"; 1008 reg = <0x80005000 0x1000>; 1009 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1010 1011 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ 1012 <&dma 28 0 0x0>; /* Logical - MemToDev */ 1013 dma-names = "rx", "tx"; 1014 1015 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; 1016 clock-names = "sdi", "apb_pclk"; 1017 power-domains = <&pm_domains DOMAIN_VAPE>; 1018 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; 1019 1020 status = "disabled"; 1021 }; 1022 1023 mmc@80119000 { 1024 compatible = "arm,pl18x", "arm,primecell"; 1025 reg = <0x80119000 0x1000>; 1026 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1027 1028 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ 1029 <&dma 41 0 0x0>; /* Logical - MemToDev */ 1030 dma-names = "rx", "tx"; 1031 1032 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; 1033 clock-names = "sdi", "apb_pclk"; 1034 power-domains = <&pm_domains DOMAIN_VAPE>; 1035 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; 1036 1037 status = "disabled"; 1038 }; 1039 1040 mmc@80114000 { 1041 compatible = "arm,pl18x", "arm,primecell"; 1042 reg = <0x80114000 0x1000>; 1043 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1044 1045 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ 1046 <&dma 42 0 0x0>; /* Logical - MemToDev */ 1047 dma-names = "rx", "tx"; 1048 1049 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; 1050 clock-names = "sdi", "apb_pclk"; 1051 power-domains = <&pm_domains DOMAIN_VAPE>; 1052 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; 1053 1054 status = "disabled"; 1055 }; 1056 1057 mmc@80008000 { 1058 compatible = "arm,pl18x", "arm,primecell"; 1059 reg = <0x80008000 0x1000>; 1060 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1061 1062 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ 1063 <&dma 43 0 0x0>; /* Logical - MemToDev */ 1064 dma-names = "rx", "tx"; 1065 1066 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; 1067 clock-names = "sdi", "apb_pclk"; 1068 power-domains = <&pm_domains DOMAIN_VAPE>; 1069 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; 1070 1071 status = "disabled"; 1072 }; 1073 1074 sound { 1075 compatible = "stericsson,snd-soc-mop500"; 1076 stericsson,cpu-dai = <&msp1 &msp3>; 1077 }; 1078 1079 msp0: msp@80123000 { 1080 compatible = "stericsson,ux500-msp-i2s"; 1081 reg = <0x80123000 0x1000>; 1082 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1083 v-ape-supply = <&db8500_vape_reg>; 1084 1085 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ 1086 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ 1087 dma-names = "rx", "tx"; 1088 1089 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; 1090 clock-names = "msp", "apb_pclk"; 1091 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; 1092 1093 status = "disabled"; 1094 }; 1095 1096 msp1: msp@80124000 { 1097 compatible = "stericsson,ux500-msp-i2s"; 1098 reg = <0x80124000 0x1000>; 1099 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1100 v-ape-supply = <&db8500_vape_reg>; 1101 1102 /* This DMA channel only exist on DB8500 v1 */ 1103 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ 1104 dma-names = "tx"; 1105 1106 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; 1107 clock-names = "msp", "apb_pclk"; 1108 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; 1109 1110 status = "disabled"; 1111 }; 1112 1113 // HDMI sound 1114 msp2: msp@80117000 { 1115 compatible = "stericsson,ux500-msp-i2s"; 1116 reg = <0x80117000 0x1000>; 1117 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1118 v-ape-supply = <&db8500_vape_reg>; 1119 1120 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ 1121 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev 1122 HighPrio - Fixed */ 1123 dma-names = "rx", "tx"; 1124 1125 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; 1126 clock-names = "msp", "apb_pclk"; 1127 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; 1128 1129 status = "disabled"; 1130 }; 1131 1132 msp3: msp@80125000 { 1133 compatible = "stericsson,ux500-msp-i2s"; 1134 reg = <0x80125000 0x1000>; 1135 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1136 v-ape-supply = <&db8500_vape_reg>; 1137 1138 /* This DMA channel only exist on DB8500 v2 */ 1139 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ 1140 dma-names = "rx"; 1141 1142 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; 1143 clock-names = "msp", "apb_pclk"; 1144 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; 1145 1146 status = "disabled"; 1147 }; 1148 1149 external-bus@50000000 { 1150 compatible = "simple-bus"; 1151 reg = <0x50000000 0x4000000>; 1152 #address-cells = <1>; 1153 #size-cells = <1>; 1154 ranges = <0 0x50000000 0x4000000>; 1155 status = "disabled"; 1156 }; 1157 1158 gpu@a0300000 { 1159 /* 1160 * This block is referred to as "Smart Graphics Adapter SGA500" 1161 * in documentation but is in practice a pretty straight-forward 1162 * MALI-400 GPU block. 1163 */ 1164 compatible = "stericsson,db8500-mali", "arm,mali-400"; 1165 reg = <0xa0300000 0x10000>; 1166 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "gp", 1172 "gpmmu", 1173 "pp0", 1174 "ppmmu0", 1175 "combined"; 1176 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; 1177 clock-names = "bus", "core"; 1178 mali-supply = <&db8500_sga_reg>; 1179 power-domains = <&pm_domains DOMAIN_VAPE>; 1180 }; 1181 1182 mcde@a0350000 { 1183 compatible = "ste,mcde"; 1184 reg = <0xa0350000 0x1000>; 1185 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1186 epod-supply = <&db8500_b2r2_mcde_reg>; 1187 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ 1188 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ 1189 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ 1190 clock-names = "mcde", "lcd", "hdmi"; 1191 #address-cells = <1>; 1192 #size-cells = <1>; 1193 ranges; 1194 status = "disabled"; 1195 1196 dsi0: dsi@a0351000 { 1197 compatible = "ste,mcde-dsi"; 1198 reg = <0xa0351000 0x1000>; 1199 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; 1200 clock-names = "hs", "lp"; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 }; 1204 dsi1: dsi@a0352000 { 1205 compatible = "ste,mcde-dsi"; 1206 reg = <0xa0352000 0x1000>; 1207 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; 1208 clock-names = "hs", "lp"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 }; 1212 dsi2: dsi@a0353000 { 1213 compatible = "ste,mcde-dsi"; 1214 reg = <0xa0353000 0x1000>; 1215 /* This DSI port only has the Low Power / Energy Save clock */ 1216 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; 1217 clock-names = "lp"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 }; 1221 }; 1222 1223 cryp@a03cb000 { 1224 compatible = "stericsson,ux500-cryp"; 1225 reg = <0xa03cb000 0x1000>; 1226 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&prcc_pclk 6 1>; 1228 power-domains = <&pm_domains DOMAIN_VAPE>; 1229 }; 1230 1231 hash@a03c2000 { 1232 compatible = "stericsson,ux500-hash"; 1233 reg = <0xa03c2000 0x1000>; 1234 clocks = <&prcc_pclk 6 2>; 1235 power-domains = <&pm_domains DOMAIN_VAPE>; 1236 }; 1237 }; 1238}; 1239