xref: /freebsd/sys/contrib/device-tree/src/arm/st/ste-dbx5x0-pinctrl.dtsi (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Linaro Ltd.
4 */
5
6#include "ste-nomadik-pinctrl.dtsi"
7
8&pinctrl {
9	/* Settings for all UART default and sleep states */
10	uart0 {
11		u0_a_1_default: u0_a_1_default {
12			default_mux {
13				function = "u0";
14				groups = "u0_a_1";
15			};
16			default_cfg1 {
17				pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
18				ste,config = <&in_pu>;
19			};
20			default_cfg2 {
21				pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
22				ste,config = <&out_hi>;
23			};
24		};
25
26		u0_a_1_sleep: u0_a_1_sleep {
27			sleep_cfg1 {
28				pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
29				ste,config = <&slpm_in_wkup_pdis>;
30			};
31			sleep_cfg2 {
32				pins = "GPIO1_AJ3"; /* RTS */
33				ste,config = <&slpm_out_hi_wkup_pdis>;
34			};
35			sleep_cfg3 {
36				pins = "GPIO3_AH3"; /* TXD */
37				ste,config = <&slpm_out_wkup_pdis>;
38			};
39		};
40	};
41
42	uart1 {
43		u1rxtx_a_1_default: u1rxtx_a_1_default {
44			default_mux {
45				function = "u1";
46				groups = "u1rxtx_a_1";
47			};
48			default_cfg1 {
49				pins = "GPIO4_AH6"; /* RXD */
50				ste,config = <&in_pu>;
51			};
52			default_cfg2 {
53				pins = "GPIO5_AG6"; /* TXD */
54				ste,config = <&out_hi>;
55			};
56		};
57
58		u1rxtx_a_1_sleep: u1rxtx_a_1_sleep {
59			sleep_cfg1 {
60				pins = "GPIO4_AH6"; /* RXD */
61				ste,config = <&slpm_in_wkup_pdis>;
62			};
63			sleep_cfg2 {
64				pins = "GPIO5_AG6"; /* TXD */
65				ste,config = <&slpm_out_wkup_pdis>;
66			};
67		};
68
69		u1ctsrts_a_1_default: u1ctsrts_a_1_default {
70			default_mux {
71				function = "u1";
72				groups = "u1ctsrts_a_1";
73			};
74			default_cfg1 {
75				pins = "GPIO6_AF6"; /* CTS */
76				ste,config = <&in_pu>;
77			};
78			default_cfg2 {
79				pins = "GPIO7_AG5"; /* RTS */
80				ste,config = <&out_hi>;
81			};
82		};
83
84		u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep {
85			sleep_cfg1 {
86				pins = "GPIO6_AF6"; /* CTS */
87				ste,config = <&slpm_in_wkup_pdis>;
88			};
89			sleep_cfg2 {
90				pins = "GPIO7_AG5"; /* RTS */
91				ste,config = <&slpm_out_hi_wkup_pdis>;
92			};
93		};
94	};
95
96	uart2 {
97		u2rxtx_c_1_default: u2rxtx_c_1_default {
98			default_mux {
99				function = "u2";
100				groups = "u2rxtx_c_1";
101			};
102			default_cfg1 {
103				pins = "GPIO29_W2"; /* RXD */
104				ste,config = <&in_pu>;
105			};
106			default_cfg2 {
107				pins = "GPIO30_W3"; /* TXD */
108				ste,config = <&out_hi>;
109			};
110		};
111
112		u2rxtx_c_1_sleep: u2rxtx_c_1_sleep {
113			sleep_cfg1 {
114				pins = "GPIO29_W2"; /* RXD */
115				ste,config = <&in_wkup_pdis>;
116			};
117			sleep_cfg2 {
118				pins = "GPIO30_W3"; /* TXD */
119				ste,config = <&out_wkup_pdis>;
120			};
121		};
122	};
123
124	/* Settings for all I2C default and sleep states */
125	i2c0 {
126		i2c0_a_1_default: i2c0_a_1_default {
127			default_mux {
128				function = "i2c0";
129				groups = "i2c0_a_1";
130			};
131			default_cfg1 {
132				pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
133				ste,config = <&in_nopull>;
134			};
135		};
136
137		i2c0_a_1_sleep: i2c0_a_1_sleep {
138			sleep_cfg1 {
139				pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
140				ste,config = <&slpm_in_wkup_pdis>;
141			};
142		};
143	};
144
145	i2c1 {
146		i2c1_b_2_default: i2c1_b_2_default {
147			default_mux {
148				function = "i2c1";
149				groups = "i2c1_b_2";
150			};
151			default_cfg1 {
152				pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
153				ste,config = <&in_nopull>;
154			};
155		};
156
157		i2c1_b_2_sleep: i2c1_b_2_sleep {
158			sleep_cfg1 {
159				pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
160				ste,config = <&slpm_in_wkup_pdis>;
161			};
162		};
163	};
164
165	i2c2 {
166		i2c2_b_1_default: i2c2_b_1_default {
167			default_mux {
168				function = "i2c2";
169				groups = "i2c2_b_1";
170			};
171			default_cfg1 {
172				pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
173				ste,config = <&in_nopull>;
174			};
175		};
176
177		i2c2_b_1_sleep: i2c2_b_1_sleep {
178			sleep_cfg1 {
179				pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
180				ste,config = <&slpm_in_wkup_pdis>;
181			};
182		};
183
184		i2c2_b_2_default: i2c2_b_2_default {
185			default_mux {
186				function = "i2c2";
187				groups = "i2c2_b_2";
188			};
189			default_cfg1 {
190				pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
191				ste,config = <&in_nopull>;
192			};
193		};
194
195		i2c2_b_2_sleep: i2c2_b_2_sleep {
196			sleep_cfg1 {
197				pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
198				ste,config = <&slpm_in_wkup_pdis>;
199			};
200		};
201	};
202
203	i2c3 {
204		i2c3_c_2_default: i2c3_c_2_default {
205			default_mux {
206				function = "i2c3";
207				groups = "i2c3_c_2";
208			};
209			default_cfg1 {
210				pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
211				ste,config = <&in_nopull>;
212			};
213		};
214
215		i2c3_c_2_sleep: i2c3_c_2_sleep {
216			sleep_cfg1 {
217				pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
218				ste,config = <&slpm_in_wkup_pdis>;
219			};
220		};
221	};
222
223	/*
224	 * Activating I2C4 will conflict with UART1 about the same pins so do not
225	 * enable I2C4 and UART1 at the same time.
226	 */
227	i2c4 {
228		i2c4_b_1_default: i2c4_b_1_default {
229			default_mux {
230				function = "i2c4";
231				groups = "i2c4_b_1";
232			};
233			default_cfg1 {
234				pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
235				ste,config = <&in_nopull>;
236			};
237		};
238
239		i2c4_b_1_sleep: i2c4_b_1_sleep {
240			sleep_cfg1 {
241				pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
242				ste,config = <&slpm_in_wkup_pdis>;
243			};
244		};
245	};
246
247	/* Settings for all MMC/SD/SDIO default and sleep states */
248	sdi0 {
249		/* This is the external SD card slot, 4 bits wide */
250		mc0_a_1_default: mc0_a_1_default {
251			default_mux {
252				function = "mc0";
253				groups = "mc0_a_1";
254			};
255			default_cfg1 {
256				pins =
257				"GPIO18_AC2", /* CMDDIR */
258				"GPIO19_AC1", /* DAT0DIR */
259				"GPIO20_AB4"; /* DAT2DIR */
260				ste,config = <&out_hi>;
261			};
262			default_cfg2 {
263				pins = "GPIO22_AA3"; /* FBCLK */
264				ste,config = <&in_nopull>;
265			};
266			default_cfg3 {
267				pins = "GPIO23_AA4"; /* CLK */
268				ste,config = <&out_lo>;
269			};
270			default_cfg4 {
271				pins =
272				"GPIO24_AB2", /* CMD */
273				"GPIO25_Y4", /* DAT0 */
274				"GPIO26_Y2", /* DAT1 */
275				"GPIO27_AA2", /* DAT2 */
276				"GPIO28_AA1"; /* DAT3 */
277				ste,config = <&in_pu>;
278			};
279		};
280
281		mc0_a_1_sleep: mc0_a_1_sleep {
282			sleep_cfg1 {
283				pins =
284				"GPIO18_AC2", /* CMDDIR */
285				"GPIO19_AC1", /* DAT0DIR */
286				"GPIO20_AB4"; /* DAT2DIR */
287				ste,config = <&slpm_out_hi_wkup_pdis>;
288			};
289			sleep_cfg2 {
290				pins =
291				"GPIO22_AA3", /* FBCLK */
292				"GPIO24_AB2", /* CMD */
293				"GPIO25_Y4", /* DAT0 */
294				"GPIO26_Y2", /* DAT1 */
295				"GPIO27_AA2", /* DAT2 */
296				"GPIO28_AA1"; /* DAT3 */
297				ste,config = <&slpm_in_wkup_pdis>;
298			};
299			sleep_cfg3 {
300				pins = "GPIO23_AA4"; /* CLK */
301				ste,config = <&slpm_out_lo_wkup_pdis>;
302			};
303		};
304
305		mc0_a_2_default: mc0_a_2_default {
306			default_mux {
307				function = "mc0";
308				groups = "mc0_a_2";
309			};
310			default_cfg1 {
311				pins = "GPIO22_AA3"; /* FBCLK */
312				ste,config = <&in_nopull>;
313			};
314			default_cfg2 {
315				pins = "GPIO23_AA4"; /* CLK */
316				ste,config = <&out_lo>;
317			};
318			default_cfg3 {
319				pins =
320				"GPIO24_AB2", /* CMD */
321				"GPIO25_Y4", /* DAT0 */
322				"GPIO26_Y2", /* DAT1 */
323				"GPIO27_AA2", /* DAT2 */
324				"GPIO28_AA1"; /* DAT3 */
325				ste,config = <&in_pu>;
326			};
327		};
328
329		mc0_a_2_sleep: mc0_a_2_sleep {
330			sleep_cfg1 {
331				pins =
332				"GPIO22_AA3", /* FBCLK */
333				"GPIO24_AB2", /* CMD */
334				"GPIO25_Y4", /* DAT0 */
335				"GPIO26_Y2", /* DAT1 */
336				"GPIO27_AA2", /* DAT2 */
337				"GPIO28_AA1"; /* DAT3 */
338				ste,config = <&slpm_in_wkup_pdis>;
339			};
340			sleep_cfg2 {
341				pins = "GPIO23_AA4"; /* CLK */
342				ste,config = <&slpm_out_lo_wkup_pdis>;
343			};
344		};
345	};
346
347	sdi1 {
348		/* This is the WLAN SDIO 4 bits wide */
349		mc1_a_1_default: mc1_a_1_default {
350			default_mux {
351				function = "mc1";
352				groups = "mc1_a_1";
353			};
354			default_cfg1 {
355				pins = "GPIO208_AH16"; /* CLK */
356				ste,config = <&out_lo>;
357			};
358			default_cfg2 {
359				pins = "GPIO209_AG15"; /* FBCLK */
360				ste,config = <&in_nopull>;
361			};
362			default_cfg3 {
363				pins =
364				"GPIO210_AJ15", /* CMD */
365				"GPIO211_AG14", /* DAT0 */
366				"GPIO212_AF13", /* DAT1 */
367				"GPIO213_AG13", /* DAT2 */
368				"GPIO214_AH15"; /* DAT3 */
369				ste,config = <&in_pu>;
370			};
371		};
372
373		mc1_a_1_sleep: mc1_a_1_sleep {
374			sleep_cfg1 {
375				pins = "GPIO208_AH16"; /* CLK */
376				ste,config = <&slpm_out_lo_wkup_pdis>;
377			};
378			sleep_cfg2 {
379				pins =
380				"GPIO209_AG15", /* FBCLK */
381				"GPIO210_AJ15", /* CMD */
382				"GPIO211_AG14", /* DAT0 */
383				"GPIO212_AF13", /* DAT1 */
384				"GPIO213_AG13", /* DAT2 */
385				"GPIO214_AH15"; /* DAT3 */
386				ste,config = <&slpm_in_wkup_pdis>;
387			};
388		};
389
390		mc1_a_2_default: mc1_a_2_default {
391			default_mux {
392				function = "mc1";
393				groups = "mc1_a_2";
394			};
395			default_cfg1 {
396				pins = "GPIO208_AH16"; /* CLK */
397				ste,config = <&out_lo>;
398			};
399			default_cfg2 {
400				pins =
401				"GPIO210_AJ15", /* CMD */
402				"GPIO211_AG14", /* DAT0 */
403				"GPIO212_AF13", /* DAT1 */
404				"GPIO213_AG13", /* DAT2 */
405				"GPIO214_AH15"; /* DAT3 */
406				ste,config = <&in_pu>;
407			};
408		};
409
410		mc1_a_2_sleep: mc1_a_2_sleep {
411			sleep_cfg1 {
412				pins = "GPIO208_AH16"; /* CLK */
413				ste,config = <&slpm_out_lo_wkup_pdis>;
414			};
415			sleep_cfg2 {
416				pins =
417				"GPIO210_AJ15", /* CMD */
418				"GPIO211_AG14", /* DAT0 */
419				"GPIO212_AF13", /* DAT1 */
420				"GPIO213_AG13", /* DAT2 */
421				"GPIO214_AH15"; /* DAT3 */
422				ste,config = <&slpm_in_wkup_pdis>;
423			};
424		};
425	};
426
427	sdi2 {
428		/* This is the eMMC 8 bits wide, usually PoP eMMC */
429		mc2_a_1_default: mc2_a_1_default {
430			default_mux {
431				function = "mc2";
432				groups = "mc2_a_1";
433			};
434			default_cfg1 {
435				pins = "GPIO128_A5"; /* CLK */
436				ste,config = <&out_lo>;
437			};
438			default_cfg2 {
439				pins = "GPIO130_C8"; /* FBCLK */
440				ste,config = <&in_nopull>;
441			};
442			default_cfg3 {
443				pins =
444				"GPIO129_B4", /* CMD */
445				"GPIO131_A12", /* DAT0 */
446				"GPIO132_C10", /* DAT1 */
447				"GPIO133_B10", /* DAT2 */
448				"GPIO134_B9", /* DAT3 */
449				"GPIO135_A9", /* DAT4 */
450				"GPIO136_C7", /* DAT5 */
451				"GPIO137_A7", /* DAT6 */
452				"GPIO138_C5"; /* DAT7 */
453				ste,config = <&in_pu>;
454			};
455		};
456
457		mc2_a_1_sleep: mc2_a_1_sleep {
458			sleep_cfg1 {
459				pins = "GPIO128_A5"; /* CLK */
460				ste,config = <&out_lo_wkup_pdis>;
461			};
462			sleep_cfg2 {
463				pins =
464				"GPIO130_C8", /* FBCLK */
465				"GPIO129_B4"; /* CMD */
466				ste,config = <&in_wkup_pdis_en>;
467			};
468			sleep_cfg3 {
469				pins =
470				"GPIO131_A12", /* DAT0 */
471				"GPIO132_C10", /* DAT1 */
472				"GPIO133_B10", /* DAT2 */
473				"GPIO134_B9", /* DAT3 */
474				"GPIO135_A9", /* DAT4 */
475				"GPIO136_C7", /* DAT5 */
476				"GPIO137_A7", /* DAT6 */
477				"GPIO138_C5"; /* DAT7 */
478				ste,config = <&in_wkup_pdis>;
479			};
480		};
481	};
482
483	sdi4 {
484		/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
485		mc4_a_1_default: mc4_a_1_default {
486			default_mux {
487				function = "mc4";
488				groups = "mc4_a_1";
489			};
490			default_cfg1 {
491				pins = "GPIO203_AE23"; /* CLK */
492				ste,config = <&out_lo>;
493			};
494			default_cfg2 {
495				pins = "GPIO202_AF25"; /* FBCLK */
496				ste,config = <&in_nopull>;
497			};
498			default_cfg3 {
499				pins =
500				"GPIO201_AF24", /* CMD */
501				"GPIO200_AH26", /* DAT0 */
502				"GPIO199_AH23", /* DAT1 */
503				"GPIO198_AG25", /* DAT2 */
504				"GPIO197_AH24", /* DAT3 */
505				"GPIO207_AJ23", /* DAT4 */
506				"GPIO206_AG24", /* DAT5 */
507				"GPIO205_AG23", /* DAT6 */
508				"GPIO204_AF23"; /* DAT7 */
509				ste,config = <&in_pu>;
510			};
511		};
512
513		mc4_a_1_sleep: mc4_a_1_sleep {
514			sleep_cfg1 {
515				pins = "GPIO203_AE23"; /* CLK */
516				ste,config = <&out_lo_wkup_pdis>;
517			};
518			sleep_cfg2 {
519				pins =
520				"GPIO202_AF25", /* FBCLK */
521				"GPIO201_AF24", /* CMD */
522				"GPIO200_AH26", /* DAT0 */
523				"GPIO199_AH23", /* DAT1 */
524				"GPIO198_AG25", /* DAT2 */
525				"GPIO197_AH24", /* DAT3 */
526				"GPIO207_AJ23", /* DAT4 */
527				"GPIO206_AG24", /* DAT5 */
528				"GPIO205_AG23", /* DAT6 */
529				"GPIO204_AF23"; /* DAT7 */
530				ste,config = <&slpm_in_wkup_pdis>;
531			};
532		};
533	};
534
535	/*
536	 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
537	 * cannot be muxed onto any pins.
538	 */
539	msp0 {
540		msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default {
541			default_msp0_mux {
542				function = "msp0";
543				groups = "msp0txrx_a_1", "msp0tfstck_a_1";
544			};
545			default_msp0_cfg {
546				pins =
547				"GPIO12_AC4", /* TXD */
548				"GPIO15_AC3", /* RXD */
549				"GPIO13_AF3", /* TFS */
550				"GPIO14_AE3"; /* TCK */
551				ste,config = <&in_nopull>;
552			};
553		};
554	};
555
556	msp1 {
557		msp1txrx_a_1_default: msp1txrx_a_1_default {
558			default_mux {
559				function = "msp1";
560				groups = "msp1txrx_a_1", "msp1_a_1";
561			};
562			default_cfg1 {
563				pins = "GPIO33_AF2";
564				ste,config = <&out_lo>;
565			};
566			default_cfg2 {
567				pins =
568				"GPIO34_AE1",
569				"GPIO35_AE2",
570				"GPIO36_AG2";
571				ste,config = <&in_nopull>;
572			};
573		};
574	};
575
576	msp2 {
577		msp2_a_1_default: msp2_a_1_default {
578			/* MSP2 usually used for HDMI audio */
579			default_mux {
580				function = "msp2";
581				groups = "msp2_a_1";
582			};
583			default_cfg1 {
584				pins =
585				"GPIO193_AH27", /* TXD */
586				"GPIO194_AF27", /* TCK */
587				"GPIO195_AG28"; /* TFS */
588				ste,config = <&in_pd>;
589			};
590			default_cfg2 {
591				pins = "GPIO196_AG26"; /* RXD */
592				ste,config = <&out_lo>;
593			};
594		};
595	};
596
597	musb {
598		usb_a_1_default: usb_a_1_default {
599			default_mux {
600				function = "usb";
601				groups = "usb_a_1";
602			};
603			default_cfg1 {
604				pins =
605				"GPIO256_AF28", /* NXT */
606				"GPIO258_AD29", /* XCLK */
607				"GPIO259_AC29", /* DIR */
608				"GPIO260_AD28", /* DAT7 */
609				"GPIO261_AD26", /* DAT6 */
610				"GPIO262_AE26", /* DAT5 */
611				"GPIO263_AG29", /* DAT4 */
612				"GPIO264_AE27", /* DAT3 */
613				"GPIO265_AD27", /* DAT2 */
614				"GPIO266_AC28", /* DAT1 */
615				"GPIO267_AC27"; /* DAT0 */
616				ste,config = <&in_nopull>;
617			};
618			default_cfg2 {
619				pins = "GPIO257_AE29"; /* STP */
620				ste,config = <&out_hi>;
621			};
622		};
623
624		usb_a_1_sleep: usb_a_1_sleep {
625			sleep_cfg1 {
626				pins =
627				"GPIO256_AF28", /* NXT */
628				"GPIO258_AD29", /* XCLK */
629				"GPIO259_AC29"; /* DIR */
630				ste,config = <&slpm_wkup_pdis_en>;
631			};
632			sleep_cfg2 {
633				pins = "GPIO257_AE29"; /* STP */
634				ste,config = <&slpm_out_hi_wkup_pdis>;
635			};
636			sleep_cfg3 {
637				pins =
638				"GPIO260_AD28", /* DAT7 */
639				"GPIO261_AD26", /* DAT6 */
640				"GPIO262_AE26", /* DAT5 */
641				"GPIO263_AG29", /* DAT4 */
642				"GPIO264_AE27", /* DAT3 */
643				"GPIO265_AD27", /* DAT2 */
644				"GPIO266_AC28", /* DAT1 */
645				"GPIO267_AC27"; /* DAT0 */
646				ste,config = <&slpm_in_wkup_pdis_en>;
647			};
648		};
649	};
650};
651