1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos5422 SoC cpu device tree source 4 * 5 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. 9 * 10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration 11 * but particular boards choose different booting order. 12 * 13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 14 * booting cluster (big or LITTLE) is chosen by IROM code by reading 15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting 16 * from the LITTLE: Cortex-A7. 17 */ 18 19/ { 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@100 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a7"; 59 reg = <0x100>; 60 clocks = <&clock CLK_KFC_CLK>; 61 clock-frequency = <1000000000>; 62 cci-control-port = <&cci_control0>; 63 operating-points-v2 = <&cluster_a7_opp_table>; 64 #cooling-cells = <2>; /* min followed by max */ 65 capacity-dmips-mhz = <539>; 66 dynamic-power-coefficient = <90>; 67 }; 68 69 cpu1: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a7"; 72 reg = <0x101>; 73 clocks = <&clock CLK_KFC_CLK>; 74 clock-frequency = <1000000000>; 75 cci-control-port = <&cci_control0>; 76 operating-points-v2 = <&cluster_a7_opp_table>; 77 #cooling-cells = <2>; /* min followed by max */ 78 capacity-dmips-mhz = <539>; 79 dynamic-power-coefficient = <90>; 80 }; 81 82 cpu2: cpu@102 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x102>; 86 clocks = <&clock CLK_KFC_CLK>; 87 clock-frequency = <1000000000>; 88 cci-control-port = <&cci_control0>; 89 operating-points-v2 = <&cluster_a7_opp_table>; 90 #cooling-cells = <2>; /* min followed by max */ 91 capacity-dmips-mhz = <539>; 92 dynamic-power-coefficient = <90>; 93 }; 94 95 cpu3: cpu@103 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a7"; 98 reg = <0x103>; 99 clocks = <&clock CLK_KFC_CLK>; 100 clock-frequency = <1000000000>; 101 cci-control-port = <&cci_control0>; 102 operating-points-v2 = <&cluster_a7_opp_table>; 103 #cooling-cells = <2>; /* min followed by max */ 104 capacity-dmips-mhz = <539>; 105 dynamic-power-coefficient = <90>; 106 }; 107 108 cpu4: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a15"; 111 reg = <0x0>; 112 clocks = <&clock CLK_ARM_CLK>; 113 clock-frequency = <1800000000>; 114 cci-control-port = <&cci_control1>; 115 operating-points-v2 = <&cluster_a15_opp_table>; 116 #cooling-cells = <2>; /* min followed by max */ 117 capacity-dmips-mhz = <1024>; 118 dynamic-power-coefficient = <310>; 119 }; 120 121 cpu5: cpu@1 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a15"; 124 reg = <0x1>; 125 clocks = <&clock CLK_ARM_CLK>; 126 clock-frequency = <1800000000>; 127 cci-control-port = <&cci_control1>; 128 operating-points-v2 = <&cluster_a15_opp_table>; 129 #cooling-cells = <2>; /* min followed by max */ 130 capacity-dmips-mhz = <1024>; 131 dynamic-power-coefficient = <310>; 132 }; 133 134 cpu6: cpu@2 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a15"; 137 reg = <0x2>; 138 clocks = <&clock CLK_ARM_CLK>; 139 clock-frequency = <1800000000>; 140 cci-control-port = <&cci_control1>; 141 operating-points-v2 = <&cluster_a15_opp_table>; 142 #cooling-cells = <2>; /* min followed by max */ 143 capacity-dmips-mhz = <1024>; 144 dynamic-power-coefficient = <310>; 145 }; 146 147 cpu7: cpu@3 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a15"; 150 reg = <0x3>; 151 clocks = <&clock CLK_ARM_CLK>; 152 clock-frequency = <1800000000>; 153 cci-control-port = <&cci_control1>; 154 operating-points-v2 = <&cluster_a15_opp_table>; 155 #cooling-cells = <2>; /* min followed by max */ 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <310>; 158 }; 159 }; 160}; 161 162&arm_a7_pmu { 163 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 164 status = "okay"; 165}; 166 167&arm_a15_pmu { 168 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 169 status = "okay"; 170}; 171