1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos4212 SoC device tree source 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 9 * based board files can include this file and provide values for board specific 10 * bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional 14 * nodes can be added to this file. 15 */ 16 17#include "exynos4x12.dtsi" 18 19/ { 20 compatible = "samsung,exynos4212", "samsung,exynos4"; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 }; 35 }; 36 37 cpu0: cpu@a00 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a9"; 40 reg = <0xa00>; 41 clocks = <&clock CLK_ARM_CLK>; 42 clock-names = "cpu"; 43 operating-points-v2 = <&cpu0_opp_table>; 44 #cooling-cells = <2>; /* min followed by max */ 45 }; 46 47 cpu1: cpu@a01 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a9"; 50 reg = <0xa01>; 51 clocks = <&clock CLK_ARM_CLK>; 52 clock-names = "cpu"; 53 operating-points-v2 = <&cpu0_opp_table>; 54 #cooling-cells = <2>; /* min followed by max */ 55 }; 56 }; 57 58 cpu0_opp_table: opp-table-0 { 59 compatible = "operating-points-v2"; 60 opp-shared; 61 62 opp-200000000 { 63 opp-hz = /bits/ 64 <200000000>; 64 opp-microvolt = <900000>; 65 clock-latency-ns = <200000>; 66 }; 67 opp-300000000 { 68 opp-hz = /bits/ 64 <300000000>; 69 opp-microvolt = <900000>; 70 clock-latency-ns = <200000>; 71 }; 72 opp-400000000 { 73 opp-hz = /bits/ 64 <400000000>; 74 opp-microvolt = <925000>; 75 clock-latency-ns = <200000>; 76 }; 77 opp-500000000 { 78 opp-hz = /bits/ 64 <500000000>; 79 opp-microvolt = <950000>; 80 clock-latency-ns = <200000>; 81 }; 82 opp-600000000 { 83 opp-hz = /bits/ 64 <600000000>; 84 opp-microvolt = <975000>; 85 clock-latency-ns = <200000>; 86 }; 87 opp-700000000 { 88 opp-hz = /bits/ 64 <700000000>; 89 opp-microvolt = <987500>; 90 clock-latency-ns = <200000>; 91 }; 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <1000000>; 95 clock-latency-ns = <200000>; 96 opp-suspend; 97 }; 98 opp-900000000 { 99 opp-hz = /bits/ 64 <900000000>; 100 opp-microvolt = <1037500>; 101 clock-latency-ns = <200000>; 102 }; 103 opp-1000000000 { 104 opp-hz = /bits/ 64 <1000000000>; 105 opp-microvolt = <1087500>; 106 clock-latency-ns = <200000>; 107 }; 108 opp-1100000000 { 109 opp-hz = /bits/ 64 <1100000000>; 110 opp-microvolt = <1137500>; 111 clock-latency-ns = <200000>; 112 }; 113 opp-1200000000 { 114 opp-hz = /bits/ 64 <1200000000>; 115 opp-microvolt = <1187500>; 116 clock-latency-ns = <200000>; 117 }; 118 opp-1300000000 { 119 opp-hz = /bits/ 64 <1300000000>; 120 opp-microvolt = <1250000>; 121 clock-latency-ns = <200000>; 122 }; 123 opp-1400000000 { 124 opp-hz = /bits/ 64 <1400000000>; 125 opp-microvolt = <1287500>; 126 clock-latency-ns = <200000>; 127 }; 128 cpu0_opp_1500: opp-1500000000 { 129 opp-hz = /bits/ 64 <1500000000>; 130 opp-microvolt = <1350000>; 131 clock-latency-ns = <200000>; 132 turbo-mode; 133 }; 134 }; 135}; 136 137&clock { 138 compatible = "samsung,exynos4212-clock"; 139}; 140 141&combiner { 142 samsung,combiner-nr = <18>; 143}; 144 145&gic { 146 cpu-offset = <0x8000>; 147}; 148 149&pmu { 150 interrupts = <2 2>, <3 2>; 151 interrupt-affinity = <&cpu0>, <&cpu1>; 152 status = "okay"; 153}; 154 155&pmu_system_controller { 156 compatible = "samsung,exynos4212-pmu", "simple-mfd", "syscon"; 157}; 158