1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. 5 */ 6 7/dts-v1/; 8#include "rv1126.dtsi" 9#include "rv1126-edgeble-neu2.dtsi" 10 11/ { 12 model = "Edgeble Neu2 IO Board"; 13 compatible = "edgeble,neural-compute-module-2-io", 14 "edgeble,neural-compute-module-2", "rockchip,rv1126"; 15 16 aliases { 17 serial2 = &uart2; 18 }; 19 20 chosen { 21 stdout-path = "serial2:1500000n8"; 22 }; 23}; 24 25&gmac { 26 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 27 <&cru CLK_GMAC_ETHERNET_OUT>; 28 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 29 assigned-clock-rates = <125000000>, <0>, <25000000>; 30 clock_in_out = "input"; 31 phy-handle = <&phy>; 32 phy-mode = "rgmii"; 33 phy-supply = <&vcc_3v3>; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 36 tx_delay = <0x2a>; 37 rx_delay = <0x1a>; 38 status = "okay"; 39}; 40 41&mdio { 42 phy: ethernet-phy@0 { 43 compatible = "ethernet-phy-id001c.c916", 44 "ethernet-phy-ieee802.3-c22"; 45 reg = <0x0>; 46 pinctrl-names = "default"; 47 pinctrl-0 = <ð_phy_rst>; 48 reset-assert-us = <20000>; 49 reset-deassert-us = <100000>; 50 reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; 51 }; 52}; 53 54&pinctrl { 55 ethernet { 56 eth_phy_rst: eth-phy-rst { 57 rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 58 }; 59 }; 60}; 61 62&sdmmc { 63 bus-width = <4>; 64 cap-mmc-highspeed; 65 cap-sd-highspeed; 66 card-detect-delay = <200>; 67 pinctrl-names = "default"; 68 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; 69 rockchip,default-sample-phase = <90>; 70 sd-uhs-sdr12; 71 sd-uhs-sdr25; 72 sd-uhs-sdr104; 73 vqmmc-supply = <&vccio_sd>; 74 status = "okay"; 75}; 76 77&uart2 { 78 status = "okay"; 79}; 80