xref: /freebsd/sys/contrib/device-tree/src/arm/renesas/r9a06g032-rzn1d400-db.dts (revision f126890ac5386406dadf7c4cfa9566cbb56537c5) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZN1D-DB Board
4 *
5 * Copyright (C) 2018 Renesas Electronics Europe Limited
6 *
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
12#include <dt-bindings/net/pcs-rzn1-miic.h>
13
14#include "r9a06g032.dtsi"
15
16/ {
17	model = "RZN1D-DB Board";
18	compatible = "renesas,rzn1d400-db", "renesas,r9a06g032";
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	aliases {
25		serial0 = &uart0;
26	};
27};
28
29&can0 {
30	pinctrl-0 = <&pins_can0>;
31	pinctrl-names = "default";
32
33	/* Assuming CN10/CN11 are wired for CAN1 */
34	status = "okay";
35};
36
37&can1 {
38	pinctrl-0 = <&pins_can1>;
39	pinctrl-names = "default";
40
41	/* Please only enable can0 or can1, depending on CN10/CN11 */
42	/* status = "okay"; */
43};
44
45&eth_miic {
46	status = "okay";
47	renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
48};
49
50&gmac2 {
51	status = "okay";
52	phy-mode = "gmii";
53
54	fixed-link {
55		speed = <1000>;
56		full-duplex;
57	};
58};
59
60&mii_conv4 {
61	renesas,miic-input = <MIIC_SWITCH_PORTB>;
62	status = "okay";
63};
64
65&mii_conv5 {
66	renesas,miic-input = <MIIC_SWITCH_PORTA>;
67	status = "okay";
68};
69
70&pinctrl{
71	pins_can0: pins_can0 {
72		pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>,	/* CAN0_TXD */
73			 <RZN1_PINMUX(163, RZN1_FUNC_CAN)>;	/* CAN0_RXD */
74		drive-strength = <6>;
75	};
76
77	pins_can1: pins_can1 {
78		pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>,	/* CAN1_TXD */
79			 <RZN1_PINMUX(110, RZN1_FUNC_CAN)>;	/* CAN1_RXD */
80		drive-strength = <6>;
81	};
82
83	pins_eth3: pins_eth3 {
84		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
85			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
86			 <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
87			 <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
88			 <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
89			 <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
90			 <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
91			 <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
92			 <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
93			 <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
94			 <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
95			 <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
96		drive-strength = <6>;
97		bias-disable;
98	};
99
100	pins_eth4: pins_eth4 {
101		pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
102			 <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
103			 <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
104			 <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
105			 <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
106			 <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
107			 <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
108			 <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
109			 <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
110			 <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
111			 <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
112			 <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
113		drive-strength = <6>;
114		bias-disable;
115	};
116
117	pins_mdio1: pins_mdio1 {
118		pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
119			 <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
120	};
121};
122
123&rtc0 {
124	status = "okay";
125};
126
127&switch {
128	status = "okay";
129	#address-cells = <1>;
130	#size-cells = <0>;
131
132	pinctrl-names = "default";
133	pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;
134
135	dsa,member = <0 0>;
136
137	mdio {
138		clock-frequency = <2500000>;
139
140		#address-cells = <1>;
141		#size-cells = <0>;
142
143		switch0phy4: ethernet-phy@4 {
144			reg = <4>;
145			micrel,led-mode = <1>;
146		};
147
148		switch0phy5: ethernet-phy@5 {
149			reg = <5>;
150			micrel,led-mode = <1>;
151		};
152	};
153};
154
155&switch_port0 {
156	label = "lan0";
157	phy-mode = "mii";
158	phy-handle = <&switch0phy5>;
159	status = "okay";
160};
161
162&switch_port1 {
163	label = "lan1";
164	phy-mode = "mii";
165	phy-handle = <&switch0phy4>;
166	status = "okay";
167};
168
169&switch_port4 {
170	status = "okay";
171};
172
173&uart0 {
174	status = "okay";
175};
176
177&wdt0 {
178	timeout-sec = <60>;
179	status = "okay";
180};
181