1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the SK-RZG1E board 4 * 5 * Copyright (C) 2016-2017 Cogent Embedded, Inc. 6 */ 7 8/dts-v1/; 9#include "r8a7745.dtsi" 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 model = "SK-RZG1E"; 14 compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; 15 16 aliases { 17 serial0 = &scif2; 18 }; 19 20 chosen { 21 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@40000000 { 26 device_type = "memory"; 27 reg = <0 0x40000000 0 0x40000000>; 28 }; 29}; 30 31&extal_clk { 32 clock-frequency = <20000000>; 33}; 34 35&pfc { 36 scif2_pins: scif2 { 37 groups = "scif2_data"; 38 function = "scif2"; 39 }; 40 41 ether_pins: ether { 42 groups = "eth_link", "eth_mdio", "eth_rmii"; 43 function = "eth"; 44 }; 45 46 phy1_pins: phy1 { 47 groups = "intc_irq8"; 48 function = "intc"; 49 }; 50}; 51 52&scif2 { 53 pinctrl-0 = <&scif2_pins>; 54 pinctrl-names = "default"; 55 56 status = "okay"; 57}; 58 59ðer { 60 pinctrl-0 = <ðer_pins>, <&phy1_pins>; 61 pinctrl-names = "default"; 62 63 phy-handle = <&phy1>; 64 renesas,ether-link-active-low; 65 status = "okay"; 66 67 phy1: ethernet-phy@1 { 68 compatible = "ethernet-phy-id0022.1537", 69 "ethernet-phy-ieee802.3-c22"; 70 reg = <1>; 71 interrupt-parent = <&irqc>; 72 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 73 micrel,led-mode = <1>; 74 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; 75 }; 76}; 77