1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R7S9210 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corporation 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r7s9210-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r7s9210"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 /* External clocks */ 19 extal_clk: extal { 20 #clock-cells = <0>; 21 compatible = "fixed-clock"; 22 /* Value must be set by board */ 23 clock-frequency = <0>; 24 }; 25 26 rtc_x1_clk: rtc_x1 { 27 #clock-cells = <0>; 28 compatible = "fixed-clock"; 29 /* If clk present, value (32678) must be set by board */ 30 clock-frequency = <0>; 31 }; 32 33 usb_x1_clk: usb_x1 { 34 #clock-cells = <0>; 35 compatible = "fixed-clock"; 36 /* If clk present, value (48000000) must be set by board */ 37 clock-frequency = <0>; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a9"; 47 reg = <0>; 48 clock-frequency = <528000000>; 49 next-level-cache = <&L2>; 50 }; 51 }; 52 53 soc { 54 compatible = "simple-bus"; 55 interrupt-parent = <&gic>; 56 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 61 L2: cache-controller@1f003000 { 62 compatible = "arm,pl310-cache"; 63 reg = <0x1f003000 0x1000>; 64 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 65 arm,early-bresp-disable; 66 arm,full-line-zero-disable; 67 cache-unified; 68 cache-level = <2>; 69 }; 70 71 scif0: serial@e8007000 { 72 compatible = "renesas,scif-r7s9210"; 73 reg = <0xe8007000 0x18>; 74 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 80 interrupt-names = "eri", "rxi", "txi", 81 "bri", "dri", "tei"; 82 clocks = <&cpg CPG_MOD 47>; 83 clock-names = "fck"; 84 power-domains = <&cpg>; 85 status = "disabled"; 86 }; 87 88 scif1: serial@e8007800 { 89 compatible = "renesas,scif-r7s9210"; 90 reg = <0xe8007800 0x18>; 91 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 97 interrupt-names = "eri", "rxi", "txi", 98 "bri", "dri", "tei"; 99 clocks = <&cpg CPG_MOD 46>; 100 clock-names = "fck"; 101 power-domains = <&cpg>; 102 status = "disabled"; 103 }; 104 105 scif2: serial@e8008000 { 106 compatible = "renesas,scif-r7s9210"; 107 reg = <0xe8008000 0x18>; 108 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-names = "eri", "rxi", "txi", 115 "bri", "dri", "tei"; 116 clocks = <&cpg CPG_MOD 45>; 117 clock-names = "fck"; 118 power-domains = <&cpg>; 119 status = "disabled"; 120 }; 121 122 scif3: serial@e8008800 { 123 compatible = "renesas,scif-r7s9210"; 124 reg = <0xe8008800 0x18>; 125 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-names = "eri", "rxi", "txi", 132 "bri", "dri", "tei"; 133 clocks = <&cpg CPG_MOD 44>; 134 clock-names = "fck"; 135 power-domains = <&cpg>; 136 status = "disabled"; 137 }; 138 139 scif4: serial@e8009000 { 140 compatible = "renesas,scif-r7s9210"; 141 reg = <0xe8009000 0x18>; 142 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 148 interrupt-names = "eri", "rxi", "txi", 149 "bri", "dri", "tei"; 150 clocks = <&cpg CPG_MOD 43>; 151 clock-names = "fck"; 152 power-domains = <&cpg>; 153 status = "disabled"; 154 }; 155 156 spi0: spi@e800c800 { 157 compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; 158 reg = <0xe800c800 0x24>; 159 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 162 interrupt-names = "error", "rx", "tx"; 163 clocks = <&cpg CPG_MOD 97>; 164 power-domains = <&cpg>; 165 num-cs = <1>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 status = "disabled"; 169 }; 170 171 spi1: spi@e800d000 { 172 compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; 173 reg = <0xe800d000 0x24>; 174 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 177 interrupt-names = "error", "rx", "tx"; 178 clocks = <&cpg CPG_MOD 96>; 179 power-domains = <&cpg>; 180 num-cs = <1>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 status = "disabled"; 184 }; 185 186 spi2: spi@e800d800 { 187 compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; 188 reg = <0xe800d800 0x24>; 189 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-names = "error", "rx", "tx"; 193 clocks = <&cpg CPG_MOD 95>; 194 power-domains = <&cpg>; 195 num-cs = <1>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 status = "disabled"; 199 }; 200 201 ether0: ethernet@e8204000 { 202 compatible = "renesas,ether-r7s9210"; 203 reg = <0xe8204000 0x200>; 204 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cpg CPG_MOD 65>; 206 power-domains = <&cpg>; 207 208 phy-mode = "rmii"; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 }; 213 214 ether1: ethernet@e8204200 { 215 compatible = "renesas,ether-r7s9210"; 216 reg = <0xe8204200 0x200>; 217 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cpg CPG_MOD 64>; 219 power-domains = <&cpg>; 220 phy-mode = "rmii"; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 status = "disabled"; 224 }; 225 226 i2c0: i2c@e803a000 { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; 230 reg = <0xe803a000 0x44>; 231 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>, 233 <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 239 interrupt-names = "tei", "ri", "ti", "spi", "sti", 240 "naki", "ali", "tmoi"; 241 clocks = <&cpg CPG_MOD 87>; 242 power-domains = <&cpg>; 243 clock-frequency = <100000>; 244 status = "disabled"; 245 }; 246 247 i2c1: i2c@e803a400 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; 251 reg = <0xe803a400 0x44>; 252 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 254 <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-names = "tei", "ri", "ti", "spi", "sti", 261 "naki", "ali", "tmoi"; 262 clocks = <&cpg CPG_MOD 86>; 263 power-domains = <&cpg>; 264 clock-frequency = <100000>; 265 status = "disabled"; 266 }; 267 268 i2c2: i2c@e803a800 { 269 #address-cells = <1>; 270 #size-cells = <0>; 271 compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; 272 reg = <0xe803a800 0x44>; 273 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, 275 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 276 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 281 interrupt-names = "tei", "ri", "ti", "spi", "sti", 282 "naki", "ali", "tmoi"; 283 clocks = <&cpg CPG_MOD 85>; 284 power-domains = <&cpg>; 285 clock-frequency = <100000>; 286 status = "disabled"; 287 }; 288 289 i2c3: i2c@e803ac00 { 290 #address-cells = <1>; 291 #size-cells = <0>; 292 compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; 293 reg = <0xe803ac00 0x44>; 294 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-names = "tei", "ri", "ti", "spi", "sti", 303 "naki", "ali", "tmoi"; 304 clocks = <&cpg CPG_MOD 84>; 305 power-domains = <&cpg>; 306 clock-frequency = <100000>; 307 status = "disabled"; 308 }; 309 310 ostm0: timer@e803b000 { 311 compatible = "renesas,r7s9210-ostm", "renesas,ostm"; 312 reg = <0xe803b000 0x30>; 313 interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 314 clocks = <&cpg CPG_MOD 36>; 315 power-domains = <&cpg>; 316 status = "disabled"; 317 }; 318 319 ostm1: timer@e803c000 { 320 compatible = "renesas,r7s9210-ostm", "renesas,ostm"; 321 reg = <0xe803c000 0x30>; 322 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 323 clocks = <&cpg CPG_MOD 35>; 324 power-domains = <&cpg>; 325 status = "disabled"; 326 }; 327 328 ostm2: timer@e803d000 { 329 compatible = "renesas,r7s9210-ostm", "renesas,ostm"; 330 reg = <0xe803d000 0x30>; 331 interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>; 332 clocks = <&cpg CPG_MOD 34>; 333 power-domains = <&cpg>; 334 status = "disabled"; 335 }; 336 337 ohci0: usb@e8218000 { 338 compatible = "generic-ohci"; 339 reg = <0xe8218000 0x100>; 340 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&cpg CPG_MOD 61>; 342 phys = <&usb2_phy0>; 343 phy-names = "usb"; 344 power-domains = <&cpg>; 345 status = "disabled"; 346 }; 347 348 ehci0: usb@e8218100 { 349 compatible = "generic-ehci"; 350 reg = <0xe8218100 0x100>; 351 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&cpg CPG_MOD 61>; 353 phys = <&usb2_phy0>; 354 phy-names = "usb"; 355 power-domains = <&cpg>; 356 status = "disabled"; 357 }; 358 359 usb2_phy0: usb-phy@e8218200 { 360 compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; 361 reg = <0xe8218200 0x700>; 362 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>; 364 clock-names = "fck", "usb_x1"; 365 power-domains = <&cpg>; 366 #phy-cells = <0>; 367 status = "disabled"; 368 }; 369 370 usbhs0: usb@e8219000 { 371 compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; 372 reg = <0xe8219000 0x724>; 373 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cpg CPG_MOD 61>; 375 renesas,buswait = <7>; 376 phys = <&usb2_phy0>; 377 phy-names = "usb"; 378 power-domains = <&cpg>; 379 status = "disabled"; 380 }; 381 382 ohci1: usb@e821a000 { 383 compatible = "generic-ohci"; 384 reg = <0xe821a000 0x100>; 385 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cpg CPG_MOD 60>; 387 phys = <&usb2_phy1>; 388 phy-names = "usb"; 389 power-domains = <&cpg>; 390 status = "disabled"; 391 }; 392 393 ehci1: usb@e821a100 { 394 compatible = "generic-ehci"; 395 reg = <0xe821a100 0x100>; 396 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&cpg CPG_MOD 60>; 398 phys = <&usb2_phy1>; 399 phy-names = "usb"; 400 power-domains = <&cpg>; 401 status = "disabled"; 402 }; 403 404 usb2_phy1: usb-phy@e821a200 { 405 compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; 406 reg = <0xe821a200 0x700>; 407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>; 409 clock-names = "fck", "usb_x1"; 410 power-domains = <&cpg>; 411 #phy-cells = <0>; 412 status = "disabled"; 413 }; 414 415 usbhs1: usb@e821b000 { 416 compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; 417 reg = <0xe821b000 0x724>; 418 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cpg CPG_MOD 60>; 420 renesas,buswait = <7>; 421 phys = <&usb2_phy1>; 422 phy-names = "usb"; 423 power-domains = <&cpg>; 424 status = "disabled"; 425 }; 426 427 sdhi0: mmc@e8228000 { 428 compatible = "renesas,sdhi-r7s9210"; 429 reg = <0xe8228000 0x8c0>; 430 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; 432 clock-names = "core", "cd"; 433 power-domains = <&cpg>; 434 cap-sd-highspeed; 435 cap-sdio-irq; 436 status = "disabled"; 437 }; 438 439 sdhi1: mmc@e822a000 { 440 compatible = "renesas,sdhi-r7s9210"; 441 reg = <0xe822a000 0x8c0>; 442 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; 444 clock-names = "core", "cd"; 445 power-domains = <&cpg>; 446 cap-sd-highspeed; 447 cap-sdio-irq; 448 status = "disabled"; 449 }; 450 451 gic: interrupt-controller@e8221000 { 452 compatible = "arm,gic-400"; 453 #interrupt-cells = <3>; 454 #address-cells = <0>; 455 interrupt-controller; 456 reg = <0xe8221000 0x1000>, 457 <0xe8222000 0x1000>; 458 }; 459 460 cpg: clock-controller@fcfe0010 { 461 compatible = "renesas,r7s9210-cpg-mssr"; 462 reg = <0xfcfe0010 0x455>; 463 clocks = <&extal_clk>; 464 clock-names = "extal"; 465 #clock-cells = <2>; 466 #power-domain-cells = <0>; 467 }; 468 469 wdt: watchdog@fcfe7000 { 470 compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; 471 reg = <0xfcfe7000 0x26>; 472 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; 474 }; 475 476 bsid: chipid@fcfe8004 { 477 compatible = "renesas,bsid"; 478 reg = <0xfcfe8004 4>; 479 }; 480 481 irqc: interrupt-controller@fcfef800 { 482 compatible = "renesas,r7s9210-irqc", 483 "renesas,rza1-irqc"; 484 #interrupt-cells = <2>; 485 #address-cells = <0>; 486 interrupt-controller; 487 reg = <0xfcfef800 0x6>; 488 interrupt-map = 489 <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 490 <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 491 <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 492 <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 493 <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 494 <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 495 <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 496 <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 497 interrupt-map-mask = <7 0>; 498 }; 499 500 pinctrl: pinctrl@fcffe000 { 501 compatible = "renesas,r7s9210-pinctrl"; 502 reg = <0xfcffe000 0x1000>; 503 504 gpio-controller; 505 #gpio-cells = <2>; 506 gpio-ranges = <&pinctrl 0 0 176>; 507 }; 508 }; 509}; 510