1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interconnect/qcom,msm8974.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8974.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/reset/qcom,gcc-msm8974.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 xo_board: xo_board { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <19200000>; 22 }; 23 24 sleep_clk: sleep_clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <32768>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 interrupts = <GIC_PPI 9 0xf04>; 35 36 CPU0: cpu@0 { 37 compatible = "qcom,krait"; 38 enable-method = "qcom,kpss-acc-v2"; 39 device_type = "cpu"; 40 reg = <0>; 41 next-level-cache = <&L2>; 42 qcom,acc = <&acc0>; 43 qcom,saw = <&saw0>; 44 cpu-idle-states = <&CPU_SPC>; 45 }; 46 47 CPU1: cpu@1 { 48 compatible = "qcom,krait"; 49 enable-method = "qcom,kpss-acc-v2"; 50 device_type = "cpu"; 51 reg = <1>; 52 next-level-cache = <&L2>; 53 qcom,acc = <&acc1>; 54 qcom,saw = <&saw1>; 55 cpu-idle-states = <&CPU_SPC>; 56 }; 57 58 CPU2: cpu@2 { 59 compatible = "qcom,krait"; 60 enable-method = "qcom,kpss-acc-v2"; 61 device_type = "cpu"; 62 reg = <2>; 63 next-level-cache = <&L2>; 64 qcom,acc = <&acc2>; 65 qcom,saw = <&saw2>; 66 cpu-idle-states = <&CPU_SPC>; 67 }; 68 69 CPU3: cpu@3 { 70 compatible = "qcom,krait"; 71 enable-method = "qcom,kpss-acc-v2"; 72 device_type = "cpu"; 73 reg = <3>; 74 next-level-cache = <&L2>; 75 qcom,acc = <&acc3>; 76 qcom,saw = <&saw3>; 77 cpu-idle-states = <&CPU_SPC>; 78 }; 79 80 L2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 qcom,saw = <&saw_l2>; 85 }; 86 87 idle-states { 88 CPU_SPC: spc { 89 compatible = "qcom,idle-state-spc", 90 "arm,idle-state"; 91 entry-latency-us = <150>; 92 exit-latency-us = <200>; 93 min-residency-us = <2000>; 94 }; 95 }; 96 }; 97 98 firmware { 99 scm { 100 compatible = "qcom,scm-msm8974", "qcom,scm"; 101 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 102 clock-names = "core", "bus", "iface"; 103 }; 104 }; 105 106 memory { 107 device_type = "memory"; 108 reg = <0x0 0x0>; 109 }; 110 111 pmu { 112 compatible = "qcom,krait-pmu"; 113 interrupts = <GIC_PPI 7 0xf04>; 114 }; 115 116 rpm: remoteproc { 117 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; 118 119 master-stats { 120 compatible = "qcom,rpm-master-stats"; 121 qcom,rpm-msg-ram = <&apss_master_stats>, 122 <&mpss_master_stats>, 123 <&lpss_master_stats>, 124 <&pronto_master_stats>; 125 qcom,master-names = "APSS", 126 "MPSS", 127 "LPSS", 128 "PRONTO"; 129 }; 130 131 smd-edge { 132 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 133 qcom,ipc = <&apcs 8 0>; 134 qcom,smd-edge = <15>; 135 136 rpm_requests: rpm-requests { 137 compatible = "qcom,rpm-msm8974"; 138 qcom,smd-channels = "rpm_requests"; 139 140 rpmcc: clock-controller { 141 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 142 #clock-cells = <1>; 143 clocks = <&xo_board>; 144 clock-names = "xo"; 145 }; 146 }; 147 }; 148 }; 149 150 reserved-memory { 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges; 154 155 mpss_region: mpss@8000000 { 156 reg = <0x08000000 0x5100000>; 157 no-map; 158 }; 159 160 mba_region: mba@d100000 { 161 reg = <0x0d100000 0x100000>; 162 no-map; 163 }; 164 165 wcnss_region: wcnss@d200000 { 166 reg = <0x0d200000 0xa00000>; 167 no-map; 168 }; 169 170 adsp_region: adsp@dc00000 { 171 reg = <0x0dc00000 0x1900000>; 172 no-map; 173 }; 174 175 venus_region: memory@f500000 { 176 reg = <0x0f500000 0x500000>; 177 no-map; 178 }; 179 180 smem_region: smem@fa00000 { 181 reg = <0xfa00000 0x200000>; 182 no-map; 183 }; 184 185 tz_region: memory@fc00000 { 186 reg = <0x0fc00000 0x160000>; 187 no-map; 188 }; 189 190 rfsa_mem: memory@fd60000 { 191 reg = <0x0fd60000 0x20000>; 192 no-map; 193 }; 194 195 rmtfs@fd80000 { 196 compatible = "qcom,rmtfs-mem"; 197 reg = <0x0fd80000 0x180000>; 198 no-map; 199 200 qcom,client-id = <1>; 201 }; 202 }; 203 204 smem { 205 compatible = "qcom,smem"; 206 207 memory-region = <&smem_region>; 208 qcom,rpm-msg-ram = <&rpm_msg_ram>; 209 210 hwlocks = <&tcsr_mutex 3>; 211 }; 212 213 smp2p-adsp { 214 compatible = "qcom,smp2p"; 215 qcom,smem = <443>, <429>; 216 217 interrupt-parent = <&intc>; 218 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 219 220 qcom,ipc = <&apcs 8 10>; 221 222 qcom,local-pid = <0>; 223 qcom,remote-pid = <2>; 224 225 adsp_smp2p_out: master-kernel { 226 qcom,entry-name = "master-kernel"; 227 #qcom,smem-state-cells = <1>; 228 }; 229 230 adsp_smp2p_in: slave-kernel { 231 qcom,entry-name = "slave-kernel"; 232 233 interrupt-controller; 234 #interrupt-cells = <2>; 235 }; 236 }; 237 238 smp2p-modem { 239 compatible = "qcom,smp2p"; 240 qcom,smem = <435>, <428>; 241 242 interrupt-parent = <&intc>; 243 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 244 245 qcom,ipc = <&apcs 8 14>; 246 247 qcom,local-pid = <0>; 248 qcom,remote-pid = <1>; 249 250 modem_smp2p_out: master-kernel { 251 qcom,entry-name = "master-kernel"; 252 #qcom,smem-state-cells = <1>; 253 }; 254 255 modem_smp2p_in: slave-kernel { 256 qcom,entry-name = "slave-kernel"; 257 258 interrupt-controller; 259 #interrupt-cells = <2>; 260 }; 261 }; 262 263 smp2p-wcnss { 264 compatible = "qcom,smp2p"; 265 qcom,smem = <451>, <431>; 266 267 interrupt-parent = <&intc>; 268 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 269 270 qcom,ipc = <&apcs 8 18>; 271 272 qcom,local-pid = <0>; 273 qcom,remote-pid = <4>; 274 275 wcnss_smp2p_out: master-kernel { 276 qcom,entry-name = "master-kernel"; 277 278 #qcom,smem-state-cells = <1>; 279 }; 280 281 wcnss_smp2p_in: slave-kernel { 282 qcom,entry-name = "slave-kernel"; 283 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 }; 287 }; 288 289 smsm { 290 compatible = "qcom,smsm"; 291 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 qcom,ipc-1 = <&apcs 8 13>; 296 qcom,ipc-2 = <&apcs 8 9>; 297 qcom,ipc-3 = <&apcs 8 19>; 298 299 apps_smsm: apps@0 { 300 reg = <0>; 301 302 #qcom,smem-state-cells = <1>; 303 }; 304 305 modem_smsm: modem@1 { 306 reg = <1>; 307 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 308 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 }; 312 313 adsp_smsm: adsp@2 { 314 reg = <2>; 315 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 316 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 }; 320 321 wcnss_smsm: wcnss@7 { 322 reg = <7>; 323 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 324 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 }; 328 }; 329 330 soc: soc { 331 #address-cells = <1>; 332 #size-cells = <1>; 333 ranges; 334 compatible = "simple-bus"; 335 336 intc: interrupt-controller@f9000000 { 337 compatible = "qcom,msm-qgic2"; 338 interrupt-controller; 339 #interrupt-cells = <3>; 340 reg = <0xf9000000 0x1000>, 341 <0xf9002000 0x1000>; 342 }; 343 344 apcs: syscon@f9011000 { 345 compatible = "syscon"; 346 reg = <0xf9011000 0x1000>; 347 }; 348 349 saw_l2: power-controller@f9012000 { 350 compatible = "qcom,saw2"; 351 reg = <0xf9012000 0x1000>; 352 regulator; 353 }; 354 355 watchdog@f9017000 { 356 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt"; 357 reg = <0xf9017000 0x1000>; 358 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 359 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 360 clocks = <&sleep_clk>; 361 }; 362 363 timer@f9020000 { 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges; 367 compatible = "arm,armv7-timer-mem"; 368 reg = <0xf9020000 0x1000>; 369 clock-frequency = <19200000>; 370 371 frame@f9021000 { 372 frame-number = <0>; 373 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 375 reg = <0xf9021000 0x1000>, 376 <0xf9022000 0x1000>; 377 }; 378 379 frame@f9023000 { 380 frame-number = <1>; 381 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 382 reg = <0xf9023000 0x1000>; 383 status = "disabled"; 384 }; 385 386 frame@f9024000 { 387 frame-number = <2>; 388 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 389 reg = <0xf9024000 0x1000>; 390 status = "disabled"; 391 }; 392 393 frame@f9025000 { 394 frame-number = <3>; 395 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 396 reg = <0xf9025000 0x1000>; 397 status = "disabled"; 398 }; 399 400 frame@f9026000 { 401 frame-number = <4>; 402 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 403 reg = <0xf9026000 0x1000>; 404 status = "disabled"; 405 }; 406 407 frame@f9027000 { 408 frame-number = <5>; 409 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 410 reg = <0xf9027000 0x1000>; 411 status = "disabled"; 412 }; 413 414 frame@f9028000 { 415 frame-number = <6>; 416 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 417 reg = <0xf9028000 0x1000>; 418 status = "disabled"; 419 }; 420 }; 421 422 acc0: power-manager@f9088000 { 423 compatible = "qcom,kpss-acc-v2"; 424 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 425 }; 426 427 saw0: power-controller@f9089000 { 428 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 429 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 430 }; 431 432 acc1: power-manager@f9098000 { 433 compatible = "qcom,kpss-acc-v2"; 434 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 435 }; 436 437 saw1: power-controller@f9099000 { 438 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 439 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 440 }; 441 442 acc2: power-manager@f90a8000 { 443 compatible = "qcom,kpss-acc-v2"; 444 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 445 }; 446 447 saw2: power-controller@f90a9000 { 448 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 449 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 450 }; 451 452 acc3: power-manager@f90b8000 { 453 compatible = "qcom,kpss-acc-v2"; 454 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 455 }; 456 457 saw3: power-controller@f90b9000 { 458 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 459 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 460 }; 461 462 sdhc_1: mmc@f9824900 { 463 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 464 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 465 reg-names = "hc", "core"; 466 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "hc_irq", "pwr_irq"; 469 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 470 <&gcc GCC_SDCC1_APPS_CLK>, 471 <&xo_board>; 472 clock-names = "iface", "core", "xo"; 473 bus-width = <8>; 474 non-removable; 475 476 status = "disabled"; 477 }; 478 479 sdhc_3: mmc@f9864900 { 480 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 481 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 482 reg-names = "hc", "core"; 483 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 485 interrupt-names = "hc_irq", "pwr_irq"; 486 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 487 <&gcc GCC_SDCC3_APPS_CLK>, 488 <&xo_board>; 489 clock-names = "iface", "core", "xo"; 490 bus-width = <4>; 491 492 #address-cells = <1>; 493 #size-cells = <0>; 494 495 status = "disabled"; 496 }; 497 498 sdhc_2: mmc@f98a4900 { 499 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 500 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 501 reg-names = "hc", "core"; 502 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "hc_irq", "pwr_irq"; 505 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 506 <&gcc GCC_SDCC2_APPS_CLK>, 507 <&xo_board>; 508 clock-names = "iface", "core", "xo"; 509 bus-width = <4>; 510 511 #address-cells = <1>; 512 #size-cells = <0>; 513 514 status = "disabled"; 515 }; 516 517 blsp1_uart1: serial@f991d000 { 518 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 519 reg = <0xf991d000 0x1000>; 520 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 522 clock-names = "core", "iface"; 523 status = "disabled"; 524 }; 525 526 blsp1_uart2: serial@f991e000 { 527 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 528 reg = <0xf991e000 0x1000>; 529 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 531 clock-names = "core", "iface"; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&blsp1_uart2_default>; 534 status = "disabled"; 535 }; 536 537 blsp1_i2c1: i2c@f9923000 { 538 status = "disabled"; 539 compatible = "qcom,i2c-qup-v2.1.1"; 540 reg = <0xf9923000 0x1000>; 541 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 543 clock-names = "core", "iface"; 544 pinctrl-names = "default", "sleep"; 545 pinctrl-0 = <&blsp1_i2c1_default>; 546 pinctrl-1 = <&blsp1_i2c1_sleep>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 }; 550 551 blsp1_i2c2: i2c@f9924000 { 552 status = "disabled"; 553 compatible = "qcom,i2c-qup-v2.1.1"; 554 reg = <0xf9924000 0x1000>; 555 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 557 clock-names = "core", "iface"; 558 pinctrl-names = "default", "sleep"; 559 pinctrl-0 = <&blsp1_i2c2_default>; 560 pinctrl-1 = <&blsp1_i2c2_sleep>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 }; 564 565 blsp1_i2c3: i2c@f9925000 { 566 status = "disabled"; 567 compatible = "qcom,i2c-qup-v2.1.1"; 568 reg = <0xf9925000 0x1000>; 569 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 571 clock-names = "core", "iface"; 572 pinctrl-names = "default", "sleep"; 573 pinctrl-0 = <&blsp1_i2c3_default>; 574 pinctrl-1 = <&blsp1_i2c3_sleep>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 }; 578 579 blsp1_i2c6: i2c@f9928000 { 580 status = "disabled"; 581 compatible = "qcom,i2c-qup-v2.1.1"; 582 reg = <0xf9928000 0x1000>; 583 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 585 clock-names = "core", "iface"; 586 pinctrl-names = "default", "sleep"; 587 pinctrl-0 = <&blsp1_i2c6_default>; 588 pinctrl-1 = <&blsp1_i2c6_sleep>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 }; 592 593 blsp2_dma: dma-controller@f9944000 { 594 compatible = "qcom,bam-v1.4.0"; 595 reg = <0xf9944000 0x19000>; 596 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 598 clock-names = "bam_clk"; 599 #dma-cells = <1>; 600 qcom,ee = <0>; 601 }; 602 603 blsp2_uart1: serial@f995d000 { 604 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 605 reg = <0xf995d000 0x1000>; 606 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 608 clock-names = "core", "iface"; 609 pinctrl-names = "default", "sleep"; 610 pinctrl-0 = <&blsp2_uart1_default>; 611 pinctrl-1 = <&blsp2_uart1_sleep>; 612 status = "disabled"; 613 }; 614 615 blsp2_uart2: serial@f995e000 { 616 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 617 reg = <0xf995e000 0x1000>; 618 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 620 clock-names = "core", "iface"; 621 status = "disabled"; 622 }; 623 624 blsp2_uart4: serial@f9960000 { 625 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 626 reg = <0xf9960000 0x1000>; 627 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 629 clock-names = "core", "iface"; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&blsp2_uart4_default>; 632 status = "disabled"; 633 }; 634 635 blsp2_i2c2: i2c@f9964000 { 636 status = "disabled"; 637 compatible = "qcom,i2c-qup-v2.1.1"; 638 reg = <0xf9964000 0x1000>; 639 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 641 clock-names = "core", "iface"; 642 pinctrl-names = "default", "sleep"; 643 pinctrl-0 = <&blsp2_i2c2_default>; 644 pinctrl-1 = <&blsp2_i2c2_sleep>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 }; 648 649 blsp2_i2c5: i2c@f9967000 { 650 status = "disabled"; 651 compatible = "qcom,i2c-qup-v2.1.1"; 652 reg = <0xf9967000 0x1000>; 653 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 655 clock-names = "core", "iface"; 656 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 657 dma-names = "tx", "rx"; 658 pinctrl-names = "default", "sleep"; 659 pinctrl-0 = <&blsp2_i2c5_default>; 660 pinctrl-1 = <&blsp2_i2c5_sleep>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 }; 664 665 blsp2_i2c6: i2c@f9968000 { 666 status = "disabled"; 667 compatible = "qcom,i2c-qup-v2.1.1"; 668 reg = <0xf9968000 0x1000>; 669 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 671 clock-names = "core", "iface"; 672 pinctrl-names = "default", "sleep"; 673 pinctrl-0 = <&blsp2_i2c6_default>; 674 pinctrl-1 = <&blsp2_i2c6_sleep>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 }; 678 679 usb: usb@f9a55000 { 680 compatible = "qcom,ci-hdrc"; 681 reg = <0xf9a55000 0x200>, 682 <0xf9a55200 0x200>; 683 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 685 <&gcc GCC_USB_HS_SYSTEM_CLK>; 686 clock-names = "iface", "core"; 687 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 688 assigned-clock-rates = <75000000>; 689 resets = <&gcc GCC_USB_HS_BCR>; 690 reset-names = "core"; 691 phy_type = "ulpi"; 692 dr_mode = "otg"; 693 ahb-burst-config = <0>; 694 phy-names = "usb-phy"; 695 status = "disabled"; 696 #reset-cells = <1>; 697 698 ulpi { 699 usb_hs1_phy: phy-0 { 700 compatible = "qcom,usb-hs-phy-msm8974", 701 "qcom,usb-hs-phy"; 702 #phy-cells = <0>; 703 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 704 clock-names = "ref", "sleep"; 705 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 706 reset-names = "phy", "por"; 707 status = "disabled"; 708 }; 709 710 usb_hs2_phy: phy-1 { 711 compatible = "qcom,usb-hs-phy-msm8974", 712 "qcom,usb-hs-phy"; 713 #phy-cells = <0>; 714 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 715 clock-names = "ref", "sleep"; 716 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; 717 reset-names = "phy", "por"; 718 status = "disabled"; 719 }; 720 }; 721 }; 722 723 rng@f9bff000 { 724 compatible = "qcom,prng"; 725 reg = <0xf9bff000 0x200>; 726 clocks = <&gcc GCC_PRNG_AHB_CLK>; 727 clock-names = "core"; 728 }; 729 730 pronto: remoteproc@fb204000 { 731 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 732 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 733 reg-names = "ccu", "dxe", "pmu"; 734 735 memory-region = <&wcnss_region>; 736 737 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 738 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 739 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 740 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 741 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 742 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 743 744 qcom,smem-states = <&wcnss_smp2p_out 0>; 745 qcom,smem-state-names = "stop"; 746 747 status = "disabled"; 748 749 iris { 750 compatible = "qcom,wcn3680"; 751 752 clocks = <&rpmcc RPM_SMD_CXO_A2>; 753 clock-names = "xo"; 754 }; 755 756 smd-edge { 757 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 758 759 qcom,ipc = <&apcs 8 17>; 760 qcom,smd-edge = <6>; 761 762 wcnss { 763 compatible = "qcom,wcnss"; 764 qcom,smd-channels = "WCNSS_CTRL"; 765 status = "disabled"; 766 767 qcom,mmio = <&pronto>; 768 769 bluetooth { 770 compatible = "qcom,wcnss-bt"; 771 }; 772 773 wifi { 774 compatible = "qcom,wcnss-wlan"; 775 776 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 777 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 778 interrupt-names = "tx", "rx"; 779 780 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 781 qcom,smem-state-names = "tx-enable", 782 "tx-rings-empty"; 783 }; 784 }; 785 }; 786 }; 787 788 sram@fc190000 { 789 compatible = "qcom,msm8974-rpm-stats"; 790 reg = <0xfc190000 0x10000>; 791 }; 792 793 etf@fc307000 { 794 compatible = "arm,coresight-tmc", "arm,primecell"; 795 reg = <0xfc307000 0x1000>; 796 797 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 798 clock-names = "apb_pclk", "atclk"; 799 800 out-ports { 801 port { 802 etf_out: endpoint { 803 remote-endpoint = <&replicator_in>; 804 }; 805 }; 806 }; 807 808 in-ports { 809 port { 810 etf_in: endpoint { 811 remote-endpoint = <&merger_out>; 812 }; 813 }; 814 }; 815 }; 816 817 tpiu@fc318000 { 818 compatible = "arm,coresight-tpiu", "arm,primecell"; 819 reg = <0xfc318000 0x1000>; 820 821 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 822 clock-names = "apb_pclk", "atclk"; 823 824 in-ports { 825 port { 826 tpiu_in: endpoint { 827 remote-endpoint = <&replicator_out1>; 828 }; 829 }; 830 }; 831 }; 832 833 funnel@fc31a000 { 834 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 835 reg = <0xfc31a000 0x1000>; 836 837 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 838 clock-names = "apb_pclk", "atclk"; 839 840 in-ports { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 844 /* 845 * Not described input ports: 846 * 0 - not-connected 847 * 1 - connected trought funnel to Multimedia CPU 848 * 2 - connected to Wireless CPU 849 * 3 - not-connected 850 * 4 - not-connected 851 * 6 - not-connected 852 * 7 - connected to STM 853 */ 854 port@5 { 855 reg = <5>; 856 funnel1_in5: endpoint { 857 remote-endpoint = <&kpss_out>; 858 }; 859 }; 860 }; 861 862 out-ports { 863 port { 864 funnel1_out: endpoint { 865 remote-endpoint = <&merger_in1>; 866 }; 867 }; 868 }; 869 }; 870 871 funnel@fc31b000 { 872 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 873 reg = <0xfc31b000 0x1000>; 874 875 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 876 clock-names = "apb_pclk", "atclk"; 877 878 in-ports { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 /* 883 * Not described input ports: 884 * 0 - connected trought funnel to Audio, Modem and 885 * Resource and Power Manager CPU's 886 * 2...7 - not-connected 887 */ 888 port@1 { 889 reg = <1>; 890 merger_in1: endpoint { 891 remote-endpoint = <&funnel1_out>; 892 }; 893 }; 894 }; 895 896 out-ports { 897 port { 898 merger_out: endpoint { 899 remote-endpoint = <&etf_in>; 900 }; 901 }; 902 }; 903 }; 904 905 replicator@fc31c000 { 906 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 907 reg = <0xfc31c000 0x1000>; 908 909 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 910 clock-names = "apb_pclk", "atclk"; 911 912 out-ports { 913 #address-cells = <1>; 914 #size-cells = <0>; 915 916 port@0 { 917 reg = <0>; 918 replicator_out0: endpoint { 919 remote-endpoint = <&etr_in>; 920 }; 921 }; 922 port@1 { 923 reg = <1>; 924 replicator_out1: endpoint { 925 remote-endpoint = <&tpiu_in>; 926 }; 927 }; 928 }; 929 930 in-ports { 931 port { 932 replicator_in: endpoint { 933 remote-endpoint = <&etf_out>; 934 }; 935 }; 936 }; 937 }; 938 939 etr@fc322000 { 940 compatible = "arm,coresight-tmc", "arm,primecell"; 941 reg = <0xfc322000 0x1000>; 942 943 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 944 clock-names = "apb_pclk", "atclk"; 945 946 in-ports { 947 port { 948 etr_in: endpoint { 949 remote-endpoint = <&replicator_out0>; 950 }; 951 }; 952 }; 953 }; 954 955 etm@fc33c000 { 956 compatible = "arm,coresight-etm4x", "arm,primecell"; 957 reg = <0xfc33c000 0x1000>; 958 959 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 960 clock-names = "apb_pclk", "atclk"; 961 962 cpu = <&CPU0>; 963 964 out-ports { 965 port { 966 etm0_out: endpoint { 967 remote-endpoint = <&kpss_in0>; 968 }; 969 }; 970 }; 971 }; 972 973 etm@fc33d000 { 974 compatible = "arm,coresight-etm4x", "arm,primecell"; 975 reg = <0xfc33d000 0x1000>; 976 977 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 978 clock-names = "apb_pclk", "atclk"; 979 980 cpu = <&CPU1>; 981 982 out-ports { 983 port { 984 etm1_out: endpoint { 985 remote-endpoint = <&kpss_in1>; 986 }; 987 }; 988 }; 989 }; 990 991 etm@fc33e000 { 992 compatible = "arm,coresight-etm4x", "arm,primecell"; 993 reg = <0xfc33e000 0x1000>; 994 995 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 996 clock-names = "apb_pclk", "atclk"; 997 998 cpu = <&CPU2>; 999 1000 out-ports { 1001 port { 1002 etm2_out: endpoint { 1003 remote-endpoint = <&kpss_in2>; 1004 }; 1005 }; 1006 }; 1007 }; 1008 1009 etm@fc33f000 { 1010 compatible = "arm,coresight-etm4x", "arm,primecell"; 1011 reg = <0xfc33f000 0x1000>; 1012 1013 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1014 clock-names = "apb_pclk", "atclk"; 1015 1016 cpu = <&CPU3>; 1017 1018 out-ports { 1019 port { 1020 etm3_out: endpoint { 1021 remote-endpoint = <&kpss_in3>; 1022 }; 1023 }; 1024 }; 1025 }; 1026 1027 /* KPSS funnel, only 4 inputs are used */ 1028 funnel@fc345000 { 1029 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1030 reg = <0xfc345000 0x1000>; 1031 1032 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1033 clock-names = "apb_pclk", "atclk"; 1034 1035 in-ports { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 1039 port@0 { 1040 reg = <0>; 1041 kpss_in0: endpoint { 1042 remote-endpoint = <&etm0_out>; 1043 }; 1044 }; 1045 port@1 { 1046 reg = <1>; 1047 kpss_in1: endpoint { 1048 remote-endpoint = <&etm1_out>; 1049 }; 1050 }; 1051 port@2 { 1052 reg = <2>; 1053 kpss_in2: endpoint { 1054 remote-endpoint = <&etm2_out>; 1055 }; 1056 }; 1057 port@3 { 1058 reg = <3>; 1059 kpss_in3: endpoint { 1060 remote-endpoint = <&etm3_out>; 1061 }; 1062 }; 1063 }; 1064 1065 out-ports { 1066 port { 1067 kpss_out: endpoint { 1068 remote-endpoint = <&funnel1_in5>; 1069 }; 1070 }; 1071 }; 1072 }; 1073 1074 bimc: interconnect@fc380000 { 1075 reg = <0xfc380000 0x6a000>; 1076 compatible = "qcom,msm8974-bimc"; 1077 #interconnect-cells = <1>; 1078 clock-names = "bus", "bus_a"; 1079 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1080 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1081 }; 1082 1083 gcc: clock-controller@fc400000 { 1084 compatible = "qcom,gcc-msm8974"; 1085 #clock-cells = <1>; 1086 #reset-cells = <1>; 1087 #power-domain-cells = <1>; 1088 reg = <0xfc400000 0x4000>; 1089 1090 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1091 <&sleep_clk>; 1092 clock-names = "xo", 1093 "sleep_clk"; 1094 }; 1095 1096 rpm_msg_ram: sram@fc428000 { 1097 compatible = "qcom,rpm-msg-ram"; 1098 reg = <0xfc428000 0x4000>; 1099 1100 #address-cells = <1>; 1101 #size-cells = <1>; 1102 ranges = <0 0xfc428000 0x4000>; 1103 1104 apss_master_stats: sram@150 { 1105 reg = <0x150 0x14>; 1106 }; 1107 1108 mpss_master_stats: sram@b50 { 1109 reg = <0xb50 0x14>; 1110 }; 1111 1112 lpss_master_stats: sram@1550 { 1113 reg = <0x1550 0x14>; 1114 }; 1115 1116 pronto_master_stats: sram@1f50 { 1117 reg = <0x1f50 0x14>; 1118 }; 1119 }; 1120 1121 snoc: interconnect@fc460000 { 1122 reg = <0xfc460000 0x4000>; 1123 compatible = "qcom,msm8974-snoc"; 1124 #interconnect-cells = <1>; 1125 clock-names = "bus", "bus_a"; 1126 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1127 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1128 }; 1129 1130 pnoc: interconnect@fc468000 { 1131 reg = <0xfc468000 0x4000>; 1132 compatible = "qcom,msm8974-pnoc"; 1133 #interconnect-cells = <1>; 1134 clock-names = "bus", "bus_a"; 1135 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1136 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1137 }; 1138 1139 ocmemnoc: interconnect@fc470000 { 1140 reg = <0xfc470000 0x4000>; 1141 compatible = "qcom,msm8974-ocmemnoc"; 1142 #interconnect-cells = <1>; 1143 clock-names = "bus", "bus_a"; 1144 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1145 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1146 }; 1147 1148 mmssnoc: interconnect@fc478000 { 1149 reg = <0xfc478000 0x4000>; 1150 compatible = "qcom,msm8974-mmssnoc"; 1151 #interconnect-cells = <1>; 1152 clock-names = "bus", "bus_a"; 1153 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1154 <&mmcc MMSS_S0_AXI_CLK>; 1155 }; 1156 1157 cnoc: interconnect@fc480000 { 1158 reg = <0xfc480000 0x4000>; 1159 compatible = "qcom,msm8974-cnoc"; 1160 #interconnect-cells = <1>; 1161 clock-names = "bus", "bus_a"; 1162 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1163 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1164 }; 1165 1166 tsens: thermal-sensor@fc4a9000 { 1167 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 1168 reg = <0xfc4a9000 0x1000>, /* TM */ 1169 <0xfc4a8000 0x1000>; /* SROT */ 1170 nvmem-cells = <&tsens_mode>, 1171 <&tsens_base1>, <&tsens_base2>, 1172 <&tsens_use_backup>, 1173 <&tsens_mode_backup>, 1174 <&tsens_base1_backup>, <&tsens_base2_backup>, 1175 <&tsens_s0_p1>, <&tsens_s0_p2>, 1176 <&tsens_s1_p1>, <&tsens_s1_p2>, 1177 <&tsens_s2_p1>, <&tsens_s2_p2>, 1178 <&tsens_s3_p1>, <&tsens_s3_p2>, 1179 <&tsens_s4_p1>, <&tsens_s4_p2>, 1180 <&tsens_s5_p1>, <&tsens_s5_p2>, 1181 <&tsens_s6_p1>, <&tsens_s6_p2>, 1182 <&tsens_s7_p1>, <&tsens_s7_p2>, 1183 <&tsens_s8_p1>, <&tsens_s8_p2>, 1184 <&tsens_s9_p1>, <&tsens_s9_p2>, 1185 <&tsens_s10_p1>, <&tsens_s10_p2>, 1186 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 1187 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 1188 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 1189 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 1190 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 1191 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 1192 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 1193 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 1194 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 1195 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 1196 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 1197 nvmem-cell-names = "mode", 1198 "base1", "base2", 1199 "use_backup", 1200 "mode_backup", 1201 "base1_backup", "base2_backup", 1202 "s0_p1", "s0_p2", 1203 "s1_p1", "s1_p2", 1204 "s2_p1", "s2_p2", 1205 "s3_p1", "s3_p2", 1206 "s4_p1", "s4_p2", 1207 "s5_p1", "s5_p2", 1208 "s6_p1", "s6_p2", 1209 "s7_p1", "s7_p2", 1210 "s8_p1", "s8_p2", 1211 "s9_p1", "s9_p2", 1212 "s10_p1", "s10_p2", 1213 "s0_p1_backup", "s0_p2_backup", 1214 "s1_p1_backup", "s1_p2_backup", 1215 "s2_p1_backup", "s2_p2_backup", 1216 "s3_p1_backup", "s3_p2_backup", 1217 "s4_p1_backup", "s4_p2_backup", 1218 "s5_p1_backup", "s5_p2_backup", 1219 "s6_p1_backup", "s6_p2_backup", 1220 "s7_p1_backup", "s7_p2_backup", 1221 "s8_p1_backup", "s8_p2_backup", 1222 "s9_p1_backup", "s9_p2_backup", 1223 "s10_p1_backup", "s10_p2_backup"; 1224 #qcom,sensors = <11>; 1225 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1226 interrupt-names = "uplow"; 1227 #thermal-sensor-cells = <1>; 1228 }; 1229 1230 restart@fc4ab000 { 1231 compatible = "qcom,pshold"; 1232 reg = <0xfc4ab000 0x4>; 1233 }; 1234 1235 qfprom: qfprom@fc4bc000 { 1236 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1237 reg = <0xfc4bc000 0x1000>; 1238 #address-cells = <1>; 1239 #size-cells = <1>; 1240 1241 tsens_base1: base1@d0 { 1242 reg = <0xd0 0x1>; 1243 bits = <0 8>; 1244 }; 1245 1246 tsens_s0_p1: s0-p1@d1 { 1247 reg = <0xd1 0x1>; 1248 bits = <0 6>; 1249 }; 1250 1251 tsens_s1_p1: s1-p1@d2 { 1252 reg = <0xd1 0x2>; 1253 bits = <6 6>; 1254 }; 1255 1256 tsens_s2_p1: s2-p1@d2 { 1257 reg = <0xd2 0x2>; 1258 bits = <4 6>; 1259 }; 1260 1261 tsens_s3_p1: s3-p1@d3 { 1262 reg = <0xd3 0x1>; 1263 bits = <2 6>; 1264 }; 1265 1266 tsens_s4_p1: s4-p1@d4 { 1267 reg = <0xd4 0x1>; 1268 bits = <0 6>; 1269 }; 1270 1271 tsens_s5_p1: s5-p1@d4 { 1272 reg = <0xd4 0x2>; 1273 bits = <6 6>; 1274 }; 1275 1276 tsens_s6_p1: s6-p1@d5 { 1277 reg = <0xd5 0x2>; 1278 bits = <4 6>; 1279 }; 1280 1281 tsens_s7_p1: s7-p1@d6 { 1282 reg = <0xd6 0x1>; 1283 bits = <2 6>; 1284 }; 1285 1286 tsens_s8_p1: s8-p1@d7 { 1287 reg = <0xd7 0x1>; 1288 bits = <0 6>; 1289 }; 1290 1291 tsens_mode: mode@d7 { 1292 reg = <0xd7 0x1>; 1293 bits = <6 2>; 1294 }; 1295 1296 tsens_s9_p1: s9-p1@d8 { 1297 reg = <0xd8 0x1>; 1298 bits = <0 6>; 1299 }; 1300 1301 tsens_s10_p1: s10_p1@d8 { 1302 reg = <0xd8 0x2>; 1303 bits = <6 6>; 1304 }; 1305 1306 tsens_base2: base2@d9 { 1307 reg = <0xd9 0x2>; 1308 bits = <4 8>; 1309 }; 1310 1311 tsens_s0_p2: s0-p2@da { 1312 reg = <0xda 0x2>; 1313 bits = <4 6>; 1314 }; 1315 1316 tsens_s1_p2: s1-p2@db { 1317 reg = <0xdb 0x1>; 1318 bits = <2 6>; 1319 }; 1320 1321 tsens_s2_p2: s2-p2@dc { 1322 reg = <0xdc 0x1>; 1323 bits = <0 6>; 1324 }; 1325 1326 tsens_s3_p2: s3-p2@dc { 1327 reg = <0xdc 0x2>; 1328 bits = <6 6>; 1329 }; 1330 1331 tsens_s4_p2: s4-p2@dd { 1332 reg = <0xdd 0x2>; 1333 bits = <4 6>; 1334 }; 1335 1336 tsens_s5_p2: s5-p2@de { 1337 reg = <0xde 0x2>; 1338 bits = <2 6>; 1339 }; 1340 1341 tsens_s6_p2: s6-p2@df { 1342 reg = <0xdf 0x1>; 1343 bits = <0 6>; 1344 }; 1345 1346 tsens_s7_p2: s7-p2@e0 { 1347 reg = <0xe0 0x1>; 1348 bits = <0 6>; 1349 }; 1350 1351 tsens_s8_p2: s8-p2@e0 { 1352 reg = <0xe0 0x2>; 1353 bits = <6 6>; 1354 }; 1355 1356 tsens_s9_p2: s9-p2@e1 { 1357 reg = <0xe1 0x2>; 1358 bits = <4 6>; 1359 }; 1360 1361 tsens_s10_p2: s10_p2@e2 { 1362 reg = <0xe2 0x2>; 1363 bits = <2 6>; 1364 }; 1365 1366 tsens_s5_p2_backup: s5-p2_backup@e3 { 1367 reg = <0xe3 0x2>; 1368 bits = <0 6>; 1369 }; 1370 1371 tsens_mode_backup: mode_backup@e3 { 1372 reg = <0xe3 0x1>; 1373 bits = <6 2>; 1374 }; 1375 1376 tsens_s6_p2_backup: s6-p2_backup@e4 { 1377 reg = <0xe4 0x1>; 1378 bits = <0 6>; 1379 }; 1380 1381 tsens_s7_p2_backup: s7-p2_backup@e4 { 1382 reg = <0xe4 0x2>; 1383 bits = <6 6>; 1384 }; 1385 1386 tsens_s8_p2_backup: s8-p2_backup@e5 { 1387 reg = <0xe5 0x2>; 1388 bits = <4 6>; 1389 }; 1390 1391 tsens_s9_p2_backup: s9-p2_backup@e6 { 1392 reg = <0xe6 0x2>; 1393 bits = <2 6>; 1394 }; 1395 1396 tsens_s10_p2_backup: s10_p2_backup@e7 { 1397 reg = <0xe7 0x1>; 1398 bits = <0 6>; 1399 }; 1400 1401 tsens_base1_backup: base1_backup@440 { 1402 reg = <0x440 0x1>; 1403 bits = <0 8>; 1404 }; 1405 1406 tsens_s0_p1_backup: s0-p1_backup@441 { 1407 reg = <0x441 0x1>; 1408 bits = <0 6>; 1409 }; 1410 1411 tsens_s1_p1_backup: s1-p1_backup@442 { 1412 reg = <0x441 0x2>; 1413 bits = <6 6>; 1414 }; 1415 1416 tsens_s2_p1_backup: s2-p1_backup@442 { 1417 reg = <0x442 0x2>; 1418 bits = <4 6>; 1419 }; 1420 1421 tsens_s3_p1_backup: s3-p1_backup@443 { 1422 reg = <0x443 0x1>; 1423 bits = <2 6>; 1424 }; 1425 1426 tsens_s4_p1_backup: s4-p1_backup@444 { 1427 reg = <0x444 0x1>; 1428 bits = <0 6>; 1429 }; 1430 1431 tsens_s5_p1_backup: s5-p1_backup@444 { 1432 reg = <0x444 0x2>; 1433 bits = <6 6>; 1434 }; 1435 1436 tsens_s6_p1_backup: s6-p1_backup@445 { 1437 reg = <0x445 0x2>; 1438 bits = <4 6>; 1439 }; 1440 1441 tsens_s7_p1_backup: s7-p1_backup@446 { 1442 reg = <0x446 0x1>; 1443 bits = <2 6>; 1444 }; 1445 1446 tsens_use_backup: use_backup@447 { 1447 reg = <0x447 0x1>; 1448 bits = <5 3>; 1449 }; 1450 1451 tsens_s8_p1_backup: s8-p1_backup@448 { 1452 reg = <0x448 0x1>; 1453 bits = <0 6>; 1454 }; 1455 1456 tsens_s9_p1_backup: s9-p1_backup@448 { 1457 reg = <0x448 0x2>; 1458 bits = <6 6>; 1459 }; 1460 1461 tsens_s10_p1_backup: s10_p1_backup@449 { 1462 reg = <0x449 0x2>; 1463 bits = <4 6>; 1464 }; 1465 1466 tsens_base2_backup: base2_backup@44a { 1467 reg = <0x44a 0x2>; 1468 bits = <2 8>; 1469 }; 1470 1471 tsens_s0_p2_backup: s0-p2_backup@44b { 1472 reg = <0x44b 0x3>; 1473 bits = <2 6>; 1474 }; 1475 1476 tsens_s1_p2_backup: s1-p2_backup@44c { 1477 reg = <0x44c 0x1>; 1478 bits = <0 6>; 1479 }; 1480 1481 tsens_s2_p2_backup: s2-p2_backup@44c { 1482 reg = <0x44c 0x2>; 1483 bits = <6 6>; 1484 }; 1485 1486 tsens_s3_p2_backup: s3-p2_backup@44d { 1487 reg = <0x44d 0x2>; 1488 bits = <4 6>; 1489 }; 1490 1491 tsens_s4_p2_backup: s4-p2_backup@44e { 1492 reg = <0x44e 0x1>; 1493 bits = <2 6>; 1494 }; 1495 }; 1496 1497 spmi_bus: spmi@fc4cf000 { 1498 compatible = "qcom,spmi-pmic-arb"; 1499 reg-names = "core", "intr", "cnfg"; 1500 reg = <0xfc4cf000 0x1000>, 1501 <0xfc4cb000 0x1000>, 1502 <0xfc4ca000 0x1000>; 1503 interrupt-names = "periph_irq"; 1504 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1505 qcom,ee = <0>; 1506 qcom,channel = <0>; 1507 #address-cells = <2>; 1508 #size-cells = <0>; 1509 interrupt-controller; 1510 #interrupt-cells = <4>; 1511 }; 1512 1513 bam_dmux_dma: dma-controller@fc834000 { 1514 compatible = "qcom,bam-v1.4.0"; 1515 reg = <0xfc834000 0x7000>; 1516 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1517 #dma-cells = <1>; 1518 qcom,ee = <0>; 1519 1520 num-channels = <6>; 1521 qcom,num-ees = <1>; 1522 qcom,powered-remotely; 1523 }; 1524 1525 remoteproc_mss: remoteproc@fc880000 { 1526 compatible = "qcom,msm8974-mss-pil"; 1527 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1528 reg-names = "qdsp6", "rmb"; 1529 1530 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1531 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1532 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1533 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1534 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1535 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1536 1537 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1538 <&gcc GCC_MSS_CFG_AHB_CLK>, 1539 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1540 <&xo_board>; 1541 clock-names = "iface", "bus", "mem", "xo"; 1542 1543 resets = <&gcc GCC_MSS_RESTART>; 1544 reset-names = "mss_restart"; 1545 1546 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; 1547 1548 qcom,smem-states = <&modem_smp2p_out 0>; 1549 qcom,smem-state-names = "stop"; 1550 1551 status = "disabled"; 1552 1553 mba { 1554 memory-region = <&mba_region>; 1555 }; 1556 1557 mpss { 1558 memory-region = <&mpss_region>; 1559 }; 1560 1561 bam_dmux: bam-dmux { 1562 compatible = "qcom,bam-dmux"; 1563 1564 interrupt-parent = <&modem_smsm>; 1565 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1566 interrupt-names = "pc", "pc-ack"; 1567 1568 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1569 qcom,smem-state-names = "pc", "pc-ack"; 1570 1571 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1572 dma-names = "tx", "rx"; 1573 }; 1574 1575 smd-edge { 1576 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1577 1578 qcom,ipc = <&apcs 8 12>; 1579 qcom,smd-edge = <0>; 1580 1581 label = "modem"; 1582 }; 1583 }; 1584 1585 tcsr_mutex: hwlock@fd484000 { 1586 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; 1587 reg = <0xfd484000 0x2000>; 1588 #hwlock-cells = <1>; 1589 }; 1590 1591 tcsr: syscon@fd4a0000 { 1592 compatible = "qcom,tcsr-msm8974", "syscon"; 1593 reg = <0xfd4a0000 0x10000>; 1594 }; 1595 1596 tlmm: pinctrl@fd510000 { 1597 compatible = "qcom,msm8974-pinctrl"; 1598 reg = <0xfd510000 0x4000>; 1599 gpio-controller; 1600 gpio-ranges = <&tlmm 0 0 146>; 1601 #gpio-cells = <2>; 1602 interrupt-controller; 1603 #interrupt-cells = <2>; 1604 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1605 1606 sdc1_off: sdc1-off-state { 1607 clk-pins { 1608 pins = "sdc1_clk"; 1609 bias-disable; 1610 drive-strength = <2>; 1611 }; 1612 1613 cmd-pins { 1614 pins = "sdc1_cmd"; 1615 bias-pull-up; 1616 drive-strength = <2>; 1617 }; 1618 1619 data-pins { 1620 pins = "sdc1_data"; 1621 bias-pull-up; 1622 drive-strength = <2>; 1623 }; 1624 }; 1625 1626 sdc2_off: sdc2-off-state { 1627 clk-pins { 1628 pins = "sdc2_clk"; 1629 bias-disable; 1630 drive-strength = <2>; 1631 }; 1632 1633 cmd-pins { 1634 pins = "sdc2_cmd"; 1635 bias-pull-up; 1636 drive-strength = <2>; 1637 }; 1638 1639 data-pins { 1640 pins = "sdc2_data"; 1641 bias-pull-up; 1642 drive-strength = <2>; 1643 }; 1644 }; 1645 1646 blsp1_uart2_default: blsp1-uart2-default-state { 1647 rx-pins { 1648 pins = "gpio5"; 1649 function = "blsp_uart2"; 1650 drive-strength = <2>; 1651 bias-pull-up; 1652 }; 1653 1654 tx-pins { 1655 pins = "gpio4"; 1656 function = "blsp_uart2"; 1657 drive-strength = <4>; 1658 bias-disable; 1659 }; 1660 }; 1661 1662 blsp2_uart1_default: blsp2-uart1-default-state { 1663 tx-rts-pins { 1664 pins = "gpio41", "gpio44"; 1665 function = "blsp_uart7"; 1666 drive-strength = <2>; 1667 bias-disable; 1668 }; 1669 1670 rx-cts-pins { 1671 pins = "gpio42", "gpio43"; 1672 function = "blsp_uart7"; 1673 drive-strength = <2>; 1674 bias-pull-up; 1675 }; 1676 }; 1677 1678 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 1679 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1680 function = "gpio"; 1681 drive-strength = <2>; 1682 bias-pull-down; 1683 }; 1684 1685 blsp2_uart4_default: blsp2-uart4-default-state { 1686 tx-rts-pins { 1687 pins = "gpio53", "gpio56"; 1688 function = "blsp_uart10"; 1689 drive-strength = <2>; 1690 bias-disable; 1691 }; 1692 1693 rx-cts-pins { 1694 pins = "gpio54", "gpio55"; 1695 function = "blsp_uart10"; 1696 drive-strength = <2>; 1697 bias-pull-up; 1698 }; 1699 }; 1700 1701 blsp1_i2c1_default: blsp1-i2c1-default-state { 1702 pins = "gpio2", "gpio3"; 1703 function = "blsp_i2c1"; 1704 drive-strength = <2>; 1705 bias-disable; 1706 }; 1707 1708 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { 1709 pins = "gpio2", "gpio3"; 1710 function = "blsp_i2c1"; 1711 drive-strength = <2>; 1712 bias-pull-up; 1713 }; 1714 1715 blsp1_i2c2_default: blsp1-i2c2-default-state { 1716 pins = "gpio6", "gpio7"; 1717 function = "blsp_i2c2"; 1718 drive-strength = <2>; 1719 bias-disable; 1720 }; 1721 1722 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 1723 pins = "gpio6", "gpio7"; 1724 function = "blsp_i2c2"; 1725 drive-strength = <2>; 1726 bias-pull-up; 1727 }; 1728 1729 blsp1_i2c3_default: blsp1-i2c3-default-state { 1730 pins = "gpio10", "gpio11"; 1731 function = "blsp_i2c3"; 1732 drive-strength = <2>; 1733 bias-disable; 1734 }; 1735 1736 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1737 pins = "gpio10", "gpio11"; 1738 function = "blsp_i2c3"; 1739 drive-strength = <2>; 1740 bias-pull-up; 1741 }; 1742 1743 /* BLSP1_I2C4 info is missing */ 1744 1745 /* BLSP1_I2C5 info is missing */ 1746 1747 blsp1_i2c6_default: blsp1-i2c6-default-state { 1748 pins = "gpio29", "gpio30"; 1749 function = "blsp_i2c6"; 1750 drive-strength = <2>; 1751 bias-disable; 1752 }; 1753 1754 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1755 pins = "gpio29", "gpio30"; 1756 function = "blsp_i2c6"; 1757 drive-strength = <2>; 1758 bias-pull-up; 1759 }; 1760 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1761 1762 /* BLSP2_I2C1 info is missing */ 1763 1764 blsp2_i2c2_default: blsp2-i2c2-default-state { 1765 pins = "gpio47", "gpio48"; 1766 function = "blsp_i2c8"; 1767 drive-strength = <2>; 1768 bias-disable; 1769 }; 1770 1771 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1772 pins = "gpio47", "gpio48"; 1773 function = "blsp_i2c8"; 1774 drive-strength = <2>; 1775 bias-pull-up; 1776 }; 1777 1778 /* BLSP2_I2C3 info is missing */ 1779 1780 /* BLSP2_I2C4 info is missing */ 1781 1782 blsp2_i2c5_default: blsp2-i2c5-default-state { 1783 pins = "gpio83", "gpio84"; 1784 function = "blsp_i2c11"; 1785 drive-strength = <2>; 1786 bias-disable; 1787 }; 1788 1789 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1790 pins = "gpio83", "gpio84"; 1791 function = "blsp_i2c11"; 1792 drive-strength = <2>; 1793 bias-pull-up; 1794 }; 1795 1796 blsp2_i2c6_default: blsp2-i2c6-default-state { 1797 pins = "gpio87", "gpio88"; 1798 function = "blsp_i2c12"; 1799 drive-strength = <2>; 1800 bias-disable; 1801 }; 1802 1803 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1804 pins = "gpio87", "gpio88"; 1805 function = "blsp_i2c12"; 1806 drive-strength = <2>; 1807 bias-pull-up; 1808 }; 1809 1810 cci_default: cci-default-state { 1811 cci_i2c0_default: cci-i2c0-default-pins { 1812 pins = "gpio19", "gpio20"; 1813 function = "cci_i2c0"; 1814 drive-strength = <2>; 1815 bias-disable; 1816 }; 1817 1818 cci_i2c1_default: cci-i2c1-default-pins { 1819 pins = "gpio21", "gpio22"; 1820 function = "cci_i2c1"; 1821 drive-strength = <2>; 1822 bias-disable; 1823 }; 1824 }; 1825 1826 cci_sleep: cci-sleep-state { 1827 cci_i2c0_sleep: cci-i2c0-sleep-pins { 1828 pins = "gpio19", "gpio20"; 1829 function = "gpio"; 1830 drive-strength = <2>; 1831 bias-disable; 1832 }; 1833 1834 cci_i2c1_sleep: cci-i2c1-sleep-pins { 1835 pins = "gpio21", "gpio22"; 1836 function = "gpio"; 1837 drive-strength = <2>; 1838 bias-disable; 1839 }; 1840 }; 1841 1842 spi8_default: spi8_default-state { 1843 mosi-pins { 1844 pins = "gpio45"; 1845 function = "blsp_spi8"; 1846 }; 1847 miso-pins { 1848 pins = "gpio46"; 1849 function = "blsp_spi8"; 1850 }; 1851 cs-pins { 1852 pins = "gpio47"; 1853 function = "blsp_spi8"; 1854 }; 1855 clk-pins { 1856 pins = "gpio48"; 1857 function = "blsp_spi8"; 1858 }; 1859 }; 1860 }; 1861 1862 mmcc: clock-controller@fd8c0000 { 1863 compatible = "qcom,mmcc-msm8974"; 1864 #clock-cells = <1>; 1865 #reset-cells = <1>; 1866 #power-domain-cells = <1>; 1867 reg = <0xfd8c0000 0x6000>; 1868 clocks = <&xo_board>, 1869 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1870 <&gcc GPLL0_VOTE>, 1871 <&gcc GPLL1_VOTE>, 1872 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1873 <&mdss_dsi0_phy 1>, 1874 <&mdss_dsi0_phy 0>, 1875 <&mdss_dsi1_phy 1>, 1876 <&mdss_dsi1_phy 0>, 1877 <0>, 1878 <0>, 1879 <0>; 1880 clock-names = "xo", 1881 "mmss_gpll0_vote", 1882 "gpll0_vote", 1883 "gpll1_vote", 1884 "gfx3d_clk_src", 1885 "dsi0pll", 1886 "dsi0pllbyte", 1887 "dsi1pll", 1888 "dsi1pllbyte", 1889 "hdmipll", 1890 "edp_link_clk", 1891 "edp_vco_div"; 1892 }; 1893 1894 mdss: display-subsystem@fd900000 { 1895 compatible = "qcom,mdss"; 1896 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1897 reg-names = "mdss_phys", "vbif_phys"; 1898 1899 power-domains = <&mmcc MDSS_GDSC>; 1900 1901 clocks = <&mmcc MDSS_AHB_CLK>, 1902 <&mmcc MDSS_AXI_CLK>, 1903 <&mmcc MDSS_VSYNC_CLK>; 1904 clock-names = "iface", "bus", "vsync"; 1905 1906 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1907 1908 interrupt-controller; 1909 #interrupt-cells = <1>; 1910 1911 status = "disabled"; 1912 1913 #address-cells = <1>; 1914 #size-cells = <1>; 1915 ranges; 1916 1917 mdp: display-controller@fd900000 { 1918 compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; 1919 reg = <0xfd900100 0x22000>; 1920 reg-names = "mdp_phys"; 1921 1922 interrupt-parent = <&mdss>; 1923 interrupts = <0>; 1924 1925 clocks = <&mmcc MDSS_AHB_CLK>, 1926 <&mmcc MDSS_AXI_CLK>, 1927 <&mmcc MDSS_MDP_CLK>, 1928 <&mmcc MDSS_VSYNC_CLK>; 1929 clock-names = "iface", "bus", "core", "vsync"; 1930 1931 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1932 interconnect-names = "mdp0-mem"; 1933 1934 ports { 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 1938 port@0 { 1939 reg = <0>; 1940 mdp5_intf1_out: endpoint { 1941 remote-endpoint = <&mdss_dsi0_in>; 1942 }; 1943 }; 1944 1945 port@1 { 1946 reg = <1>; 1947 mdp5_intf2_out: endpoint { 1948 remote-endpoint = <&mdss_dsi1_in>; 1949 }; 1950 }; 1951 }; 1952 }; 1953 1954 mdss_dsi0: dsi@fd922800 { 1955 compatible = "qcom,msm8974-dsi-ctrl", 1956 "qcom,mdss-dsi-ctrl"; 1957 reg = <0xfd922800 0x1f8>; 1958 reg-names = "dsi_ctrl"; 1959 1960 interrupt-parent = <&mdss>; 1961 interrupts = <4>; 1962 1963 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1964 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1965 1966 clocks = <&mmcc MDSS_MDP_CLK>, 1967 <&mmcc MDSS_AHB_CLK>, 1968 <&mmcc MDSS_AXI_CLK>, 1969 <&mmcc MDSS_BYTE0_CLK>, 1970 <&mmcc MDSS_PCLK0_CLK>, 1971 <&mmcc MDSS_ESC0_CLK>, 1972 <&mmcc MMSS_MISC_AHB_CLK>; 1973 clock-names = "mdp_core", 1974 "iface", 1975 "bus", 1976 "byte", 1977 "pixel", 1978 "core", 1979 "core_mmss"; 1980 1981 phys = <&mdss_dsi0_phy>; 1982 1983 status = "disabled"; 1984 1985 #address-cells = <1>; 1986 #size-cells = <0>; 1987 1988 ports { 1989 #address-cells = <1>; 1990 #size-cells = <0>; 1991 1992 port@0 { 1993 reg = <0>; 1994 mdss_dsi0_in: endpoint { 1995 remote-endpoint = <&mdp5_intf1_out>; 1996 }; 1997 }; 1998 1999 port@1 { 2000 reg = <1>; 2001 mdss_dsi0_out: endpoint { 2002 }; 2003 }; 2004 }; 2005 }; 2006 2007 mdss_dsi0_phy: phy@fd922a00 { 2008 compatible = "qcom,dsi-phy-28nm-hpm"; 2009 reg = <0xfd922a00 0xd4>, 2010 <0xfd922b00 0x280>, 2011 <0xfd922d80 0x30>; 2012 reg-names = "dsi_pll", 2013 "dsi_phy", 2014 "dsi_phy_regulator"; 2015 2016 #clock-cells = <1>; 2017 #phy-cells = <0>; 2018 2019 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2020 clock-names = "iface", "ref"; 2021 2022 status = "disabled"; 2023 }; 2024 2025 mdss_dsi1: dsi@fd922e00 { 2026 compatible = "qcom,msm8974-dsi-ctrl", 2027 "qcom,mdss-dsi-ctrl"; 2028 reg = <0xfd922e00 0x1f8>; 2029 reg-names = "dsi_ctrl"; 2030 2031 interrupt-parent = <&mdss>; 2032 interrupts = <4>; 2033 2034 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 2035 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2036 2037 clocks = <&mmcc MDSS_MDP_CLK>, 2038 <&mmcc MDSS_AHB_CLK>, 2039 <&mmcc MDSS_AXI_CLK>, 2040 <&mmcc MDSS_BYTE1_CLK>, 2041 <&mmcc MDSS_PCLK1_CLK>, 2042 <&mmcc MDSS_ESC1_CLK>, 2043 <&mmcc MMSS_MISC_AHB_CLK>; 2044 clock-names = "mdp_core", 2045 "iface", 2046 "bus", 2047 "byte", 2048 "pixel", 2049 "core", 2050 "core_mmss"; 2051 2052 phys = <&mdss_dsi1_phy>; 2053 2054 status = "disabled"; 2055 2056 #address-cells = <1>; 2057 #size-cells = <0>; 2058 2059 ports { 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 2063 port@0 { 2064 reg = <0>; 2065 mdss_dsi1_in: endpoint { 2066 remote-endpoint = <&mdp5_intf2_out>; 2067 }; 2068 }; 2069 2070 port@1 { 2071 reg = <1>; 2072 mdss_dsi1_out: endpoint { 2073 }; 2074 }; 2075 }; 2076 }; 2077 2078 mdss_dsi1_phy: phy@fd923000 { 2079 compatible = "qcom,dsi-phy-28nm-hpm"; 2080 reg = <0xfd923000 0xd4>, 2081 <0xfd923100 0x280>, 2082 <0xfd923380 0x30>; 2083 reg-names = "dsi_pll", 2084 "dsi_phy", 2085 "dsi_phy_regulator"; 2086 2087 #clock-cells = <1>; 2088 #phy-cells = <0>; 2089 2090 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2091 clock-names = "iface", "ref"; 2092 2093 status = "disabled"; 2094 }; 2095 }; 2096 2097 cci: cci@fda0c000 { 2098 compatible = "qcom,msm8974-cci"; 2099 #address-cells = <1>; 2100 #size-cells = <0>; 2101 reg = <0xfda0c000 0x1000>; 2102 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 2103 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2104 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 2105 <&mmcc CAMSS_CCI_CCI_CLK>; 2106 clock-names = "camss_top_ahb", 2107 "cci_ahb", 2108 "cci"; 2109 2110 pinctrl-names = "default", "sleep"; 2111 pinctrl-0 = <&cci_default>; 2112 pinctrl-1 = <&cci_sleep>; 2113 2114 status = "disabled"; 2115 2116 cci_i2c0: i2c-bus@0 { 2117 reg = <0>; 2118 clock-frequency = <100000>; 2119 #address-cells = <1>; 2120 #size-cells = <0>; 2121 }; 2122 2123 cci_i2c1: i2c-bus@1 { 2124 reg = <1>; 2125 clock-frequency = <100000>; 2126 #address-cells = <1>; 2127 #size-cells = <0>; 2128 }; 2129 }; 2130 2131 gpu: adreno@fdb00000 { 2132 compatible = "qcom,adreno-330.1", "qcom,adreno"; 2133 reg = <0xfdb00000 0x10000>; 2134 reg-names = "kgsl_3d0_reg_memory"; 2135 2136 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2137 interrupt-names = "kgsl_3d0_irq"; 2138 2139 clocks = <&mmcc OXILI_GFX3D_CLK>, 2140 <&mmcc OXILICX_AHB_CLK>, 2141 <&mmcc OXILICX_AXI_CLK>; 2142 clock-names = "core", "iface", "mem_iface"; 2143 2144 sram = <&gmu_sram>; 2145 power-domains = <&mmcc OXILICX_GDSC>; 2146 operating-points-v2 = <&gpu_opp_table>; 2147 2148 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 2149 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 2150 interconnect-names = "gfx-mem", "ocmem"; 2151 2152 // iommus = <&gpu_iommu 0>; 2153 2154 status = "disabled"; 2155 2156 gpu_opp_table: opp-table { 2157 compatible = "operating-points-v2"; 2158 2159 opp-320000000 { 2160 opp-hz = /bits/ 64 <320000000>; 2161 }; 2162 2163 opp-200000000 { 2164 opp-hz = /bits/ 64 <200000000>; 2165 }; 2166 2167 opp-27000000 { 2168 opp-hz = /bits/ 64 <27000000>; 2169 }; 2170 }; 2171 }; 2172 2173 sram@fdd00000 { 2174 compatible = "qcom,msm8974-ocmem"; 2175 reg = <0xfdd00000 0x2000>, 2176 <0xfec00000 0x180000>; 2177 reg-names = "ctrl", "mem"; 2178 ranges = <0 0xfec00000 0x180000>; 2179 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 2180 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 2181 clock-names = "core", "iface"; 2182 2183 #address-cells = <1>; 2184 #size-cells = <1>; 2185 2186 gmu_sram: gmu-sram@0 { 2187 reg = <0x0 0x100000>; 2188 }; 2189 }; 2190 2191 remoteproc_adsp: remoteproc@fe200000 { 2192 compatible = "qcom,msm8974-adsp-pil"; 2193 reg = <0xfe200000 0x100>; 2194 2195 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2196 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2197 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2198 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2199 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2200 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2201 2202 clocks = <&xo_board>; 2203 clock-names = "xo"; 2204 2205 memory-region = <&adsp_region>; 2206 2207 qcom,smem-states = <&adsp_smp2p_out 0>; 2208 qcom,smem-state-names = "stop"; 2209 2210 status = "disabled"; 2211 2212 smd-edge { 2213 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2214 2215 qcom,ipc = <&apcs 8 8>; 2216 qcom,smd-edge = <1>; 2217 label = "lpass"; 2218 }; 2219 }; 2220 2221 imem: sram@fe805000 { 2222 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 2223 reg = <0xfe805000 0x1000>; 2224 2225 reboot-mode { 2226 compatible = "syscon-reboot-mode"; 2227 offset = <0x65c>; 2228 }; 2229 }; 2230 }; 2231 2232 thermal-zones { 2233 cpu0-thermal { 2234 polling-delay-passive = <250>; 2235 polling-delay = <1000>; 2236 2237 thermal-sensors = <&tsens 5>; 2238 2239 trips { 2240 cpu_alert0: trip0 { 2241 temperature = <75000>; 2242 hysteresis = <2000>; 2243 type = "passive"; 2244 }; 2245 cpu_crit0: trip1 { 2246 temperature = <110000>; 2247 hysteresis = <2000>; 2248 type = "critical"; 2249 }; 2250 }; 2251 }; 2252 2253 cpu1-thermal { 2254 polling-delay-passive = <250>; 2255 polling-delay = <1000>; 2256 2257 thermal-sensors = <&tsens 6>; 2258 2259 trips { 2260 cpu_alert1: trip0 { 2261 temperature = <75000>; 2262 hysteresis = <2000>; 2263 type = "passive"; 2264 }; 2265 cpu_crit1: trip1 { 2266 temperature = <110000>; 2267 hysteresis = <2000>; 2268 type = "critical"; 2269 }; 2270 }; 2271 }; 2272 2273 cpu2-thermal { 2274 polling-delay-passive = <250>; 2275 polling-delay = <1000>; 2276 2277 thermal-sensors = <&tsens 7>; 2278 2279 trips { 2280 cpu_alert2: trip0 { 2281 temperature = <75000>; 2282 hysteresis = <2000>; 2283 type = "passive"; 2284 }; 2285 cpu_crit2: trip1 { 2286 temperature = <110000>; 2287 hysteresis = <2000>; 2288 type = "critical"; 2289 }; 2290 }; 2291 }; 2292 2293 cpu3-thermal { 2294 polling-delay-passive = <250>; 2295 polling-delay = <1000>; 2296 2297 thermal-sensors = <&tsens 8>; 2298 2299 trips { 2300 cpu_alert3: trip0 { 2301 temperature = <75000>; 2302 hysteresis = <2000>; 2303 type = "passive"; 2304 }; 2305 cpu_crit3: trip1 { 2306 temperature = <110000>; 2307 hysteresis = <2000>; 2308 type = "critical"; 2309 }; 2310 }; 2311 }; 2312 2313 q6-dsp-thermal { 2314 polling-delay-passive = <250>; 2315 polling-delay = <1000>; 2316 2317 thermal-sensors = <&tsens 1>; 2318 2319 trips { 2320 q6_dsp_alert0: trip-point0 { 2321 temperature = <90000>; 2322 hysteresis = <2000>; 2323 type = "hot"; 2324 }; 2325 }; 2326 }; 2327 2328 modemtx-thermal { 2329 polling-delay-passive = <250>; 2330 polling-delay = <1000>; 2331 2332 thermal-sensors = <&tsens 2>; 2333 2334 trips { 2335 modemtx_alert0: trip-point0 { 2336 temperature = <90000>; 2337 hysteresis = <2000>; 2338 type = "hot"; 2339 }; 2340 }; 2341 }; 2342 2343 video-thermal { 2344 polling-delay-passive = <250>; 2345 polling-delay = <1000>; 2346 2347 thermal-sensors = <&tsens 3>; 2348 2349 trips { 2350 video_alert0: trip-point0 { 2351 temperature = <95000>; 2352 hysteresis = <2000>; 2353 type = "hot"; 2354 }; 2355 }; 2356 }; 2357 2358 wlan-thermal { 2359 polling-delay-passive = <250>; 2360 polling-delay = <1000>; 2361 2362 thermal-sensors = <&tsens 4>; 2363 2364 trips { 2365 wlan_alert0: trip-point0 { 2366 temperature = <105000>; 2367 hysteresis = <2000>; 2368 type = "hot"; 2369 }; 2370 }; 2371 }; 2372 2373 gpu-top-thermal { 2374 polling-delay-passive = <250>; 2375 polling-delay = <1000>; 2376 2377 thermal-sensors = <&tsens 9>; 2378 2379 trips { 2380 gpu1_alert0: trip-point0 { 2381 temperature = <90000>; 2382 hysteresis = <2000>; 2383 type = "hot"; 2384 }; 2385 }; 2386 }; 2387 2388 gpu-bottom-thermal { 2389 polling-delay-passive = <250>; 2390 polling-delay = <1000>; 2391 2392 thermal-sensors = <&tsens 10>; 2393 2394 trips { 2395 gpu2_alert0: trip-point0 { 2396 temperature = <90000>; 2397 hysteresis = <2000>; 2398 type = "hot"; 2399 }; 2400 }; 2401 }; 2402 }; 2403 2404 timer { 2405 compatible = "arm,armv7-timer"; 2406 interrupts = <GIC_PPI 2 0xf08>, 2407 <GIC_PPI 3 0xf08>, 2408 <GIC_PPI 4 0xf08>, 2409 <GIC_PPI 1 0xf08>; 2410 clock-frequency = <19200000>; 2411 }; 2412}; 2413