xref: /freebsd/sys/contrib/device-tree/src/arm/nxp/vf/vf610-zii-dev-rev-c.dts (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
4 */
5
6/dts-v1/;
7#include "vf610-zii-dev.dtsi"
8
9/ {
10	model = "ZII VF610 Development Board, Rev C";
11	compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
12
13	mdio-mux {
14		compatible = "mdio-mux-gpio";
15		pinctrl-0 = <&pinctrl_mdio_mux>;
16		pinctrl-names = "default";
17		gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
18			 &gpio0 9  GPIO_ACTIVE_HIGH
19			 &gpio0 25 GPIO_ACTIVE_HIGH>;
20		mdio-parent-bus = <&mdio1>;
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		mdio_mux_1: mdio@1 {
25			reg = <1>;
26			#address-cells = <1>;
27			#size-cells = <0>;
28
29			switch0: switch@0 {
30				compatible = "marvell,mv88e6190";
31				pinctrl-0 = <&pinctrl_gpio_switch0>;
32				pinctrl-names = "default";
33				reg = <0>;
34				dsa,member = <0 0>;
35				eeprom-length = <65536>;
36				interrupt-parent = <&gpio0>;
37				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
38				interrupt-controller;
39				#interrupt-cells = <2>;
40
41				ports {
42					#address-cells = <1>;
43					#size-cells = <0>;
44
45					port@0 {
46						reg = <0>;
47						phy-mode = "rmii";
48						ethernet = <&fec1>;
49
50						fixed-link {
51							speed = <100>;
52							full-duplex;
53						};
54					};
55
56					port@1 {
57						reg = <1>;
58						label = "lan1";
59						phy-handle = <&switch0phy1>;
60					};
61
62					port@2 {
63						reg = <2>;
64						label = "lan2";
65						phy-handle = <&switch0phy2>;
66					};
67
68					port@3 {
69						reg = <3>;
70						label = "lan3";
71						phy-handle = <&switch0phy3>;
72					};
73
74					port@4 {
75						reg = <4>;
76						label = "lan4";
77						phy-handle = <&switch0phy4>;
78					};
79
80					switch0port10: port@10 {
81						reg = <10>;
82						label = "dsa";
83						phy-mode = "xaui";
84						link = <&switch1port10>;
85
86						fixed-link {
87							speed = <10000>;
88							full-duplex;
89						};
90					};
91				};
92
93				mdio {
94					#address-cells = <1>;
95					#size-cells = <0>;
96
97					switch0phy1: switch0phy@1 {
98						reg = <1>;
99						interrupt-parent = <&switch0>;
100						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
101					};
102
103					switch0phy2: switch0phy@2 {
104						reg = <2>;
105						interrupt-parent = <&switch0>;
106						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
107					};
108
109					switch0phy3: switch0phy@3 {
110						reg = <3>;
111						interrupt-parent = <&switch0>;
112						interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
113					};
114
115					switch0phy4: switch0phy@4 {
116						reg = <4>;
117						interrupt-parent = <&switch0>;
118						interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
119					};
120				};
121			};
122		};
123
124		mdio_mux_2: mdio@2 {
125			reg = <2>;
126			#address-cells = <1>;
127			#size-cells = <0>;
128
129			switch1: switch@0 {
130				compatible = "marvell,mv88e6190";
131				pinctrl-0 = <&pinctrl_gpio_switch1>;
132				pinctrl-names = "default";
133				reg = <0>;
134				dsa,member = <0 1>;
135				eeprom-length = <65536>;
136				interrupt-parent = <&gpio0>;
137				interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
138				interrupt-controller;
139				#interrupt-cells = <2>;
140
141				ports {
142					#address-cells = <1>;
143					#size-cells = <0>;
144
145					port@1 {
146						reg = <1>;
147						label = "lan5";
148						phy-handle = <&switch1phy1>;
149					};
150
151					port@2 {
152						reg = <2>;
153						label = "lan6";
154						phy-handle = <&switch1phy2>;
155					};
156
157					port@3 {
158						reg = <3>;
159						label = "lan7";
160						phy-handle = <&switch1phy3>;
161					};
162
163					port@4 {
164						reg = <4>;
165						label = "lan8";
166						phy-handle = <&switch1phy4>;
167					};
168
169					port@9 {
170						reg = <9>;
171						label = "sff2";
172						phy-mode = "1000base-x";
173						managed = "in-band-status";
174						sfp = <&sff2>;
175					};
176
177					switch1port10: port@10 {
178						reg = <10>;
179						label = "dsa";
180						phy-mode = "xaui";
181						link = <&switch0port10>;
182
183						fixed-link {
184							speed = <10000>;
185							full-duplex;
186						};
187					};
188				};
189				mdio {
190					#address-cells = <1>;
191					#size-cells = <0>;
192
193					switch1phy1: switch1phy@1 {
194						reg = <1>;
195						interrupt-parent = <&switch1>;
196						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
197					};
198
199					switch1phy2: switch1phy@2 {
200						reg = <2>;
201						interrupt-parent = <&switch1>;
202						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
203					};
204
205					switch1phy3: switch1phy@3 {
206						reg = <3>;
207						interrupt-parent = <&switch1>;
208						interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
209					};
210
211					switch1phy4: switch1phy@4 {
212						reg = <4>;
213						interrupt-parent = <&switch1>;
214						interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
215					};
216				};
217			};
218		};
219
220		mdio_mux_4: mdio@4 {
221			reg = <4>;
222			#address-cells = <1>;
223			#size-cells = <0>;
224		};
225	};
226
227	sff2: sff2 {
228		/* lower */
229		compatible = "sff,sff";
230		i2c-bus = <&sff2_i2c>;
231		los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
232		tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
233	};
234
235	sff3: sff3 {
236		/* upper */
237		compatible = "sff,sff";
238		i2c-bus = <&sff3_i2c>;
239		los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
240		tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
241	};
242};
243
244&dspi0 {
245	bus-num = <0>;
246	pinctrl-names = "default";
247	pinctrl-0 = <&pinctrl_dspi0>;
248	status = "okay";
249	spi-num-chipselects = <2>;
250
251	flash@0 {
252		compatible = "m25p128", "jedec,spi-nor";
253		#address-cells = <1>;
254		#size-cells = <1>;
255		reg = <0>;
256		spi-max-frequency = <1000000>;
257	};
258
259	atzb-rf-233@1 {
260		compatible = "atmel,at86rf233";
261
262		pinctrl-names = "default";
263		pinctrl-0 = <&pinctr_atzb_rf_233>;
264
265		spi-max-frequency = <7500000>;
266		reg = <1>;
267		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
268		interrupt-parent = <&gpio3>;
269		xtal-trim = /bits/ 8 <0x06>;
270
271		sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
272		reset-gpio = <&gpio6 10 GPIO_ACTIVE_LOW>;
273
274		fsl,spi-cs-sck-delay = <180>;
275		fsl,spi-sck-cs-delay = <250>;
276	};
277};
278
279&i2c0 {
280	/*
281	 * U712
282	 *
283	 * Exposed signals:
284	 *    P1 - WE2_CMD
285	 *    P2 - WE2_CLK
286	 */
287	gpio5: io-expander@18 {
288		compatible = "nxp,pca9557";
289		reg = <0x18>;
290		gpio-controller;
291		#gpio-cells = <2>;
292	};
293
294	/*
295	 * U121
296	 *
297	 * Exposed signals:
298	 *    I/O0  - ENET_SWR_EN
299	 *    I/O1  - ESW1_RESETn
300	 *    I/O2  - ARINC_RESET
301	 *    I/O3  - DD1_IO_RESET
302	 *    I/O4  - ESW2_RESETn
303	 *    I/O5  - ESW3_RESETn
304	 *    I/O6  - ESW4_RESETn
305	 *    I/O8  - TP909
306	 *    I/O9  - FEM_SEL
307	 *    I/O10 - WIFI_RESETn
308	 *    I/O11 - PHY_RSTn
309	 *    I/O12 - OPT1_SD
310	 *    I/O13 - OPT2_SD
311	 *    I/O14 - OPT1_TX_DIS
312	 *    I/O15 - OPT2_TX_DIS
313	 */
314	gpio6: sx1503@20 {
315		compatible = "semtech,sx1503q";
316
317		pinctrl-names = "default";
318		pinctrl-0 = <&pinctrl_sx1503_20>;
319		#gpio-cells = <2>;
320		#interrupt-cells = <2>;
321		reg = <0x20>;
322		interrupt-parent = <&gpio0>;
323		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
324		gpio-controller;
325		interrupt-controller;
326	};
327
328	/*
329	 * U715
330	 *
331	 * Exposed signals:
332	 *     IO0 - WE1_CLK
333	 *     IO1 - WE1_CMD
334	 */
335	gpio7: io-expander@22 {
336		compatible = "nxp,pca9554";
337		reg = <0x22>;
338		gpio-controller;
339		#gpio-cells = <2>;
340
341	};
342};
343
344&i2c1 {
345	eeprom@50 {
346		compatible = "atmel,24c02";
347		reg = <0x50>;
348		read-only;
349	};
350};
351
352&i2c2 {
353	i2c-mux@70 {
354		compatible = "nxp,pca9548";
355		pinctrl-0 = <&pinctrl_i2c_mux_reset>;
356		pinctrl-names = "default";
357		#address-cells = <1>;
358		#size-cells = <0>;
359		reg = <0x70>;
360		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
361
362		i2c@0 {
363			#address-cells = <1>;
364			#size-cells = <0>;
365			reg = <0>;
366		};
367
368		sff2_i2c: i2c@1 {
369			#address-cells = <1>;
370			#size-cells = <0>;
371			reg = <1>;
372		};
373
374		sff3_i2c: i2c@2 {
375			#address-cells = <1>;
376			#size-cells = <0>;
377			reg = <2>;
378		};
379
380		i2c@3 {
381			#address-cells = <1>;
382			#size-cells = <0>;
383			reg = <3>;
384		};
385	};
386};
387
388&uart3 {
389	pinctrl-names = "default";
390	pinctrl-0 = <&pinctrl_uart3>;
391	status = "okay";
392};
393
394&gpio0 {
395	eth0_intrp {
396		gpio-hog;
397		gpios = <23 GPIO_ACTIVE_HIGH>;
398		input;
399		line-name = "sx1503-irq";
400	};
401};
402
403&gpio3 {
404	eth0_intrp {
405		gpio-hog;
406		gpios = <2 GPIO_ACTIVE_HIGH>;
407		input;
408		line-name = "eth0-intrp";
409	};
410};
411
412&fec0 {
413	mdio {
414		#address-cells = <1>;
415		#size-cells = <0>;
416		status = "okay";
417
418		ethernet-phy@0 {
419			compatible = "ethernet-phy-ieee802.3-c22";
420
421			pinctrl-names = "default";
422			pinctrl-0 = <&pinctrl_fec0_phy_int>;
423
424			interrupt-parent = <&gpio3>;
425			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
426			reg = <0>;
427		};
428	};
429};
430
431&iomuxc {
432	pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
433		fsl,pins = <
434			VF610_PAD_PTB2__GPIO_24		0x31c2
435			VF610_PAD_PTE27__GPIO_132	0x33e2
436		>;
437	};
438
439
440	pinctrl_sx1503_20: pinctrl-sx1503-20 {
441		fsl,pins = <
442			VF610_PAD_PTB1__GPIO_23		0x219d
443		>;
444	};
445
446	pinctrl_uart3: uart3grp {
447		fsl,pins = <
448			VF610_PAD_PTA20__UART3_TX	0x21a2
449			VF610_PAD_PTA21__UART3_RX	0x21a1
450		>;
451	};
452
453	pinctrl_mdio_mux: pinctrl-mdio-mux {
454		fsl,pins = <
455			VF610_PAD_PTA18__GPIO_8		0x31c2
456			VF610_PAD_PTA19__GPIO_9		0x31c2
457			VF610_PAD_PTB3__GPIO_25		0x31c2
458		>;
459	};
460
461	pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
462		fsl,pins = <
463			VF610_PAD_PTB28__GPIO_98	0x219d
464		>;
465	};
466};
467