xref: /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/imx6sll-kobo-clarahd.dts (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1// SPDX-License-Identifier: (GPL-2.0)
2/*
3 * Device tree for the Kobo Clara HD ebook reader
4 *
5 * Name on mainboard is: 37NB-E60K00+4A4
6 * Serials start with: E60K02 (a number also seen in
7 * vendor kernel sources)
8 *
9 * This mainboard seems to be equipped with different SoCs.
10 * In the Kobo Clara HD ebook reader it is an i.MX6SLL
11 *
12 * Copyright 2019 Andreas Kemnade
13 * based on works
14 * Copyright 2016 Freescale Semiconductor, Inc.
15 */
16
17/dts-v1/;
18
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/gpio/gpio.h>
21#include "imx6sll.dtsi"
22#include "e60k02.dtsi"
23
24/ {
25	model = "Kobo Clara HD";
26	compatible = "kobo,clarahd", "fsl,imx6sll";
27};
28
29&clks {
30	assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
31	assigned-clock-rates = <393216000>;
32};
33
34&cpu0 {
35	arm-supply = <&dcdc3_reg>;
36	soc-supply = <&dcdc1_reg>;
37};
38
39&gpio_keys {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_gpio_keys>;
42};
43
44&i2c1 {
45	pinctrl-names = "default","sleep";
46	pinctrl-0 = <&pinctrl_i2c1>;
47	pinctrl-1 = <&pinctrl_i2c1_sleep>;
48};
49
50&i2c2 {
51	pinctrl-names = "default","sleep";
52	pinctrl-0 = <&pinctrl_i2c2>;
53	pinctrl-1 = <&pinctrl_i2c2_sleep>;
54};
55
56&i2c3 {
57	pinctrl-names = "default";
58	pinctrl-0 = <&pinctrl_i2c3>;
59};
60
61&iomuxc {
62	pinctrl-names = "default";
63	pinctrl-0 = <&pinctrl_hog>;
64
65	pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
66		fsl,pins = <
67			MX6SLL_PAD_SD1_DATA3__GPIO5_IO06                0x17059 /* TP_INT */
68			MX6SLL_PAD_SD1_DATA2__GPIO5_IO13                0x10059 /* TP_RST */
69		>;
70	};
71
72	pinctrl_gpio_keys: gpio-keysgrp {
73		fsl,pins = <
74			MX6SLL_PAD_SD1_DATA1__GPIO5_IO08	0x17059	/* PWR_SW */
75			MX6SLL_PAD_SD1_DATA4__GPIO5_IO12	0x17059	/* HALL_EN */
76		>;
77	};
78
79	pinctrl_hog: hoggrp {
80		fsl,pins = <
81			MX6SLL_PAD_LCD_DATA00__GPIO2_IO20	0x79
82			MX6SLL_PAD_LCD_DATA01__GPIO2_IO21	0x79
83			MX6SLL_PAD_LCD_DATA02__GPIO2_IO22	0x79
84			MX6SLL_PAD_LCD_DATA03__GPIO2_IO23	0x79
85			MX6SLL_PAD_LCD_DATA04__GPIO2_IO24	0x79
86			MX6SLL_PAD_LCD_DATA05__GPIO2_IO25	0x79
87			MX6SLL_PAD_LCD_DATA06__GPIO2_IO26	0x79
88			MX6SLL_PAD_LCD_DATA07__GPIO2_IO27	0x79
89			MX6SLL_PAD_LCD_DATA08__GPIO2_IO28	0x79
90			MX6SLL_PAD_LCD_DATA09__GPIO2_IO29	0x79
91			MX6SLL_PAD_LCD_DATA10__GPIO2_IO30	0x79
92			MX6SLL_PAD_LCD_DATA11__GPIO2_IO31	0x79
93			MX6SLL_PAD_LCD_DATA12__GPIO3_IO00	0x79
94			MX6SLL_PAD_LCD_DATA13__GPIO3_IO01	0x79
95			MX6SLL_PAD_LCD_DATA14__GPIO3_IO02	0x79
96			MX6SLL_PAD_LCD_DATA15__GPIO3_IO03	0x79
97			MX6SLL_PAD_LCD_DATA16__GPIO3_IO04	0x79
98			MX6SLL_PAD_LCD_DATA17__GPIO3_IO05	0x79
99			MX6SLL_PAD_LCD_DATA18__GPIO3_IO06	0x79
100			MX6SLL_PAD_LCD_DATA19__GPIO3_IO07	0x79
101			MX6SLL_PAD_LCD_DATA20__GPIO3_IO08	0x79
102			MX6SLL_PAD_LCD_DATA21__GPIO3_IO09	0x79
103			MX6SLL_PAD_LCD_DATA22__GPIO3_IO10	0x79
104			MX6SLL_PAD_LCD_DATA23__GPIO3_IO11	0x79
105			MX6SLL_PAD_LCD_CLK__GPIO2_IO15		0x79
106			MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16	0x79
107			MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17	0x79
108			MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18	0x79
109			MX6SLL_PAD_LCD_RESET__GPIO2_IO19	0x79
110			MX6SLL_PAD_KEY_COL3__GPIO3_IO30		0x79
111			MX6SLL_PAD_KEY_ROW7__GPIO4_IO07		0x79
112			MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13	0x79
113			MX6SLL_PAD_KEY_COL5__GPIO4_IO02		0x79
114		>;
115	};
116
117	pinctrl_i2c1: i2c1grp {
118		fsl,pins = <
119			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	0x4001f8b1
120			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	0x4001f8b1
121		>;
122	};
123
124	pinctrl_i2c1_sleep: i2c1grp-sleep {
125		fsl,pins = <
126			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	0x400108b1
127			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	0x400108b1
128		>;
129	};
130
131	pinctrl_i2c2: i2c2grp {
132		fsl,pins = <
133			MX6SLL_PAD_I2C2_SCL__I2C2_SCL	0x4001f8b1
134			MX6SLL_PAD_I2C2_SDA__I2C2_SDA	0x4001f8b1
135		>;
136	};
137
138	pinctrl_i2c2_sleep: i2c2grp-sleep {
139		fsl,pins = <
140			MX6SLL_PAD_I2C2_SCL__I2C2_SCL	0x400108b1
141			MX6SLL_PAD_I2C2_SDA__I2C2_SDA	0x400108b1
142		>;
143	};
144
145	pinctrl_i2c3: i2c3grp {
146		fsl,pins = <
147			MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
148			MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
149		>;
150	};
151
152	pinctrl_led: ledgrp {
153		fsl,pins = <
154			MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059
155		>;
156	};
157
158	pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
159		fsl,pins = <
160			MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10	0x10059 /* HWEN */
161		>;
162	};
163
164	pinctrl_ricoh_gpio: ricoh-gpiogrp {
165		fsl,pins = <
166			MX6SLL_PAD_SD1_CLK__GPIO5_IO15	0x1b8b1 /* ricoh619 chg */
167			MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
168			MX6SLL_PAD_KEY_COL2__GPIO3_IO28	0x1b8b1 /* ricoh619 bat_low_int */
169		>;
170	};
171
172	pinctrl_uart1: uart1grp {
173		fsl,pins = <
174			MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
175			MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
176		>;
177	};
178
179	pinctrl_uart4: uart4grp {
180		fsl,pins = <
181			MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1
182			MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1
183		>;
184	};
185
186	pinctrl_usbotg1: usbotg1grp {
187		fsl,pins = <
188			MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
189		>;
190	};
191
192	pinctrl_usdhc2: usdhc2grp {
193		fsl,pins = <
194			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x17059
195			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x13059
196			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x17059
197			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x17059
198			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x17059
199			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x17059
200		>;
201	};
202
203	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
204		fsl,pins = <
205			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170b9
206			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130b9
207			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x170b9
208			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170b9
209			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170b9
210			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170b9
211		>;
212	};
213
214	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
215		fsl,pins = <
216			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170f9
217			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130f9
218			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x170f9
219			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170f9
220			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170f9
221			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170f9
222		>;
223	};
224
225	pinctrl_usdhc2_sleep: usdhc2grp-sleep {
226		fsl,pins = <
227			MX6SLL_PAD_SD2_CMD__GPIO5_IO04		0x100f9
228			MX6SLL_PAD_SD2_CLK__GPIO5_IO05		0x100f9
229			MX6SLL_PAD_SD2_DATA0__GPIO5_IO01	0x100f9
230			MX6SLL_PAD_SD2_DATA1__GPIO4_IO30	0x100f9
231			MX6SLL_PAD_SD2_DATA2__GPIO5_IO03	0x100f9
232			MX6SLL_PAD_SD2_DATA3__GPIO4_IO28	0x100f9
233		>;
234	};
235
236	pinctrl_usdhc3: usdhc3grp {
237		fsl,pins = <
238			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x11059
239			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x11059
240			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x11059
241			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x11059
242			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x11059
243			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x11059
244		>;
245	};
246
247	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
248		fsl,pins = <
249			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
250			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170b9
251			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
252			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
253			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
254			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
255		>;
256	};
257
258	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
259		fsl,pins = <
260			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
261			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170f9
262			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
263			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
264			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
265			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
266		>;
267	};
268
269	pinctrl_usdhc3_sleep: usdhc3grp-sleep {
270		fsl,pins = <
271			MX6SLL_PAD_SD3_CMD__GPIO5_IO21	0x100c1
272			MX6SLL_PAD_SD3_CLK__GPIO5_IO18	0x100c1
273			MX6SLL_PAD_SD3_DATA0__GPIO5_IO19	0x100c1
274			MX6SLL_PAD_SD3_DATA1__GPIO5_IO20	0x100c1
275			MX6SLL_PAD_SD3_DATA2__GPIO5_IO16	0x100c1
276			MX6SLL_PAD_SD3_DATA3__GPIO5_IO17	0x100c1
277		>;
278	};
279
280	pinctrl_wifi_power: wifi-powergrp {
281		fsl,pins = <
282			MX6SLL_PAD_SD2_DATA6__GPIO4_IO29	0x10059		/* WIFI_3V3_ON */
283		>;
284	};
285
286	pinctrl_wifi_reset: wifi-resetgrp {
287		fsl,pins = <
288			MX6SLL_PAD_SD2_DATA7__GPIO5_IO00	0x10059		/* WIFI_RST */
289		>;
290	};
291};
292
293&leds {
294	pinctrl-names = "default";
295	pinctrl-0 = <&pinctrl_led>;
296};
297
298&lm3630a {
299	pinctrl-names = "default";
300	pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
301};
302
303&reg_wifi {
304	pinctrl-names = "default";
305	pinctrl-0 = <&pinctrl_wifi_power>;
306};
307
308&ricoh619 {
309	pinctrl-names = "default";
310	pinctrl-0 = <&pinctrl_ricoh_gpio>;
311};
312
313&uart1 {
314	pinctrl-names = "default";
315	pinctrl-0 = <&pinctrl_uart1>;
316};
317
318&uart4 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_uart4>;
321};
322
323&usdhc2 {
324	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
325	pinctrl-0 = <&pinctrl_usdhc2>;
326	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
327	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
328	pinctrl-3 = <&pinctrl_usdhc2_sleep>;
329};
330
331&usdhc3 {
332	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
333	pinctrl-0 = <&pinctrl_usdhc3>;
334	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
335	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
336	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
337};
338
339&wifi_pwrseq {
340	pinctrl-names = "default";
341	pinctrl-0 = <&pinctrl_wifi_reset>;
342};
343