1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2016 Boundary Devices, Inc. 4 */ 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/input/input.h> 7 8/ { 9 chosen { 10 stdout-path = &uart2; 11 }; 12 13 memory@10000000 { 14 device_type = "memory"; 15 reg = <0x10000000 0x40000000>; 16 }; 17 18 backlight_lcd: backlight-lcd { 19 compatible = "pwm-backlight"; 20 pwms = <&pwm1 0 5000000>; 21 brightness-levels = <0 4 8 16 32 64 128 255>; 22 default-brightness-level = <7>; 23 power-supply = <®_3p3v>; 24 status = "okay"; 25 }; 26 27 backlight_lvds0: backlight-lvds0 { 28 compatible = "pwm-backlight"; 29 pwms = <&pwm4 0 5000000>; 30 brightness-levels = <0 4 8 16 32 64 128 255>; 31 default-brightness-level = <7>; 32 power-supply = <®_3p3v>; 33 status = "okay"; 34 }; 35 36 backlight_lvds1: backlight-lvds1 { 37 compatible = "gpio-backlight"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_backlight_lvds1>; 40 gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; 41 default-on; 42 status = "okay"; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_gpio_keys>; 49 50 power { 51 label = "Power Button"; 52 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 53 linux,code = <KEY_POWER>; 54 wakeup-source; 55 }; 56 57 menu { 58 label = "Menu"; 59 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 60 linux,code = <KEY_MENU>; 61 }; 62 63 home { 64 label = "Home"; 65 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 66 linux,code = <KEY_HOME>; 67 }; 68 69 back { 70 label = "Back"; 71 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 72 linux,code = <KEY_BACK>; 73 }; 74 75 volume-up { 76 label = "Volume Up"; 77 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 78 linux,code = <KEY_VOLUMEUP>; 79 }; 80 81 volume-down { 82 label = "Volume Down"; 83 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 84 linux,code = <KEY_VOLUMEDOWN>; 85 }; 86 }; 87 88 lcd_display: disp0 { 89 compatible = "fsl,imx-parallel-display"; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 interface-pix-fmt = "bgr666"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_j15>; 95 status = "okay"; 96 97 port@0 { 98 reg = <0>; 99 100 lcd_display_in: endpoint { 101 remote-endpoint = <&ipu1_di0_disp0>; 102 }; 103 }; 104 105 port@1 { 106 reg = <1>; 107 108 lcd_display_out: endpoint { 109 remote-endpoint = <&lcd_panel_in>; 110 }; 111 }; 112 }; 113 114 panel-lcd { 115 compatible = "okaya,rs800480t-7x0gp"; 116 backlight = <&backlight_lcd>; 117 118 port { 119 lcd_panel_in: endpoint { 120 remote-endpoint = <&lcd_display_out>; 121 }; 122 }; 123 }; 124 125 panel-lvds0 { 126 compatible = "hannstar,hsd100pxn1"; 127 backlight = <&backlight_lvds0>; 128 129 port { 130 panel_in_lvds0: endpoint { 131 remote-endpoint = <&lvds0_out>; 132 }; 133 }; 134 }; 135 136 panel-lvds1 { 137 compatible = "hannstar,hsd100pxn1"; 138 backlight = <&backlight_lvds1>; 139 140 port { 141 panel_in_lvds1: endpoint { 142 remote-endpoint = <&lvds1_out>; 143 }; 144 }; 145 }; 146 147 reg_1p8v: regulator-1v8 { 148 compatible = "regulator-fixed"; 149 regulator-name = "1P8V"; 150 regulator-min-microvolt = <1800000>; 151 regulator-max-microvolt = <1800000>; 152 regulator-always-on; 153 }; 154 155 reg_2p5v: regulator-2v5 { 156 compatible = "regulator-fixed"; 157 regulator-name = "2P5V"; 158 regulator-min-microvolt = <2500000>; 159 regulator-max-microvolt = <2500000>; 160 regulator-always-on; 161 }; 162 163 reg_3p3v: regulator-3v3 { 164 compatible = "regulator-fixed"; 165 regulator-name = "3P3V"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 regulator-always-on; 169 }; 170 171 reg_can_xcvr: regulator-can-xcvr { 172 compatible = "regulator-fixed"; 173 regulator-name = "CAN XCVR"; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_can_xcvr>; 178 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 179 }; 180 181 reg_usb_h1_vbus: regulator-usb-h1-vbus { 182 compatible = "regulator-fixed"; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_usbh1>; 185 regulator-name = "usb_h1_vbus"; 186 regulator-min-microvolt = <3300000>; 187 regulator-max-microvolt = <3300000>; 188 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 189 enable-active-high; 190 regulator-always-on; 191 }; 192 193 reg_usb_otg_vbus: regulator-usb-otg-vbus { 194 compatible = "regulator-fixed"; 195 regulator-name = "usb_otg_vbus"; 196 regulator-min-microvolt = <5000000>; 197 regulator-max-microvolt = <5000000>; 198 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 199 enable-active-high; 200 }; 201 202 reg_wlan_vmmc: regulator-wlan-vmmc { 203 compatible = "regulator-fixed"; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_wlan_vmmc>; 206 regulator-name = "reg_wlan_vmmc"; 207 regulator-min-microvolt = <3300000>; 208 regulator-max-microvolt = <3300000>; 209 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 210 startup-delay-us = <70000>; 211 enable-active-high; 212 }; 213 214 sound { 215 compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", 216 "fsl,imx-audio-sgtl5000"; 217 model = "imx6q-nitrogen6_som2-sgtl5000"; 218 ssi-controller = <&ssi1>; 219 audio-codec = <&codec>; 220 audio-routing = 221 "MIC_IN", "Mic Jack", 222 "Mic Jack", "Mic Bias", 223 "Headphone Jack", "HP_OUT"; 224 mux-int-port = <1>; 225 mux-ext-port = <3>; 226 }; 227}; 228 229&audmux { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_audmux>; 232 status = "okay"; 233}; 234 235&can1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_can1>; 238 xceiver-supply = <®_can_xcvr>; 239 status = "okay"; 240}; 241 242&clks { 243 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 244 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 245 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 246 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 247}; 248 249&ecspi1 { 250 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_ecspi1>; 253 status = "okay"; 254 255 flash: flash@0 { 256 compatible = "microchip,sst25vf016b"; 257 spi-max-frequency = <20000000>; 258 reg = <0>; 259 }; 260}; 261 262&fec { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_enet>; 265 phy-mode = "rgmii"; 266 /delete-property/ interrupts; 267 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 268 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 269 fsl,err006687-workaround-present; 270 status = "okay"; 271}; 272 273&hdmi { 274 ddc-i2c-bus = <&i2c2>; 275 status = "okay"; 276}; 277 278&i2c1 { 279 clock-frequency = <100000>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_i2c1>; 282 status = "okay"; 283 284 codec: sgtl5000@a { 285 compatible = "fsl,sgtl5000"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_sgtl5000>; 288 reg = <0x0a>; 289 #sound-dai-cells = <0>; 290 clocks = <&clks IMX6QDL_CLK_CKO>; 291 VDDA-supply = <®_2p5v>; 292 VDDIO-supply = <®_3p3v>; 293 }; 294 295 rtc@68 { 296 compatible = "microcrystal,rv4162"; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_rv4162>; 299 reg = <0x68>; 300 interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; 301 }; 302}; 303 304&i2c2 { 305 clock-frequency = <100000>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_i2c2>; 308 status = "okay"; 309}; 310 311&i2c3 { 312 clock-frequency = <100000>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_i2c3>; 315 status = "okay"; 316 317 touchscreen@4 { 318 compatible = "eeti,egalax_ts"; 319 reg = <0x04>; 320 interrupt-parent = <&gpio1>; 321 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 322 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 323 }; 324 325 touchscreen@38 { 326 compatible = "edt,edt-ft5x06"; 327 reg = <0x38>; 328 interrupt-parent = <&gpio1>; 329 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 330 wakeup-source; 331 }; 332}; 333 334&iomuxc { 335 pinctrl_audmux: audmuxgrp { 336 fsl,pins = < 337 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 338 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 339 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 340 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 341 >; 342 }; 343 344 pinctrl_backlight_lvds1: backlight-lvds1grp { 345 fsl,pins = < 346 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 347 >; 348 }; 349 350 pinctrl_can1: can1grp { 351 fsl,pins = < 352 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 353 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 354 >; 355 }; 356 357 pinctrl_can_xcvr: can-xcvrgrp { 358 fsl,pins = < 359 /* Flexcan XCVR enable */ 360 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 361 >; 362 }; 363 364 pinctrl_ecspi1: ecspi1grp { 365 fsl,pins = < 366 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 367 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 368 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 369 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 370 >; 371 }; 372 373 pinctrl_enet: enetgrp { 374 fsl,pins = < 375 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 376 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 377 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 378 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 379 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 380 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 381 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 382 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 383 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 384 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 385 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 386 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 387 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 388 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 389 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 390 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 391 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 392 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 393 >; 394 }; 395 396 pinctrl_gpio_keys: gpio-keysgrp { 397 fsl,pins = < 398 /* Power Button */ 399 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 400 /* Menu Button */ 401 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 402 /* Home Button */ 403 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 404 /* Back Button */ 405 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 406 /* Volume Up Button */ 407 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 408 /* Volume Down Button */ 409 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 410 >; 411 }; 412 413 pinctrl_i2c1: i2c1grp { 414 fsl,pins = < 415 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 416 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 417 >; 418 }; 419 420 pinctrl_i2c2: i2c2grp { 421 fsl,pins = < 422 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 423 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 424 >; 425 }; 426 427 pinctrl_i2c3: i2c3grp { 428 fsl,pins = < 429 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 430 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 431 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 432 >; 433 }; 434 435 pinctrl_i2c3mux: i2c3muxgrp { 436 fsl,pins = < 437 /* PCIe I2C enable */ 438 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 439 >; 440 }; 441 442 pinctrl_j15: j15grp { 443 fsl,pins = < 444 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 445 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 446 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 447 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 448 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 449 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 450 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 451 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 452 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 453 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 454 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 455 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 456 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 457 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 458 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 459 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 460 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 461 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 462 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 463 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 464 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 465 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 466 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 467 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 468 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 469 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 470 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 471 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 472 >; 473 }; 474 475 pinctrl_pcie: pciegrp { 476 fsl,pins = < 477 /* PCIe reset */ 478 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 479 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 480 >; 481 }; 482 483 pinctrl_pwm1: pwm1grp { 484 fsl,pins = < 485 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 486 >; 487 }; 488 489 pinctrl_pwm3: pwm3grp { 490 fsl,pins = < 491 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 492 >; 493 }; 494 495 pinctrl_pwm4: pwm4grp { 496 fsl,pins = < 497 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 498 >; 499 }; 500 501 pinctrl_rv4162: rv4162grp { 502 fsl,pins = < 503 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 504 >; 505 }; 506 507 pinctrl_sgtl5000: sgtl5000grp { 508 fsl,pins = < 509 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 510 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 511 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 512 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 513 >; 514 }; 515 516 pinctrl_uart1: uart1grp { 517 fsl,pins = < 518 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 519 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 520 >; 521 }; 522 523 pinctrl_uart2: uart2grp { 524 fsl,pins = < 525 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 526 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 527 >; 528 }; 529 530 pinctrl_uart3: uart3grp { 531 fsl,pins = < 532 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 533 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 534 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 535 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 536 >; 537 }; 538 539 pinctrl_usbh1: usbh1grp { 540 fsl,pins = < 541 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 542 >; 543 }; 544 545 pinctrl_usbotg: usbotggrp { 546 fsl,pins = < 547 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 548 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 549 /* power enable, high active */ 550 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 551 >; 552 }; 553 554 pinctrl_usdhc2: usdhc2grp { 555 fsl,pins = < 556 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 557 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 558 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 559 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 560 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 561 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 562 >; 563 }; 564 565 pinctrl_usdhc3: usdhc3grp { 566 fsl,pins = < 567 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 568 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 569 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 570 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 571 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 572 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 573 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 574 >; 575 }; 576 577 pinctrl_usdhc4: usdhc4grp { 578 fsl,pins = < 579 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 580 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 581 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 582 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 583 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 584 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 585 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 586 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 587 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 588 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 589 >; 590 }; 591 592 pinctrl_wlan_vmmc: wlan-vmmcgrp { 593 fsl,pins = < 594 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 595 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 596 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 597 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 598 >; 599 }; 600}; 601 602&ipu1_di0_disp0 { 603 remote-endpoint = <&lcd_display_in>; 604}; 605 606&ldb { 607 status = "okay"; 608 609 lvds-channel@0 { 610 status = "okay"; 611 612 port@4 { 613 reg = <4>; 614 615 lvds0_out: endpoint { 616 remote-endpoint = <&panel_in_lvds0>; 617 }; 618 }; 619 }; 620 621 lvds-channel@1 { 622 fsl,data-mapping = "spwg"; 623 fsl,data-width = <18>; 624 status = "okay"; 625 626 port@4 { 627 reg = <4>; 628 629 lvds1_out: endpoint { 630 remote-endpoint = <&panel_in_lvds1>; 631 }; 632 }; 633 }; 634}; 635 636&pcie { 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_pcie>; 639 reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; 640 status = "okay"; 641}; 642 643&pwm1 { 644 #pwm-cells = <2>; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pinctrl_pwm1>; 647 status = "okay"; 648}; 649 650&pwm3 { 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_pwm3>; 653 status = "okay"; 654}; 655 656&pwm4 { 657 #pwm-cells = <2>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&pinctrl_pwm4>; 660 status = "okay"; 661}; 662 663&ssi1 { 664 status = "okay"; 665}; 666 667&uart1 { 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_uart1>; 670 status = "okay"; 671}; 672 673&uart2 { 674 pinctrl-names = "default"; 675 pinctrl-0 = <&pinctrl_uart2>; 676 status = "okay"; 677}; 678 679&uart3 { 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_uart3>; 682 uart-has-rtscts; 683 status = "okay"; 684}; 685 686&usbh1 { 687 vbus-supply = <®_usb_h1_vbus>; 688 status = "okay"; 689}; 690 691&usbotg { 692 vbus-supply = <®_usb_otg_vbus>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_usbotg>; 695 disable-over-current; 696 status = "okay"; 697}; 698 699&usdhc2 { 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_usdhc2>; 702 bus-width = <4>; 703 non-removable; 704 vmmc-supply = <®_wlan_vmmc>; 705 cap-power-off-card; 706 keep-power-in-suspend; 707 status = "okay"; 708 709 #address-cells = <1>; 710 #size-cells = <0>; 711 wlcore: wlcore@2 { 712 compatible = "ti,wl1271"; 713 reg = <2>; 714 interrupt-parent = <&gpio6>; 715 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 716 ref-clock-frequency = <38400000>; 717 }; 718}; 719 720&usdhc3 { 721 pinctrl-names = "default"; 722 pinctrl-0 = <&pinctrl_usdhc3>; 723 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 724 bus-width = <4>; 725 vmmc-supply = <®_3p3v>; 726 status = "okay"; 727}; 728 729&usdhc4 { 730 pinctrl-names = "default"; 731 pinctrl-0 = <&pinctrl_usdhc4>; 732 bus-width = <8>; 733 non-removable; 734 vmmc-supply = <®_1p8v>; 735 keep-power-in-suspend; 736 status = "okay"; 737}; 738