1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2012 Armadeus Systems - <support@armadeus.com> 4 * Copyright 2012 Laurent Cans <laurent.cans@gmail.com> 5 * 6 * Based on mx51-babbage.dts 7 * Copyright 2011 Freescale Semiconductor, Inc. 8 * Copyright 2011 Linaro Ltd. 9 */ 10 11/dts-v1/; 12#include "imx51.dtsi" 13 14/ { 15 model = "Armadeus Systems APF51 module"; 16 compatible = "armadeus,imx51-apf51", "fsl,imx51"; 17 18 memory@90000000 { 19 device_type = "memory"; 20 reg = <0x90000000 0x20000000>; 21 }; 22 23 clocks { 24 osc { 25 clock-frequency = <33554432>; 26 }; 27 }; 28}; 29 30&fec { 31 pinctrl-names = "default"; 32 pinctrl-0 = <&pinctrl_fec>; 33 phy-mode = "mii"; 34 phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 35 phy-reset-duration = <1>; 36 status = "okay"; 37}; 38 39&iomuxc { 40 imx51-apf51 { 41 pinctrl_fec: fecgrp { 42 fsl,pins = < 43 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 44 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 45 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 46 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 47 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 48 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 49 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 50 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 51 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 52 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 53 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 54 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 55 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 56 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 57 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 58 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 59 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 60 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 61 >; 62 }; 63 64 pinctrl_uart3: uart3grp { 65 fsl,pins = < 66 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 67 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 68 >; 69 }; 70 }; 71}; 72 73&nfc { 74 nand-bus-width = <8>; 75 nand-ecc-mode = "hw"; 76 nand-on-flash-bbt; 77 status = "okay"; 78}; 79 80&uart3 { 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_uart3>; 83 status = "okay"; 84}; 85