xref: /freebsd/sys/contrib/device-tree/src/arm/nvidia/tegra20-acer-a500-picasso.dts (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/atmel-maxtouch.h>
5#include <dt-bindings/input/gpio-keys.h>
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/thermal/thermal.h>
8
9#include "tegra20.dtsi"
10#include "tegra20-cpu-opp.dtsi"
11#include "tegra20-cpu-opp-microvolt.dtsi"
12
13/ {
14	model = "Acer Iconia Tab A500";
15	compatible = "acer,picasso", "nvidia,tegra20";
16
17	aliases {
18		mmc0 = &sdmmc4; /* eMMC */
19		mmc1 = &sdmmc3; /* MicroSD */
20		mmc2 = &sdmmc1; /* WiFi */
21
22		rtc0 = &pmic;
23		rtc1 = "/rtc@7000e000";
24
25		serial0 = &uartd; /* Docking station */
26		serial1 = &uartc; /* Bluetooth */
27		serial2 = &uartb; /* GPS */
28	};
29
30	/*
31	 * The decompressor and also some bootloaders rely on a
32	 * pre-existing /chosen node to be available to insert the
33	 * command line and merge other ATAGS info.
34	 */
35	chosen {};
36
37	memory@0 {
38		reg = <0x00000000 0x40000000>;
39	};
40
41	reserved-memory {
42		#address-cells = <1>;
43		#size-cells = <1>;
44		ranges;
45
46		ramoops@2ffe0000 {
47			compatible = "ramoops";
48			reg = <0x2ffe0000 0x10000>;	/* 64kB */
49			console-size = <0x8000>;	/* 32kB */
50			record-size = <0x400>;		/*  1kB */
51			ecc-size = <16>;
52		};
53
54		linux,cma@30000000 {
55			compatible = "shared-dma-pool";
56			alloc-ranges = <0x30000000 0x10000000>;
57			size = <0x10000000>; /* 256MiB */
58			linux,cma-default;
59			reusable;
60		};
61	};
62
63	host1x@50000000 {
64		dc@54200000 {
65			rgb {
66				status = "okay";
67
68				port@0 {
69					lcd_output: endpoint {
70						remote-endpoint = <&lvds_encoder_input>;
71						bus-width = <18>;
72					};
73				};
74			};
75		};
76
77		hdmi@54280000 {
78			status = "okay";
79
80			vdd-supply = <&hdmi_vdd_reg>;
81			pll-supply = <&hdmi_pll_reg>;
82			hdmi-supply = <&vdd_5v0_sys>;
83
84			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
85			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
86				GPIO_ACTIVE_HIGH>;
87		};
88	};
89
90	pinmux@70000014 {
91		pinctrl-names = "default";
92		pinctrl-0 = <&state_default>;
93
94		state_default: pinmux {
95			ata {
96				nvidia,pins = "ata";
97				nvidia,function = "ide";
98			};
99			atb {
100				nvidia,pins = "atb", "gma", "gme";
101				nvidia,function = "sdio4";
102			};
103			atc {
104				nvidia,pins = "atc";
105				nvidia,function = "nand";
106			};
107			atd {
108				nvidia,pins = "atd", "ate", "gmb", "spia",
109					"spib", "spic";
110				nvidia,function = "gmi";
111			};
112			cdev1 {
113				nvidia,pins = "cdev1";
114				nvidia,function = "plla_out";
115			};
116			cdev2 {
117				nvidia,pins = "cdev2";
118				nvidia,function = "pllp_out4";
119			};
120			crtp {
121				nvidia,pins = "crtp", "lm1";
122				nvidia,function = "crt";
123			};
124			csus {
125				nvidia,pins = "csus";
126				nvidia,function = "vi_sensor_clk";
127			};
128			dap1 {
129				nvidia,pins = "dap1";
130				nvidia,function = "dap1";
131			};
132			dap2 {
133				nvidia,pins = "dap2";
134				nvidia,function = "dap2";
135			};
136			dap3 {
137				nvidia,pins = "dap3";
138				nvidia,function = "dap3";
139			};
140			dap4 {
141				nvidia,pins = "dap4";
142				nvidia,function = "dap4";
143			};
144			dta {
145				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
146				nvidia,function = "vi";
147			};
148			dtf {
149				nvidia,pins = "dtf";
150				nvidia,function = "i2c3";
151			};
152			gmc {
153				nvidia,pins = "gmc";
154				nvidia,function = "uartd";
155			};
156			gmd {
157				nvidia,pins = "gmd";
158				nvidia,function = "sflash";
159			};
160			gpu {
161				nvidia,pins = "gpu";
162				nvidia,function = "pwm";
163			};
164			gpu7 {
165				nvidia,pins = "gpu7";
166				nvidia,function = "rtck";
167			};
168			gpv {
169				nvidia,pins = "gpv", "slxa";
170				nvidia,function = "pcie";
171			};
172			hdint {
173				nvidia,pins = "hdint";
174				nvidia,function = "hdmi";
175			};
176			i2cp {
177				nvidia,pins = "i2cp";
178				nvidia,function = "i2cp";
179			};
180			irrx {
181				nvidia,pins = "irrx", "irtx";
182				nvidia,function = "uartb";
183			};
184			kbca {
185				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
186					"kbce", "kbcf";
187				nvidia,function = "kbc";
188			};
189			lcsn {
190				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
191					"lsdi", "lvp0";
192				nvidia,function = "rsvd4";
193			};
194			ld0 {
195				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
196					"ld5", "ld6", "ld7", "ld8", "ld9",
197					"ld10", "ld11", "ld12", "ld13", "ld14",
198					"ld15", "ld16", "ld17", "ldi", "lhp0",
199					"lhp1", "lhp2", "lhs", "lpp", "lsc0",
200					"lsc1", "lsck", "lsda", "lspi", "lvp1",
201					"lvs";
202				nvidia,function = "displaya";
203			};
204			owc {
205				nvidia,pins = "owc", "spdi", "spdo", "uac";
206				nvidia,function = "rsvd2";
207			};
208			pmc {
209				nvidia,pins = "pmc";
210				nvidia,function = "pwr_on";
211			};
212			rm {
213				nvidia,pins = "rm";
214				nvidia,function = "i2c1";
215			};
216			sdb {
217				nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
218				nvidia,function = "sdio3";
219			};
220			sdio1 {
221				nvidia,pins = "sdio1";
222				nvidia,function = "sdio1";
223			};
224			slxd {
225				nvidia,pins = "slxd";
226				nvidia,function = "spdif";
227			};
228			spid {
229				nvidia,pins = "spid", "spie", "spif";
230				nvidia,function = "spi1";
231			};
232			spig {
233				nvidia,pins = "spig", "spih";
234				nvidia,function = "spi2_alt";
235			};
236			uaa {
237				nvidia,pins = "uaa", "uab", "uda";
238				nvidia,function = "ulpi";
239			};
240			uad {
241				nvidia,pins = "uad";
242				nvidia,function = "irda";
243			};
244			uca {
245				nvidia,pins = "uca", "ucb";
246				nvidia,function = "uartc";
247			};
248			conf_ata {
249				nvidia,pins = "ata", "atb", "atc", "atd",
250					"cdev1", "cdev2", "csus", "dap1",
251					"dap4", "dte", "dtf", "gma", "gmc",
252					"gme", "gpu", "gpu7", "gpv", "i2cp",
253					"irrx", "irtx", "pta", "rm",
254					"sdc", "sdd", "slxc", "slxd", "slxk",
255					"spdi", "spdo", "uac", "uad", "uda";
256				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257				nvidia,tristate = <TEGRA_PIN_DISABLE>;
258			};
259			conf_ate {
260				nvidia,pins = "ate", "dap2", "dap3",
261					"gmd", "owc", "spia", "spib", "spic",
262					"spid", "spie";
263				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264				nvidia,tristate = <TEGRA_PIN_ENABLE>;
265			};
266			conf_ck32 {
267				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
268					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
269				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
270			};
271			conf_crtp {
272				nvidia,pins = "crtp", "gmb", "slxa", "spig",
273					"spih";
274				nvidia,pull = <TEGRA_PIN_PULL_UP>;
275				nvidia,tristate = <TEGRA_PIN_ENABLE>;
276			};
277			conf_dta {
278				nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
279				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
280				nvidia,tristate = <TEGRA_PIN_DISABLE>;
281			};
282			conf_dte {
283				nvidia,pins = "spif";
284				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
285				nvidia,tristate = <TEGRA_PIN_ENABLE>;
286			};
287			conf_hdint {
288				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
289					"lpw1", "lsck", "lsda", "lsdi",
290					"lvp0";
291				nvidia,tristate = <TEGRA_PIN_ENABLE>;
292			};
293			conf_kbca {
294				nvidia,pins = "kbca", "kbcc", "kbcd",
295					"kbce", "kbcf", "sdio1", "uaa",
296					"uab", "uca", "ucb";
297				nvidia,pull = <TEGRA_PIN_PULL_UP>;
298				nvidia,tristate = <TEGRA_PIN_DISABLE>;
299			};
300			conf_lc {
301				nvidia,pins = "lc", "ls";
302				nvidia,pull = <TEGRA_PIN_PULL_UP>;
303			};
304			conf_ld0 {
305				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
306					"ld5", "ld6", "ld7", "ld8", "ld9",
307					"ld10", "ld11", "ld12", "ld13", "ld14",
308					"ld15", "ld16", "ld17", "ldi", "lhp0",
309					"lhp1", "lhp2", "lhs", "lm0", "lpp",
310					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
311					"lvp1", "lvs", "pmc", "sdb";
312				nvidia,tristate = <TEGRA_PIN_DISABLE>;
313			};
314			conf_ld17_0 {
315				nvidia,pins = "ld17_0";
316				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
317			};
318			drive_ddc {
319				nvidia,pins = "drive_ddc",
320						"drive_vi1",
321						"drive_sdio1";
322				nvidia,pull-up-strength = <31>;
323				nvidia,pull-down-strength = <31>;
324				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
325				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
326				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
327				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
329			};
330			drive_dbg {
331				nvidia,pins = "drive_dbg",
332						"drive_vi2",
333						"drive_at1",
334						"drive_ao1";
335				nvidia,pull-up-strength = <31>;
336				nvidia,pull-down-strength = <31>;
337				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
338				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
339				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
340				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
342			};
343		};
344
345		state_i2cmux_ddc: pinmux-i2cmux-ddc {
346			ddc {
347				nvidia,pins = "ddc";
348				nvidia,function = "i2c2";
349			};
350
351			pta {
352				nvidia,pins = "pta";
353				nvidia,function = "rsvd4";
354			};
355		};
356
357		state_i2cmux_idle: pinmux-i2cmux-idle {
358			ddc {
359				nvidia,pins = "ddc";
360				nvidia,function = "rsvd4";
361			};
362
363			pta {
364				nvidia,pins = "pta";
365				nvidia,function = "rsvd4";
366			};
367		};
368
369		state_i2cmux_pta: pinmux-i2cmux-pta {
370			ddc {
371				nvidia,pins = "ddc";
372				nvidia,function = "rsvd4";
373			};
374
375			pta {
376				nvidia,pins = "pta";
377				nvidia,function = "i2c2";
378			};
379		};
380	};
381
382	tegra_spdif: spdif@70002400 {
383		status = "okay";
384
385		nvidia,fixed-parent-rate;
386	};
387
388	tegra_i2s1: i2s@70002800 {
389		status = "okay";
390
391		nvidia,fixed-parent-rate;
392	};
393
394	uartb: serial@70006040 {
395		compatible = "nvidia,tegra20-hsuart";
396		/delete-property/ reg-shift;
397		/* GPS BCM4751 */
398	};
399
400	uartc: serial@70006200 {
401		compatible = "nvidia,tegra20-hsuart";
402		/delete-property/ reg-shift;
403		status = "okay";
404
405		/* Azurewave AW-NH665 BCM4329B1 */
406		bluetooth {
407			compatible = "brcm,bcm4329-bt";
408
409			interrupt-parent = <&gpio>;
410			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
411			interrupt-names = "host-wakeup";
412
413			/* PLLP 216MHz / 16 / 4 */
414			max-speed = <3375000>;
415
416			clocks = <&rtc_32k_wifi>;
417			clock-names = "txco";
418
419			vbat-supply  = <&vdd_3v3_sys>;
420			vddio-supply = <&vdd_1v8_sys>;
421
422			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
423			shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
424		};
425	};
426
427	uartd: serial@70006300 {
428		/* Docking station */
429	};
430
431	pwm: pwm@7000a000 {
432		status = "okay";
433	};
434
435	i2c@7000c000 {
436		clock-frequency = <400000>;
437		status = "okay";
438
439		wm8903: audio-codec@1a {
440			compatible = "wlf,wm8903";
441			reg = <0x1a>;
442
443			interrupt-parent = <&gpio>;
444			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
445
446			gpio-controller;
447			#gpio-cells = <2>;
448
449			micdet-cfg = <0>;
450			micdet-delay = <100>;
451
452			gpio-cfg = <
453				0x0000 /* MIC_LR_OUT#    GPIO, output, low */
454				0x0000 /* FM2018-enable  GPIO, output, low */
455				0x0000 /* Speaker-enable GPIO, output, low */
456				0x0200 /* Interrupt, output */
457				0x01a0 /* BCLK, input, active high */
458			>;
459
460			AVDD-supply  = <&vdd_1v8_sys>;
461			CPVDD-supply = <&vdd_1v8_sys>;
462			DBVDD-supply = <&vdd_1v8_sys>;
463			DCVDD-supply = <&vdd_1v8_sys>;
464		};
465
466		touchscreen@4c {
467			compatible = "atmel,maxtouch";
468			reg = <0x4c>;
469
470			interrupt-parent = <&gpio>;
471			interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
472
473			reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
474
475			vdda-supply = <&vdd_3v3_sys>;
476			vdd-supply  = <&vdd_3v3_sys>;
477
478			atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
479		};
480
481		gyroscope@68 {
482			compatible = "invensense,mpu3050";
483			reg = <0x68>;
484
485			interrupt-parent = <&gpio>;
486			interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
487
488			vdd-supply    = <&vdd_3v3_sys>;
489			vlogic-supply = <&vdd_1v8_sys>;
490
491			mount-matrix =	 "0",  "1",  "0",
492					 "1",  "0",  "0",
493					 "0",  "0", "-1";
494
495			i2c-gate {
496				#address-cells = <1>;
497				#size-cells = <0>;
498
499				accelerometer@f {
500					compatible = "kionix,kxtf9";
501					reg = <0x0f>;
502
503					interrupt-parent = <&gpio>;
504					interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
505
506					vdd-supply   = <&vdd_1v8_sys>;
507					vddio-supply = <&vdd_1v8_sys>;
508
509					mount-matrix =	 "0",  "1",  "0",
510							 "1",  "0",  "0",
511							 "0",  "0", "-1";
512				};
513			};
514		};
515	};
516
517	i2c@7000c400 {
518		clock-frequency = <10000>;
519		status = "okay";
520	};
521
522	i2c@7000d000 {
523		clock-frequency = <100000>;
524		status = "okay";
525
526		magnetometer@c {
527			compatible = "asahi-kasei,ak8975";
528			reg = <0x0c>;
529
530			interrupt-parent = <&gpio>;
531			interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
532
533			vdd-supply = <&vdd_3v3_sys>;
534			vid-supply = <&vdd_1v8_sys>;
535
536			mount-matrix =	"1",  "0",  "0",
537					"0", "-1",  "0",
538					"0",  "0", "-1";
539		};
540
541		pmic: pmic@34 {
542			compatible = "ti,tps6586x";
543			reg = <0x34>;
544
545			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
546
547			#gpio-cells = <2>;
548			gpio-controller;
549
550			sys-supply       = <&vdd_5v0_sys>;
551			vin-sm0-supply   = <&sys_reg>;
552			vin-sm1-supply   = <&sys_reg>;
553			vin-sm2-supply   = <&sys_reg>;
554			vinldo01-supply  = <&sm2_reg>;
555			vinldo23-supply  = <&sm2_reg>;
556			vinldo4-supply   = <&sm2_reg>;
557			vinldo678-supply = <&sm2_reg>;
558			vinldo9-supply   = <&sm2_reg>;
559
560			regulators {
561				sys_reg: sys {
562					regulator-name = "vdd_sys";
563					regulator-always-on;
564				};
565
566				vdd_core: sm0 {
567					regulator-name = "vdd_sm0,vdd_core";
568					regulator-min-microvolt = <950000>;
569					regulator-max-microvolt = <1300000>;
570					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
571					regulator-coupled-max-spread = <170000 550000>;
572					regulator-always-on;
573					regulator-boot-on;
574
575					nvidia,tegra-core-regulator;
576				};
577
578				vdd_cpu: sm1 {
579					regulator-name = "vdd_sm1,vdd_cpu";
580					regulator-min-microvolt = <750000>;
581					regulator-max-microvolt = <1125000>;
582					regulator-coupled-with = <&vdd_core &rtc_vdd>;
583					regulator-coupled-max-spread = <550000 550000>;
584					regulator-always-on;
585					regulator-boot-on;
586
587					nvidia,tegra-cpu-regulator;
588				};
589
590				sm2_reg: sm2 {
591					regulator-name = "vdd_sm2,vin_ldo*";
592					regulator-min-microvolt = <3700000>;
593					regulator-max-microvolt = <3700000>;
594					regulator-always-on;
595				};
596
597				/* LDO0 is not connected to anything */
598
599				ldo1 {
600					regulator-name = "vdd_ldo1,avdd_pll*";
601					regulator-min-microvolt = <1100000>;
602					regulator-max-microvolt = <1100000>;
603					regulator-always-on;
604					regulator-boot-on;
605				};
606
607				rtc_vdd: ldo2 {
608					regulator-name = "vdd_ldo2,vdd_rtc";
609					regulator-min-microvolt = <950000>;
610					regulator-max-microvolt = <1300000>;
611					regulator-coupled-with = <&vdd_core &vdd_cpu>;
612					regulator-coupled-max-spread = <170000 550000>;
613					regulator-always-on;
614					regulator-boot-on;
615
616					nvidia,tegra-rtc-regulator;
617				};
618
619				ldo3 {
620					regulator-name = "vdd_ldo3,avdd_usb*";
621					regulator-min-microvolt = <3300000>;
622					regulator-max-microvolt = <3300000>;
623					regulator-always-on;
624				};
625
626				ldo4 {
627					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
628					regulator-min-microvolt = <1800000>;
629					regulator-max-microvolt = <1800000>;
630					regulator-always-on;
631					regulator-boot-on;
632				};
633
634				vcore_emmc: ldo5 {
635					regulator-name = "vdd_ldo5,vcore_mmc";
636					regulator-min-microvolt = <2850000>;
637					regulator-max-microvolt = <2850000>;
638					regulator-always-on;
639				};
640
641				avdd_vdac_reg: ldo6 {
642					regulator-name = "vdd_ldo6,avdd_vdac";
643					regulator-min-microvolt = <2850000>;
644					regulator-max-microvolt = <2850000>;
645				};
646
647				hdmi_vdd_reg: ldo7 {
648					regulator-name = "vdd_ldo7,avdd_hdmi";
649					regulator-min-microvolt = <3300000>;
650					regulator-max-microvolt = <3300000>;
651				};
652
653				hdmi_pll_reg: ldo8 {
654					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
655					regulator-min-microvolt = <1800000>;
656					regulator-max-microvolt = <1800000>;
657				};
658
659				ldo9 {
660					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
661					regulator-min-microvolt = <2850000>;
662					regulator-max-microvolt = <2850000>;
663					regulator-always-on;
664					regulator-boot-on;
665				};
666
667				ldo_rtc {
668					regulator-name = "vdd_rtc_out,vdd_cell";
669					regulator-min-microvolt = <3300000>;
670					regulator-max-microvolt = <3300000>;
671					regulator-always-on;
672					regulator-boot-on;
673				};
674			};
675		};
676
677		nct1008: temperature-sensor@4c {
678			compatible = "onnn,nct1008";
679			reg = <0x4c>;
680			vcc-supply = <&vdd_3v3_sys>;
681
682			interrupt-parent = <&gpio>;
683			interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
684
685			#thermal-sensor-cells = <1>;
686		};
687	};
688
689	pmc@7000e400 {
690		nvidia,invert-interrupt;
691		nvidia,suspend-mode = <1>;
692		nvidia,cpu-pwr-good-time = <2000>;
693		nvidia,cpu-pwr-off-time = <100>;
694		nvidia,core-pwr-good-time = <3845 3845>;
695		nvidia,core-pwr-off-time = <458>;
696		nvidia,sys-clock-req-active-high;
697		core-supply = <&vdd_core>;
698	};
699
700	memory-controller@7000f400 {
701		nvidia,use-ram-code;
702
703		emc-tables@0 {
704			nvidia,ram-code = <0>; /* elpida-8gb */
705			reg = <0>;
706
707			#address-cells = <1>;
708			#size-cells = <0>;
709
710			emc-table@25000 {
711				reg = <25000>;
712				compatible = "nvidia,tegra20-emc-table";
713				clock-frequency = <25000>;
714				nvidia,emc-registers = <0x00000002 0x00000006
715					0x00000003 0x00000003 0x00000006 0x00000004
716					0x00000002 0x00000009 0x00000003 0x00000003
717					0x00000002 0x00000002 0x00000002 0x00000004
718					0x00000003 0x00000008 0x0000000b 0x0000004d
719					0x00000000 0x00000003 0x00000003 0x00000003
720					0x00000008 0x00000001 0x0000000a 0x00000004
721					0x00000003 0x00000008 0x00000004 0x00000006
722					0x00000002 0x00000068 0x00000000 0x00000003
723					0x00000000 0x00000000 0x00000282 0xa0ae04ae
724					0x00070000 0x00000000 0x00000000 0x00000003
725					0x00000000 0x00000000 0x00000000 0x00000000>;
726			};
727
728			emc-table@50000 {
729				reg = <50000>;
730				compatible = "nvidia,tegra20-emc-table";
731				clock-frequency = <50000>;
732				nvidia,emc-registers = <0x00000003 0x00000007
733					0x00000003 0x00000003 0x00000006 0x00000004
734					0x00000002 0x00000009 0x00000003 0x00000003
735					0x00000002 0x00000002 0x00000002 0x00000005
736					0x00000003 0x00000008 0x0000000b 0x0000009f
737					0x00000000 0x00000003 0x00000003 0x00000003
738					0x00000008 0x00000001 0x0000000a 0x00000007
739					0x00000003 0x00000008 0x00000004 0x00000006
740					0x00000002 0x000000d0 0x00000000 0x00000000
741					0x00000000 0x00000000 0x00000282 0xa0ae04ae
742					0x00070000 0x00000000 0x00000000 0x00000005
743					0x00000000 0x00000000 0x00000000 0x00000000>;
744			};
745
746			emc-table@75000 {
747				reg = <75000>;
748				compatible = "nvidia,tegra20-emc-table";
749				clock-frequency = <75000>;
750				nvidia,emc-registers = <0x00000005 0x0000000a
751					0x00000004 0x00000003 0x00000006 0x00000004
752					0x00000002 0x00000009 0x00000003 0x00000003
753					0x00000002 0x00000002 0x00000002 0x00000005
754					0x00000003 0x00000008 0x0000000b 0x000000ff
755					0x00000000 0x00000003 0x00000003 0x00000003
756					0x00000008 0x00000001 0x0000000a 0x0000000b
757					0x00000003 0x00000008 0x00000004 0x00000006
758					0x00000002 0x00000138 0x00000000 0x00000000
759					0x00000000 0x00000000 0x00000282 0xa0ae04ae
760					0x00070000 0x00000000 0x00000000 0x00000007
761					0x00000000 0x00000000 0x00000000 0x00000000>;
762			};
763
764			emc-table@150000 {
765				reg = <150000>;
766				compatible = "nvidia,tegra20-emc-table";
767				clock-frequency = <150000>;
768				nvidia,emc-registers = <0x00000009 0x00000014
769					0x00000007 0x00000003 0x00000006 0x00000004
770					0x00000002 0x00000009 0x00000003 0x00000003
771					0x00000002 0x00000002 0x00000002 0x00000005
772					0x00000003 0x00000008 0x0000000b 0x0000021f
773					0x00000000 0x00000003 0x00000003 0x00000003
774					0x00000008 0x00000001 0x0000000a 0x00000015
775					0x00000003 0x00000008 0x00000004 0x00000006
776					0x00000002 0x00000270 0x00000000 0x00000001
777					0x00000000 0x00000000 0x00000282 0xa07c04ae
778					0x007dd510 0x00000000 0x00000000 0x0000000e
779					0x00000000 0x00000000 0x00000000 0x00000000>;
780			};
781
782			emc-table@300000 {
783				reg = <300000>;
784				compatible = "nvidia,tegra20-emc-table";
785				clock-frequency = <300000>;
786				nvidia,emc-registers = <0x00000012 0x00000027
787					0x0000000d 0x00000006 0x00000007 0x00000005
788					0x00000003 0x00000009 0x00000006 0x00000006
789					0x00000003 0x00000003 0x00000002 0x00000006
790					0x00000003 0x00000009 0x0000000c 0x0000045f
791					0x00000000 0x00000004 0x00000004 0x00000006
792					0x00000008 0x00000001 0x0000000e 0x0000002a
793					0x00000003 0x0000000f 0x00000007 0x00000005
794					0x00000002 0x000004e1 0x00000005 0x00000002
795					0x00000000 0x00000000 0x00000282 0xe059048b
796					0x007e1510 0x00000000 0x00000000 0x0000001b
797					0x00000000 0x00000000 0x00000000 0x00000000>;
798			};
799		};
800
801		emc-tables@1 {
802			nvidia,ram-code = <1>; /* elpida-4gb */
803			reg = <1>;
804
805			#address-cells = <1>;
806			#size-cells = <0>;
807
808			emc-table@25000 {
809				reg = <25000>;
810				compatible = "nvidia,tegra20-emc-table";
811				clock-frequency = <25000>;
812				nvidia,emc-registers = <0x00000002 0x00000006
813					0x00000003 0x00000003 0x00000006 0x00000004
814					0x00000002 0x00000009 0x00000003 0x00000003
815					0x00000002 0x00000002 0x00000002 0x00000004
816					0x00000003 0x00000008 0x0000000b 0x0000004d
817					0x00000000 0x00000003 0x00000003 0x00000003
818					0x00000008 0x00000001 0x0000000a 0x00000004
819					0x00000003 0x00000008 0x00000004 0x00000006
820					0x00000002 0x00000068 0x00000000 0x00000003
821					0x00000000 0x00000000 0x00000282 0xa0ae04ae
822					0x0007c000 0x00000000 0x00000000 0x00000003
823					0x00000000 0x00000000 0x00000000 0x00000000>;
824			};
825
826			emc-table@50000 {
827				reg = <50000>;
828				compatible = "nvidia,tegra20-emc-table";
829				clock-frequency = <50000>;
830				nvidia,emc-registers = <0x00000003 0x00000007
831					0x00000003 0x00000003 0x00000006 0x00000004
832					0x00000002 0x00000009 0x00000003 0x00000003
833					0x00000002 0x00000002 0x00000002 0x00000005
834					0x00000003 0x00000008 0x0000000b 0x0000009f
835					0x00000000 0x00000003 0x00000003 0x00000003
836					0x00000008 0x00000001 0x0000000a 0x00000007
837					0x00000003 0x00000008 0x00000004 0x00000006
838					0x00000002 0x000000d0 0x00000000 0x00000000
839					0x00000000 0x00000000 0x00000282 0xa0ae04ae
840					0x0007c000 0x00000000 0x00000000 0x00000005
841					0x00000000 0x00000000 0x00000000 0x00000000>;
842			};
843
844			emc-table@75000 {
845				reg = <75000>;
846				compatible = "nvidia,tegra20-emc-table";
847				clock-frequency = <75000>;
848				nvidia,emc-registers = <0x00000005 0x0000000a
849					0x00000004 0x00000003 0x00000006 0x00000004
850					0x00000002 0x00000009 0x00000003 0x00000003
851					0x00000002 0x00000002 0x00000002 0x00000005
852					0x00000003 0x00000008 0x0000000b 0x000000ff
853					0x00000000 0x00000003 0x00000003 0x00000003
854					0x00000008 0x00000001 0x0000000a 0x0000000b
855					0x00000003 0x00000008 0x00000004 0x00000006
856					0x00000002 0x00000138 0x00000000 0x00000000
857					0x00000000 0x00000000 0x00000282 0xa0ae04ae
858					0x0007c000 0x00000000 0x00000000 0x00000007
859					0x00000000 0x00000000 0x00000000 0x00000000>;
860			};
861
862			emc-table@150000 {
863				reg = <150000>;
864				compatible = "nvidia,tegra20-emc-table";
865				clock-frequency = <150000>;
866				nvidia,emc-registers = <0x00000009 0x00000014
867					0x00000007 0x00000003 0x00000006 0x00000004
868					0x00000002 0x00000009 0x00000003 0x00000003
869					0x00000002 0x00000002 0x00000002 0x00000005
870					0x00000003 0x00000008 0x0000000b 0x0000021f
871					0x00000000 0x00000003 0x00000003 0x00000003
872					0x00000008 0x00000001 0x0000000a 0x00000015
873					0x00000003 0x00000008 0x00000004 0x00000006
874					0x00000002 0x00000270 0x00000000 0x00000001
875					0x00000000 0x00000000 0x00000282 0xa07c04ae
876					0x007e4010 0x00000000 0x00000000 0x0000000e
877					0x00000000 0x00000000 0x00000000 0x00000000>;
878			};
879
880			emc-table@300000 {
881				reg = <300000>;
882				compatible = "nvidia,tegra20-emc-table";
883				clock-frequency = <300000>;
884				nvidia,emc-registers = <0x00000012 0x00000027
885					0x0000000d 0x00000006 0x00000007 0x00000005
886					0x00000003 0x00000009 0x00000006 0x00000006
887					0x00000003 0x00000003 0x00000002 0x00000006
888					0x00000003 0x00000009 0x0000000c 0x0000045f
889					0x00000000 0x00000004 0x00000004 0x00000006
890					0x00000008 0x00000001 0x0000000e 0x0000002a
891					0x00000003 0x0000000f 0x00000007 0x00000005
892					0x00000002 0x000004e1 0x00000005 0x00000002
893					0x00000000 0x00000000 0x00000282 0xe059048b
894					0x007e0010 0x00000000 0x00000000 0x0000001b
895					0x00000000 0x00000000 0x00000000 0x00000000>;
896			};
897		};
898
899		emc-tables@2 {
900			nvidia,ram-code = <2>; /* hynix-8gb */
901			reg = <2>;
902
903			#address-cells = <1>;
904			#size-cells = <0>;
905
906			emc-table@25000 {
907				reg = <25000>;
908				compatible = "nvidia,tegra20-emc-table";
909				clock-frequency = <25000>;
910				nvidia,emc-registers = <0x00000002 0x00000006
911					0x00000003 0x00000003 0x00000006 0x00000004
912					0x00000002 0x00000009 0x00000003 0x00000003
913					0x00000002 0x00000002 0x00000002 0x00000004
914					0x00000003 0x00000008 0x0000000b 0x0000004d
915					0x00000000 0x00000003 0x00000003 0x00000003
916					0x00000008 0x00000001 0x0000000a 0x00000004
917					0x00000003 0x00000008 0x00000004 0x00000006
918					0x00000002 0x00000068 0x00000000 0x00000003
919					0x00000000 0x00000000 0x00000282 0xa0ae04ae
920					0x00070000 0x00000000 0x00000000 0x00000003
921					0x00000000 0x00000000 0x00000000 0x00000000>;
922			};
923
924			emc-table@50000 {
925				reg = <50000>;
926				compatible = "nvidia,tegra20-emc-table";
927				clock-frequency = <50000>;
928				nvidia,emc-registers = <0x00000003 0x00000007
929					0x00000003 0x00000003 0x00000006 0x00000004
930					0x00000002 0x00000009 0x00000003 0x00000003
931					0x00000002 0x00000002 0x00000002 0x00000005
932					0x00000003 0x00000008 0x0000000b 0x0000009f
933					0x00000000 0x00000003 0x00000003 0x00000003
934					0x00000008 0x00000001 0x0000000a 0x00000007
935					0x00000003 0x00000008 0x00000004 0x00000006
936					0x00000002 0x000000d0 0x00000000 0x00000000
937					0x00000000 0x00000000 0x00000282 0xa0ae04ae
938					0x00070000 0x00000000 0x00000000 0x00000005
939					0x00000000 0x00000000 0x00000000 0x00000000>;
940			};
941
942			emc-table@75000 {
943				reg = <75000>;
944				compatible = "nvidia,tegra20-emc-table";
945				clock-frequency = <75000>;
946				nvidia,emc-registers = <0x00000005 0x0000000a
947					0x00000004 0x00000003 0x00000006 0x00000004
948					0x00000002 0x00000009 0x00000003 0x00000003
949					0x00000002 0x00000002 0x00000002 0x00000005
950					0x00000003 0x00000008 0x0000000b 0x000000ff
951					0x00000000 0x00000003 0x00000003 0x00000003
952					0x00000008 0x00000001 0x0000000a 0x0000000b
953					0x00000003 0x00000008 0x00000004 0x00000006
954					0x00000002 0x00000138 0x00000000 0x00000000
955					0x00000000 0x00000000 0x00000282 0xa0ae04ae
956					0x00070000 0x00000000 0x00000000 0x00000007
957					0x00000000 0x00000000 0x00000000 0x00000000>;
958			};
959
960			emc-table@150000 {
961				reg = <150000>;
962				compatible = "nvidia,tegra20-emc-table";
963				clock-frequency = <150000>;
964				nvidia,emc-registers = <0x00000009 0x00000014
965					0x00000007 0x00000003 0x00000006 0x00000004
966					0x00000002 0x00000009 0x00000003 0x00000003
967					0x00000002 0x00000002 0x00000002 0x00000005
968					0x00000003 0x00000008 0x0000000b 0x0000021f
969					0x00000000 0x00000003 0x00000003 0x00000003
970					0x00000008 0x00000001 0x0000000a 0x00000015
971					0x00000003 0x00000008 0x00000004 0x00000006
972					0x00000002 0x00000270 0x00000000 0x00000001
973					0x00000000 0x00000000 0x00000282 0xa07c04ae
974					0x007dd010 0x00000000 0x00000000 0x0000000e
975					0x00000000 0x00000000 0x00000000 0x00000000>;
976			};
977
978			emc-table@300000 {
979				reg = <300000>;
980				compatible = "nvidia,tegra20-emc-table";
981				clock-frequency = <300000>;
982				nvidia,emc-registers = <0x00000012 0x00000027
983					0x0000000d 0x00000006 0x00000007 0x00000005
984					0x00000003 0x00000009 0x00000006 0x00000006
985					0x00000003 0x00000003 0x00000002 0x00000006
986					0x00000003 0x00000009 0x0000000c 0x0000045f
987					0x00000000 0x00000004 0x00000004 0x00000006
988					0x00000008 0x00000001 0x0000000e 0x0000002a
989					0x00000003 0x0000000f 0x00000007 0x00000005
990					0x00000002 0x000004e1 0x00000005 0x00000002
991					0x00000000 0x00000000 0x00000282 0xe059048b
992					0x007e2010 0x00000000 0x00000000 0x0000001b
993					0x00000000 0x00000000 0x00000000 0x00000000>;
994			};
995		};
996
997		emc-tables@3 {
998			nvidia,ram-code = <3>; /* hynix-4gb */
999			reg = <3>;
1000
1001			#address-cells = <1>;
1002			#size-cells = <0>;
1003
1004			emc-table@25000 {
1005				reg = <25000>;
1006				compatible = "nvidia,tegra20-emc-table";
1007				clock-frequency = <25000>;
1008				nvidia,emc-registers = <0x00000002 0x00000006
1009					0x00000003 0x00000003 0x00000006 0x00000004
1010					0x00000002 0x00000009 0x00000003 0x00000003
1011					0x00000002 0x00000002 0x00000002 0x00000004
1012					0x00000003 0x00000008 0x0000000b 0x0000004d
1013					0x00000000 0x00000003 0x00000003 0x00000003
1014					0x00000008 0x00000001 0x0000000a 0x00000004
1015					0x00000003 0x00000008 0x00000004 0x00000006
1016					0x00000002 0x00000068 0x00000000 0x00000003
1017					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1018					0x0007c000 0x00000000 0x00000000 0x00000003
1019					0x00000000 0x00000000 0x00000000 0x00000000>;
1020			};
1021
1022			emc-table@50000 {
1023				reg = <50000>;
1024				compatible = "nvidia,tegra20-emc-table";
1025				clock-frequency = <50000>;
1026				nvidia,emc-registers = <0x00000003 0x00000007
1027					0x00000003 0x00000003 0x00000006 0x00000004
1028					0x00000002 0x00000009 0x00000003 0x00000003
1029					0x00000002 0x00000002 0x00000002 0x00000005
1030					0x00000003 0x00000008 0x0000000b 0x0000009f
1031					0x00000000 0x00000003 0x00000003 0x00000003
1032					0x00000008 0x00000001 0x0000000a 0x00000007
1033					0x00000003 0x00000008 0x00000004 0x00000006
1034					0x00000002 0x000000d0 0x00000000 0x00000000
1035					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1036					0x0007c000 0x00078000 0x00000000 0x00000005
1037					0x00000000 0x00000000 0x00000000 0x00000000>;
1038			};
1039
1040			emc-table@75000 {
1041				reg = <75000>;
1042				compatible = "nvidia,tegra20-emc-table";
1043				clock-frequency = <75000>;
1044				nvidia,emc-registers = <0x00000005 0x0000000a
1045					0x00000004 0x00000003 0x00000006 0x00000004
1046					0x00000002 0x00000009 0x00000003 0x00000003
1047					0x00000002 0x00000002 0x00000002 0x00000005
1048					0x00000003 0x00000008 0x0000000b 0x000000ff
1049					0x00000000 0x00000003 0x00000003 0x00000003
1050					0x00000008 0x00000001 0x0000000a 0x0000000b
1051					0x00000003 0x00000008 0x00000004 0x00000006
1052					0x00000002 0x00000138 0x00000000 0x00000000
1053					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1054					0x0007c000 0x00000000 0x00000000 0x00000007
1055					0x00000000 0x00000000 0x00000000 0x00000000>;
1056			};
1057
1058			emc-table@150000 {
1059				reg = <150000>;
1060				compatible = "nvidia,tegra20-emc-table";
1061				clock-frequency = <150000>;
1062				nvidia,emc-registers = <0x00000009 0x00000014
1063					0x00000007 0x00000003 0x00000006 0x00000004
1064					0x00000002 0x00000009 0x00000003 0x00000003
1065					0x00000002 0x00000002 0x00000002 0x00000005
1066					0x00000003 0x00000008 0x0000000b 0x0000021f
1067					0x00000000 0x00000003 0x00000003 0x00000003
1068					0x00000008 0x00000001 0x0000000a 0x00000015
1069					0x00000003 0x00000008 0x00000004 0x00000006
1070					0x00000002 0x00000270 0x00000000 0x00000001
1071					0x00000000 0x00000000 0x00000282 0xa07c04ae
1072					0x007e4010 0x00000000 0x00000000 0x0000000e
1073					0x00000000 0x00000000 0x00000000 0x00000000>;
1074			};
1075
1076			emc-table@300000 {
1077				reg = <300000>;
1078				compatible = "nvidia,tegra20-emc-table";
1079				clock-frequency = <300000>;
1080				nvidia,emc-registers = <0x00000012 0x00000027
1081					0x0000000d 0x00000006 0x00000007 0x00000005
1082					0x00000003 0x00000009 0x00000006 0x00000006
1083					0x00000003 0x00000003 0x00000002 0x00000006
1084					0x00000003 0x00000009 0x0000000c 0x0000045f
1085					0x00000000 0x00000004 0x00000004 0x00000006
1086					0x00000008 0x00000001 0x0000000e 0x0000002a
1087					0x00000003 0x0000000f 0x00000007 0x00000005
1088					0x00000002 0x000004e1 0x00000005 0x00000002
1089					0x00000000 0x00000000 0x00000282 0xe059048b
1090					0x007e0010 0x00000000 0x00000000 0x0000001b
1091					0x00000000 0x00000000 0x00000000 0x00000000>;
1092			};
1093		};
1094	};
1095
1096	usb@c5000000 {
1097		compatible = "nvidia,tegra20-udc";
1098		status = "okay";
1099		dr_mode = "peripheral";
1100	};
1101
1102	usb-phy@c5000000 {
1103		status = "okay";
1104		dr_mode = "peripheral";
1105		nvidia,xcvr-setup-use-fuses;
1106		nvidia,xcvr-lsfslew = <2>;
1107		nvidia,xcvr-lsrslew = <2>;
1108	};
1109
1110	usb@c5008000 {
1111		status = "okay";
1112	};
1113
1114	usb-phy@c5008000 {
1115		status = "okay";
1116		nvidia,xcvr-setup-use-fuses;
1117		nvidia,xcvr-lsfslew = <2>;
1118		nvidia,xcvr-lsrslew = <2>;
1119		vbus-supply = <&vdd_5v0_sys>;
1120	};
1121
1122	sdmmc1: mmc@c8000000 {
1123		status = "okay";
1124
1125		#address-cells = <1>;
1126		#size-cells = <0>;
1127
1128		assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
1129		assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
1130		assigned-clock-rates = <50000000>;
1131
1132		max-frequency = <50000000>;
1133		keep-power-in-suspend;
1134		bus-width = <4>;
1135		non-removable;
1136
1137		mmc-pwrseq = <&brcm_wifi_pwrseq>;
1138		vmmc-supply = <&vdd_3v3_sys>;
1139		vqmmc-supply = <&vdd_1v8_sys>;
1140
1141		/* Azurewave AW-NH611 BCM4329 */
1142		wifi@1 {
1143			reg = <1>;
1144			compatible = "brcm,bcm4329-fmac";
1145			interrupt-parent = <&gpio>;
1146			interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
1147			interrupt-names = "host-wake";
1148		};
1149	};
1150
1151	sdmmc3: mmc@c8000400 {
1152		status = "okay";
1153		bus-width = <4>;
1154		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1155		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
1156		vmmc-supply = <&vdd_3v3_sys>;
1157		vqmmc-supply = <&vdd_3v3_sys>;
1158	};
1159
1160	sdmmc4: mmc@c8000600 {
1161		status = "okay";
1162		bus-width = <8>;
1163		vmmc-supply = <&vcore_emmc>;
1164		vqmmc-supply = <&vdd_3v3_sys>;
1165		non-removable;
1166	};
1167
1168	mains: ac-adapter-detect {
1169		compatible = "gpio-charger";
1170		charger-type = "mains";
1171		gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
1172	};
1173
1174	backlight: backlight {
1175		compatible = "pwm-backlight";
1176
1177		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
1178		power-supply = <&vdd_3v3_sys>;
1179		pwms = <&pwm 2 41667>;
1180
1181		brightness-levels = <7 255>;
1182		num-interpolated-steps = <248>;
1183		default-brightness-level = <20>;
1184	};
1185
1186	bat1010: battery-2s1p {
1187		compatible = "simple-battery";
1188		charge-full-design-microamp-hours = <3260000>;
1189		energy-full-design-microwatt-hours = <24000000>;
1190		operating-range-celsius = <0 40>;
1191	};
1192
1193	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
1194	clk32k_in: clock-32k-in {
1195		compatible = "fixed-clock";
1196		#clock-cells = <0>;
1197		clock-frequency = <32768>;
1198		clock-output-names = "tps658621-out32k";
1199	};
1200
1201	/*
1202	 * This standalone onboard fixed-clock always-ON 32KHz
1203	 * oscillator is used as a reference clock-source by the
1204	 * Azurewave WiFi/BT module.
1205	 */
1206	rtc_32k_wifi: clock-32k-wifi {
1207		compatible = "fixed-clock";
1208		#clock-cells = <0>;
1209		clock-frequency = <32768>;
1210		clock-output-names = "kk3270032";
1211	};
1212
1213	cpus {
1214		cpu0: cpu@0 {
1215			cpu-supply = <&vdd_cpu>;
1216			operating-points-v2 = <&cpu0_opp_table>;
1217			#cooling-cells = <2>;
1218		};
1219
1220		cpu1: cpu@1 {
1221			cpu-supply = <&vdd_cpu>;
1222			operating-points-v2 = <&cpu0_opp_table>;
1223			#cooling-cells = <2>;
1224		};
1225	};
1226
1227	display-panel {
1228		compatible = "auo,b101ew05", "panel-lvds";
1229
1230		ddc-i2c-bus = <&panel_ddc>;
1231		power-supply = <&vdd_pnl>;
1232		backlight = <&backlight>;
1233
1234		width-mm = <218>;
1235		height-mm = <135>;
1236
1237		data-mapping = "jeida-18";
1238
1239		panel-timing {
1240			clock-frequency = <71200000>;
1241			hactive = <1280>;
1242			vactive = <800>;
1243			hfront-porch = <8>;
1244			hback-porch = <18>;
1245			hsync-len = <184>;
1246			vsync-len = <3>;
1247			vfront-porch = <4>;
1248			vback-porch = <8>;
1249		};
1250
1251		port {
1252			panel_input: endpoint {
1253				remote-endpoint = <&lvds_encoder_output>;
1254			};
1255		};
1256	};
1257
1258	gpio-keys {
1259		compatible = "gpio-keys";
1260
1261		key-power {
1262			label = "Power";
1263			gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
1264			linux,code = <KEY_POWER>;
1265			debounce-interval = <10>;
1266			wakeup-event-action = <EV_ACT_ASSERTED>;
1267			wakeup-source;
1268		};
1269
1270		key-rotation-lock {
1271			label = "Rotate-lock";
1272			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
1273			linux,code = <SW_ROTATE_LOCK>;
1274			linux,input-type = <EV_SW>;
1275			debounce-interval = <10>;
1276		};
1277
1278		key-volume-down {
1279			label = "Volume Down";
1280			gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
1281			linux,code = <KEY_VOLUMEDOWN>;
1282			debounce-interval = <10>;
1283			wakeup-event-action = <EV_ACT_ASSERTED>;
1284			wakeup-source;
1285		};
1286
1287		key-volume-up {
1288			label = "Volume Up";
1289			gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
1290			linux,code = <KEY_VOLUMEUP>;
1291			debounce-interval = <10>;
1292			wakeup-event-action = <EV_ACT_ASSERTED>;
1293			wakeup-source;
1294		};
1295	};
1296
1297	haptic-feedback {
1298		compatible = "gpio-vibrator";
1299		enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
1300		vcc-supply = <&vdd_3v3_sys>;
1301	};
1302
1303	i2cmux {
1304		compatible = "i2c-mux-pinctrl";
1305		#address-cells = <1>;
1306		#size-cells = <0>;
1307
1308		i2c-parent = <&{/i2c@7000c400}>;
1309
1310		pinctrl-names = "ddc", "pta", "idle";
1311		pinctrl-0 = <&state_i2cmux_ddc>;
1312		pinctrl-1 = <&state_i2cmux_pta>;
1313		pinctrl-2 = <&state_i2cmux_idle>;
1314
1315		hdmi_ddc: i2c@0 {
1316			reg = <0>;
1317			#address-cells = <1>;
1318			#size-cells = <0>;
1319		};
1320
1321		panel_ddc: i2c@1 {
1322			reg = <1>;
1323			#address-cells = <1>;
1324			#size-cells = <0>;
1325
1326			embedded-controller@58 {
1327				compatible = "acer,a500-iconia-ec", "ene,kb930";
1328				reg = <0x58>;
1329
1330				system-power-controller;
1331
1332				monitored-battery = <&bat1010>;
1333				power-supplies = <&mains>;
1334			};
1335		};
1336	};
1337
1338	lvds-encoder {
1339		compatible = "ti,sn75lvds83", "lvds-encoder";
1340
1341		powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
1342		power-supply = <&vdd_3v3_sys>;
1343
1344		ports {
1345			#address-cells = <1>;
1346			#size-cells = <0>;
1347
1348			port@0 {
1349				reg = <0>;
1350
1351				lvds_encoder_input: endpoint {
1352					remote-endpoint = <&lcd_output>;
1353				};
1354			};
1355
1356			port@1 {
1357				reg = <1>;
1358
1359				lvds_encoder_output: endpoint {
1360					remote-endpoint = <&panel_input>;
1361				};
1362			};
1363		};
1364	};
1365
1366	opp-table-emc {
1367		/delete-node/ opp-666000000;
1368		/delete-node/ opp-760000000;
1369	};
1370
1371	vdd_5v0_sys: regulator-5v0 {
1372		compatible = "regulator-fixed";
1373		regulator-name = "vdd_5v0";
1374		regulator-min-microvolt = <5000000>;
1375		regulator-max-microvolt = <5000000>;
1376		regulator-always-on;
1377	};
1378
1379	vdd_3v3_sys: regulator-3v3 {
1380		compatible = "regulator-fixed";
1381		regulator-name = "vdd_3v3_vs";
1382		regulator-min-microvolt = <3300000>;
1383		regulator-max-microvolt = <3300000>;
1384		regulator-always-on;
1385		vin-supply = <&vdd_5v0_sys>;
1386	};
1387
1388	vdd_1v8_sys: regulator-1v8 {
1389		compatible = "regulator-fixed";
1390		regulator-name = "vdd_1v8_vs";
1391		regulator-min-microvolt = <1800000>;
1392		regulator-max-microvolt = <1800000>;
1393		regulator-always-on;
1394		vin-supply = <&vdd_5v0_sys>;
1395	};
1396
1397	vdd_pnl: regulator-panel {
1398		compatible = "regulator-fixed";
1399		regulator-name = "vdd_panel";
1400		regulator-min-microvolt = <3300000>;
1401		regulator-max-microvolt = <3300000>;
1402		regulator-enable-ramp-delay = <300000>;
1403		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
1404		enable-active-high;
1405		vin-supply = <&vdd_5v0_sys>;
1406	};
1407
1408	sound {
1409		compatible = "nvidia,tegra-audio-wm8903-picasso",
1410			     "nvidia,tegra-audio-wm8903";
1411		nvidia,model = "Acer Iconia Tab A500 WM8903";
1412
1413		nvidia,audio-routing =
1414			"Headphone Jack", "HPOUTR",
1415			"Headphone Jack", "HPOUTL",
1416			"Int Spk", "LINEOUTL",
1417			"Int Spk", "LINEOUTR",
1418			"Mic Jack", "MICBIAS",
1419			"IN2L", "Mic Jack",
1420			"IN2R", "Mic Jack",
1421			"IN1L", "Int Mic",
1422			"IN1R", "Int Mic";
1423
1424		nvidia,i2s-controller = <&tegra_i2s1>;
1425		nvidia,audio-codec = <&wm8903>;
1426
1427		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
1428		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1429		nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1430		nvidia,headset;
1431
1432		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1433			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1434			 <&tegra_car TEGRA20_CLK_CDEV1>;
1435		clock-names = "pll_a", "pll_a_out0", "mclk";
1436	};
1437
1438	thermal-zones {
1439		/*
1440		 * NCT1008 has two sensors:
1441		 *
1442		 *	0: internal that monitors ambient/skin temperature
1443		 *	1: external that is connected to the CPU's diode
1444		 *
1445		 * Ideally we should use userspace thermal governor,
1446		 * but it's a much more complex solution.  The "skin"
1447		 * zone is a simpler solution which prevents A500 from
1448		 * getting too hot from a user's tactile perspective.
1449		 * The CPU zone is intended to protect silicon from damage.
1450		 */
1451
1452		skin-thermal {
1453			polling-delay-passive = <1000>; /* milliseconds */
1454			polling-delay = <5000>; /* milliseconds */
1455
1456			thermal-sensors = <&nct1008 0>;
1457
1458			trips {
1459				trip0: skin-alert {
1460					/* start throttling at 60C */
1461					temperature = <60000>;
1462					hysteresis = <200>;
1463					type = "passive";
1464				};
1465
1466				trip1: skin-crit {
1467					/* shut down at 70C */
1468					temperature = <70000>;
1469					hysteresis = <2000>;
1470					type = "critical";
1471				};
1472			};
1473
1474			cooling-maps {
1475				map0 {
1476					trip = <&trip0>;
1477					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1478							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1479				};
1480			};
1481		};
1482
1483		cpu-thermal {
1484			polling-delay-passive = <1000>; /* milliseconds */
1485			polling-delay = <5000>; /* milliseconds */
1486
1487			thermal-sensors = <&nct1008 1>;
1488
1489			trips {
1490				trip2: cpu-alert {
1491					/* throttle at 85C until temperature drops to 84.8C */
1492					temperature = <85000>;
1493					hysteresis = <200>;
1494					type = "passive";
1495				};
1496
1497				trip3: cpu-crit {
1498					/* shut down at 90C */
1499					temperature = <90000>;
1500					hysteresis = <2000>;
1501					type = "critical";
1502				};
1503			};
1504
1505			cooling-maps {
1506				map1 {
1507					trip = <&trip2>;
1508					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1509							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1510				};
1511			};
1512		};
1513	};
1514
1515	brcm_wifi_pwrseq: wifi-pwrseq {
1516		compatible = "mmc-pwrseq-simple";
1517
1518		clocks = <&rtc_32k_wifi>;
1519		clock-names = "ext_clock";
1520
1521		reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
1522		post-power-on-delay-ms = <300>;
1523		power-off-delay-us = <300>;
1524	};
1525};
1526