xref: /freebsd/sys/contrib/device-tree/src/arm/nuvoton/nuvoton-common-npcm7xx.dtsi (revision cb14a3fe5122c879eae1fb480ed7ce82a699ddb6) 
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc.
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	interrupt-parent = <&gic>;
13
14	/* external reference clock */
15	clk_refclk: clk_refclk {
16		compatible = "fixed-clock";
17		#clock-cells = <0>;
18		clock-frequency = <25000000>;
19		clock-output-names = "refclk";
20	};
21
22	/* external reference clock for cpu. float in normal operation */
23	clk_sysbypck: clk_sysbypck {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		clock-frequency = <800000000>;
27		clock-output-names = "sysbypck";
28	};
29
30	/* external reference clock for MC. float in normal operation */
31	clk_mcbypck: clk_mcbypck {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <800000000>;
35		clock-output-names = "mcbypck";
36	};
37
38	 /* external clock signal rg1refck, supplied by the phy */
39	clk_rg1refck: clk_rg1refck {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <125000000>;
43		clock-output-names = "clk_rg1refck";
44	};
45
46	 /* external clock signal rg2refck, supplied by the phy */
47	clk_rg2refck: clk_rg2refck {
48		compatible = "fixed-clock";
49		#clock-cells = <0>;
50		clock-frequency = <125000000>;
51		clock-output-names = "clk_rg2refck";
52	};
53
54	clk_xin: clk_xin {
55		compatible = "fixed-clock";
56		#clock-cells = <0>;
57		clock-frequency = <50000000>;
58		clock-output-names = "clk_xin";
59	};
60
61	soc {
62		#address-cells = <1>;
63		#size-cells = <1>;
64		compatible = "simple-bus";
65		interrupt-parent = <&gic>;
66		ranges = <0x0 0xf0000000 0x00900000>;
67
68		scu: scu@3fe000 {
69			compatible = "arm,cortex-a9-scu";
70			reg = <0x3fe000 0x1000>;
71		};
72
73		l2: cache-controller@3fc000 {
74			compatible = "arm,pl310-cache";
75			reg = <0x3fc000 0x1000>;
76			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
77			cache-unified;
78			cache-level = <2>;
79			clocks = <&clk NPCM7XX_CLK_AXI>;
80			arm,shared-override;
81		};
82
83		gic: interrupt-controller@3ff000 {
84			compatible = "arm,cortex-a9-gic";
85			interrupt-controller;
86			#interrupt-cells = <3>;
87			reg = <0x3ff000 0x1000>,
88				<0x3fe100 0x100>;
89		};
90
91		gcr: gcr@800000 {
92			compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
93			reg = <0x800000 0x1000>;
94		};
95
96		rst: rst@801000 {
97			compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
98			reg = <0x801000 0x6C>;
99		};
100	};
101
102	ahb {
103		#address-cells = <1>;
104		#size-cells = <1>;
105		compatible = "simple-bus";
106		interrupt-parent = <&gic>;
107		ranges;
108
109		rstc: rstc@f0801000 {
110			compatible = "nuvoton,npcm750-reset";
111			reg = <0xf0801000 0x70>;
112			#reset-cells = <2>;
113			nuvoton,sysgcr = <&gcr>;
114		};
115
116		clk: clock-controller@f0801000 {
117			compatible = "nuvoton,npcm750-clk", "syscon";
118			#clock-cells = <1>;
119			clock-controller;
120			reg = <0xf0801000 0x1000>;
121			clock-names = "refclk", "sysbypck", "mcbypck";
122			clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
123		};
124
125		gmac0: eth@f0802000 {
126			device_type = "network";
127			compatible = "snps,dwmac";
128			reg = <0xf0802000 0x2000>;
129			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130			interrupt-names = "macirq";
131			ethernet = <0>;
132			clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
133			clock-names = "stmmaceth", "clk_gmac";
134			pinctrl-names = "default";
135			pinctrl-0 = <&rg1_pins
136					&rg1mdio_pins>;
137			status = "disabled";
138		};
139
140		ehci1: usb@f0806000 {
141			compatible = "nuvoton,npcm750-ehci";
142			reg = <0xf0806000 0x1000>;
143			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
144			status = "disabled";
145		};
146
147		fiu0: spi@fb000000 {
148			compatible = "nuvoton,npcm750-fiu";
149			#address-cells = <1>;
150			#size-cells = <0>;
151			reg = <0xfb000000 0x1000>;
152			reg-names = "control", "memory";
153			clocks = <&clk NPCM7XX_CLK_SPI0>;
154			clock-names = "clk_spi0";
155			status = "disabled";
156		};
157
158		fiu3: spi@c0000000 {
159			compatible = "nuvoton,npcm750-fiu";
160			#address-cells = <1>;
161			#size-cells = <0>;
162			reg = <0xc0000000 0x1000>;
163			reg-names = "control", "memory";
164			clocks = <&clk NPCM7XX_CLK_SPI3>;
165			clock-names = "clk_spi3";
166			pinctrl-names = "default";
167			pinctrl-0 = <&spi3_pins>;
168			status = "disabled";
169		};
170
171		fiux: spi@fb001000 {
172			compatible = "nuvoton,npcm750-fiu";
173			#address-cells = <1>;
174			#size-cells = <0>;
175			reg = <0xfb001000 0x1000>;
176			reg-names = "control", "memory";
177			clocks = <&clk NPCM7XX_CLK_SPIX>;
178			clock-names = "clk_spix";
179			status = "disabled";
180		};
181
182		apb {
183			#address-cells = <1>;
184			#size-cells = <1>;
185			compatible = "simple-bus";
186			interrupt-parent = <&gic>;
187			ranges = <0x0 0xf0000000 0x00300000>;
188
189			lpc_kcs: lpc_kcs@7000 {
190				compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
191				reg = <0x7000 0x40>;
192				reg-io-width = <1>;
193
194				#address-cells = <1>;
195				#size-cells = <1>;
196				ranges = <0x0 0x7000 0x40>;
197
198				kcs1: kcs1@0 {
199					compatible = "nuvoton,npcm750-kcs-bmc";
200					reg = <0x0 0x40>;
201					interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
202					kcs_chan = <1>;
203					status = "disabled";
204				};
205
206				kcs2: kcs2@0 {
207					compatible = "nuvoton,npcm750-kcs-bmc";
208					reg = <0x0 0x40>;
209					interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
210					kcs_chan = <2>;
211					status = "disabled";
212				};
213
214				kcs3: kcs3@0 {
215					compatible = "nuvoton,npcm750-kcs-bmc";
216					reg = <0x0 0x40>;
217					interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
218					kcs_chan = <3>;
219					status = "disabled";
220				};
221			};
222
223			spi0: spi@200000 {
224				compatible = "nuvoton,npcm750-pspi";
225				reg = <0x200000 0x1000>;
226				pinctrl-names = "default";
227				pinctrl-0 = <&pspi1_pins>;
228				#address-cells = <1>;
229				#size-cells = <0>;
230				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
231				clocks = <&clk NPCM7XX_CLK_APB5>;
232				clock-names = "clk_apb5";
233				resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
234				status = "disabled";
235			};
236
237			spi1: spi@201000 {
238				compatible = "nuvoton,npcm750-pspi";
239				reg = <0x201000 0x1000>;
240				pinctrl-names = "default";
241				pinctrl-0 = <&pspi2_pins>;
242				#address-cells = <1>;
243				#size-cells = <0>;
244				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
245				clocks = <&clk NPCM7XX_CLK_APB5>;
246				clock-names = "clk_apb5";
247				resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>;
248				status = "disabled";
249			};
250
251			timer0: timer@8000 {
252				compatible = "nuvoton,npcm750-timer";
253				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
254				reg = <0x8000 0x1C>;
255				clocks = <&clk NPCM7XX_CLK_TIMER>;
256			};
257
258			watchdog0: watchdog@801C {
259				compatible = "nuvoton,npcm750-wdt";
260				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
261				reg = <0x801C 0x4>;
262				status = "disabled";
263				clocks = <&clk NPCM7XX_CLK_TIMER>;
264			};
265
266			watchdog1: watchdog@901C {
267				compatible = "nuvoton,npcm750-wdt";
268				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
269				reg = <0x901C 0x4>;
270				status = "disabled";
271				clocks = <&clk NPCM7XX_CLK_TIMER>;
272			};
273
274			watchdog2: watchdog@a01C {
275				compatible = "nuvoton,npcm750-wdt";
276				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
277				reg = <0xa01C 0x4>;
278				status = "disabled";
279				clocks = <&clk NPCM7XX_CLK_TIMER>;
280			};
281
282			serial0: serial@1000 {
283				compatible = "nuvoton,npcm750-uart";
284				reg = <0x1000 0x1000>;
285				clocks = <&clk NPCM7XX_CLK_UART>;
286				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
287				reg-shift = <2>;
288				status = "disabled";
289			};
290
291			serial1: serial@2000 {
292				compatible = "nuvoton,npcm750-uart";
293				reg = <0x2000 0x1000>;
294				clocks = <&clk NPCM7XX_CLK_UART>;
295				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
296				reg-shift = <2>;
297				status = "disabled";
298			};
299
300			serial2: serial@3000 {
301				compatible = "nuvoton,npcm750-uart";
302				reg = <0x3000 0x1000>;
303				clocks = <&clk NPCM7XX_CLK_UART>;
304				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
305				reg-shift = <2>;
306				status = "disabled";
307			};
308
309			serial3: serial@4000 {
310				compatible = "nuvoton,npcm750-uart";
311				reg = <0x4000 0x1000>;
312				clocks = <&clk NPCM7XX_CLK_UART>;
313				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
314				reg-shift = <2>;
315				status = "disabled";
316			};
317
318			rng: rng@b000 {
319				compatible = "nuvoton,npcm750-rng";
320				reg = <0xb000 0x8>;
321				status = "disabled";
322			};
323
324			adc: adc@c000 {
325				compatible = "nuvoton,npcm750-adc";
326				reg = <0xc000 0x8>;
327				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
328				clocks = <&clk NPCM7XX_CLK_ADC>;
329				resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
330				status = "disabled";
331			};
332
333			pwm_fan: pwm-fan-controller@103000 {
334				#address-cells = <1>;
335				#size-cells = <0>;
336				compatible = "nuvoton,npcm750-pwm-fan";
337				reg = <0x103000 0x2000>, <0x180000 0x8000>;
338				reg-names = "pwm", "fan";
339				clocks = <&clk NPCM7XX_CLK_APB3>,
340					<&clk NPCM7XX_CLK_APB4>;
341				clock-names = "pwm","fan";
342				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
343						<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
344						<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
345						<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
346						<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
347						<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
348						<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
349						<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
350				pinctrl-names = "default";
351				pinctrl-0 = <&pwm0_pins &pwm1_pins
352						&pwm2_pins &pwm3_pins
353						&pwm4_pins &pwm5_pins
354						&pwm6_pins &pwm7_pins
355						&fanin0_pins &fanin1_pins
356						&fanin2_pins &fanin3_pins
357						&fanin4_pins &fanin5_pins
358						&fanin6_pins &fanin7_pins
359						&fanin8_pins &fanin9_pins
360						&fanin10_pins &fanin11_pins
361						&fanin12_pins &fanin13_pins
362						&fanin14_pins &fanin15_pins>;
363				status = "disabled";
364			};
365
366			i2c0: i2c@80000 {
367				reg = <0x80000 0x1000>;
368				compatible = "nuvoton,npcm750-i2c";
369				#address-cells = <1>;
370				#size-cells = <0>;
371				clocks = <&clk NPCM7XX_CLK_APB2>;
372				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
373				pinctrl-names = "default";
374				pinctrl-0 = <&smb0_pins>;
375				status = "disabled";
376			};
377
378			i2c1: i2c@81000 {
379				reg = <0x81000 0x1000>;
380				compatible = "nuvoton,npcm750-i2c";
381				#address-cells = <1>;
382				#size-cells = <0>;
383				clocks = <&clk NPCM7XX_CLK_APB2>;
384				interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
385				pinctrl-names = "default";
386				pinctrl-0 = <&smb1_pins>;
387				status = "disabled";
388			};
389
390			i2c2: i2c@82000 {
391				reg = <0x82000 0x1000>;
392				compatible = "nuvoton,npcm750-i2c";
393				#address-cells = <1>;
394				#size-cells = <0>;
395				clocks = <&clk NPCM7XX_CLK_APB2>;
396				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
397				pinctrl-names = "default";
398				pinctrl-0 = <&smb2_pins>;
399				status = "disabled";
400			};
401
402			i2c3: i2c@83000 {
403				reg = <0x83000 0x1000>;
404				compatible = "nuvoton,npcm750-i2c";
405				#address-cells = <1>;
406				#size-cells = <0>;
407				clocks = <&clk NPCM7XX_CLK_APB2>;
408				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
409				pinctrl-names = "default";
410				pinctrl-0 = <&smb3_pins>;
411				status = "disabled";
412			};
413
414			i2c4: i2c@84000 {
415				reg = <0x84000 0x1000>;
416				compatible = "nuvoton,npcm750-i2c";
417				#address-cells = <1>;
418				#size-cells = <0>;
419				clocks = <&clk NPCM7XX_CLK_APB2>;
420				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
421				pinctrl-names = "default";
422				pinctrl-0 = <&smb4_pins>;
423				status = "disabled";
424			};
425
426			i2c5: i2c@85000 {
427				reg = <0x85000 0x1000>;
428				compatible = "nuvoton,npcm750-i2c";
429				#address-cells = <1>;
430				#size-cells = <0>;
431				clocks = <&clk NPCM7XX_CLK_APB2>;
432				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
433				pinctrl-names = "default";
434				pinctrl-0 = <&smb5_pins>;
435				status = "disabled";
436			};
437
438			i2c6: i2c@86000 {
439				reg = <0x86000 0x1000>;
440				compatible = "nuvoton,npcm750-i2c";
441				#address-cells = <1>;
442				#size-cells = <0>;
443				clocks = <&clk NPCM7XX_CLK_APB2>;
444				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
445				pinctrl-names = "default";
446				pinctrl-0 = <&smb6_pins>;
447				status = "disabled";
448			};
449
450			i2c7: i2c@87000 {
451				reg = <0x87000 0x1000>;
452				compatible = "nuvoton,npcm750-i2c";
453				#address-cells = <1>;
454				#size-cells = <0>;
455				clocks = <&clk NPCM7XX_CLK_APB2>;
456				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
457				pinctrl-names = "default";
458				pinctrl-0 = <&smb7_pins>;
459				status = "disabled";
460			};
461
462			i2c8: i2c@88000 {
463				reg = <0x88000 0x1000>;
464				compatible = "nuvoton,npcm750-i2c";
465				#address-cells = <1>;
466				#size-cells = <0>;
467				clocks = <&clk NPCM7XX_CLK_APB2>;
468				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
469				pinctrl-names = "default";
470				pinctrl-0 = <&smb8_pins>;
471				status = "disabled";
472			};
473
474			i2c9: i2c@89000 {
475				reg = <0x89000 0x1000>;
476				compatible = "nuvoton,npcm750-i2c";
477				#address-cells = <1>;
478				#size-cells = <0>;
479				clocks = <&clk NPCM7XX_CLK_APB2>;
480				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
481				pinctrl-names = "default";
482				pinctrl-0 = <&smb9_pins>;
483				status = "disabled";
484			};
485
486			i2c10: i2c@8a000 {
487				reg = <0x8a000 0x1000>;
488				compatible = "nuvoton,npcm750-i2c";
489				#address-cells = <1>;
490				#size-cells = <0>;
491				clocks = <&clk NPCM7XX_CLK_APB2>;
492				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
493				pinctrl-names = "default";
494				pinctrl-0 = <&smb10_pins>;
495				status = "disabled";
496			};
497
498			i2c11: i2c@8b000 {
499				reg = <0x8b000 0x1000>;
500				compatible = "nuvoton,npcm750-i2c";
501				#address-cells = <1>;
502				#size-cells = <0>;
503				clocks = <&clk NPCM7XX_CLK_APB2>;
504				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
505				pinctrl-names = "default";
506				pinctrl-0 = <&smb11_pins>;
507				status = "disabled";
508			};
509
510			i2c12: i2c@8c000 {
511				reg = <0x8c000 0x1000>;
512				compatible = "nuvoton,npcm750-i2c";
513				#address-cells = <1>;
514				#size-cells = <0>;
515				clocks = <&clk NPCM7XX_CLK_APB2>;
516				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
517				pinctrl-names = "default";
518				pinctrl-0 = <&smb12_pins>;
519				status = "disabled";
520			};
521
522			i2c13: i2c@8d000 {
523				reg = <0x8d000 0x1000>;
524				compatible = "nuvoton,npcm750-i2c";
525				#address-cells = <1>;
526				#size-cells = <0>;
527				clocks = <&clk NPCM7XX_CLK_APB2>;
528				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
529				pinctrl-names = "default";
530				pinctrl-0 = <&smb13_pins>;
531				status = "disabled";
532			};
533
534			i2c14: i2c@8e000 {
535				reg = <0x8e000 0x1000>;
536				compatible = "nuvoton,npcm750-i2c";
537				#address-cells = <1>;
538				#size-cells = <0>;
539				clocks = <&clk NPCM7XX_CLK_APB2>;
540				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
541				pinctrl-names = "default";
542				pinctrl-0 = <&smb14_pins>;
543				status = "disabled";
544			};
545
546			i2c15: i2c@8f000 {
547				reg = <0x8f000 0x1000>;
548				compatible = "nuvoton,npcm750-i2c";
549				#address-cells = <1>;
550				#size-cells = <0>;
551				clocks = <&clk NPCM7XX_CLK_APB2>;
552				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
553				pinctrl-names = "default";
554				pinctrl-0 = <&smb15_pins>;
555				status = "disabled";
556			};
557		};
558	};
559
560	pinctrl: pinctrl@f0800000 {
561		#address-cells = <1>;
562		#size-cells = <1>;
563		compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
564		ranges = <0 0xf0010000 0x8000>;
565		gpio0: gpio@f0010000 {
566			gpio-controller;
567			#gpio-cells = <2>;
568			reg = <0x0 0x80>;
569			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
570			gpio-ranges = <&pinctrl 0 0 32>;
571		};
572		gpio1: gpio@f0011000 {
573			gpio-controller;
574			#gpio-cells = <2>;
575			reg = <0x1000 0x80>;
576			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
577			gpio-ranges = <&pinctrl 0 32 32>;
578		};
579		gpio2: gpio@f0012000 {
580			gpio-controller;
581			#gpio-cells = <2>;
582			reg = <0x2000 0x80>;
583			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
584			gpio-ranges = <&pinctrl 0 64 32>;
585		};
586		gpio3: gpio@f0013000 {
587			gpio-controller;
588			#gpio-cells = <2>;
589			reg = <0x3000 0x80>;
590			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
591			gpio-ranges = <&pinctrl 0 96 32>;
592		};
593		gpio4: gpio@f0014000 {
594			gpio-controller;
595			#gpio-cells = <2>;
596			reg = <0x4000 0x80>;
597			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
598			gpio-ranges = <&pinctrl 0 128 32>;
599		};
600		gpio5: gpio@f0015000 {
601			gpio-controller;
602			#gpio-cells = <2>;
603			reg = <0x5000 0x80>;
604			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
605			gpio-ranges = <&pinctrl 0 160 32>;
606		};
607		gpio6: gpio@f0016000 {
608			gpio-controller;
609			#gpio-cells = <2>;
610			reg = <0x6000 0x80>;
611			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
612			gpio-ranges = <&pinctrl 0 192 32>;
613		};
614		gpio7: gpio@f0017000 {
615			gpio-controller;
616			#gpio-cells = <2>;
617			reg = <0x7000 0x80>;
618			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
619			gpio-ranges = <&pinctrl 0 224 32>;
620		};
621
622		iox1_pins: iox1-pins {
623			groups = "iox1";
624			function = "iox1";
625		};
626		iox2_pins: iox2-pins {
627			groups = "iox2";
628			function = "iox2";
629		};
630		smb1d_pins: smb1d-pins {
631			groups = "smb1d";
632			function = "smb1d";
633		};
634		smb2d_pins: smb2d-pins {
635			groups = "smb2d";
636			function = "smb2d";
637		};
638		lkgpo1_pins: lkgpo1-pins {
639			groups = "lkgpo1";
640			function = "lkgpo1";
641		};
642		lkgpo2_pins: lkgpo2-pins {
643			groups = "lkgpo2";
644			function = "lkgpo2";
645		};
646		ioxh_pins: ioxh-pins {
647			groups = "ioxh";
648			function = "ioxh";
649		};
650		gspi_pins: gspi-pins {
651			groups = "gspi";
652			function = "gspi";
653		};
654		smb5b_pins: smb5b-pins {
655			groups = "smb5b";
656			function = "smb5b";
657		};
658		smb5c_pins: smb5c-pins {
659			groups = "smb5c";
660			function = "smb5c";
661		};
662		lkgpo0_pins: lkgpo0-pins {
663			groups = "lkgpo0";
664			function = "lkgpo0";
665		};
666		pspi2_pins: pspi2-pins {
667			groups = "pspi2";
668			function = "pspi2";
669		};
670		smb4den_pins: smb4den-pins {
671			groups = "smb4den";
672			function = "smb4den";
673		};
674		smb4b_pins: smb4b-pins {
675			groups = "smb4b";
676			function = "smb4b";
677		};
678		smb4c_pins: smb4c-pins {
679			groups = "smb4c";
680			function = "smb4c";
681		};
682		smb15_pins: smb15-pins {
683			groups = "smb15";
684			function = "smb15";
685		};
686		smb4d_pins: smb4d-pins {
687			groups = "smb4d";
688			function = "smb4d";
689		};
690		smb14_pins: smb14-pins {
691			groups = "smb14";
692			function = "smb14";
693		};
694		smb5_pins: smb5-pins {
695			groups = "smb5";
696			function = "smb5";
697		};
698		smb4_pins: smb4-pins {
699			groups = "smb4";
700			function = "smb4";
701		};
702		smb3_pins: smb3-pins {
703			groups = "smb3";
704			function = "smb3";
705		};
706		spi0cs1_pins: spi0cs1-pins {
707			groups = "spi0cs1";
708			function = "spi0cs1";
709		};
710		spi0cs2_pins: spi0cs2-pins {
711			groups = "spi0cs2";
712			function = "spi0cs2";
713		};
714		spi0cs3_pins: spi0cs3-pins {
715			groups = "spi0cs3";
716			function = "spi0cs3";
717		};
718		smb3c_pins: smb3c-pins {
719			groups = "smb3c";
720			function = "smb3c";
721		};
722		smb3b_pins: smb3b-pins {
723			groups = "smb3b";
724			function = "smb3b";
725		};
726		bmcuart0a_pins: bmcuart0a-pins {
727			groups = "bmcuart0a";
728			function = "bmcuart0a";
729		};
730		uart1_pins: uart1-pins {
731			groups = "uart1";
732			function = "uart1";
733		};
734		jtag2_pins: jtag2-pins {
735			groups = "jtag2";
736			function = "jtag2";
737		};
738		bmcuart1_pins: bmcuart1-pins {
739			groups = "bmcuart1";
740			function = "bmcuart1";
741		};
742		uart2_pins: uart2-pins {
743			groups = "uart2";
744			function = "uart2";
745		};
746		bmcuart0b_pins: bmcuart0b-pins {
747			groups = "bmcuart0b";
748			function = "bmcuart0b";
749		};
750		r1err_pins: r1err-pins {
751			groups = "r1err";
752			function = "r1err";
753		};
754		r1md_pins: r1md-pins {
755			groups = "r1md";
756			function = "r1md";
757		};
758		smb3d_pins: smb3d-pins {
759			groups = "smb3d";
760			function = "smb3d";
761		};
762		fanin0_pins: fanin0-pins {
763			groups = "fanin0";
764			function = "fanin0";
765		};
766		fanin1_pins: fanin1-pins {
767			groups = "fanin1";
768			function = "fanin1";
769		};
770		fanin2_pins: fanin2-pins {
771			groups = "fanin2";
772			function = "fanin2";
773		};
774		fanin3_pins: fanin3-pins {
775			groups = "fanin3";
776			function = "fanin3";
777		};
778		fanin4_pins: fanin4-pins {
779			groups = "fanin4";
780			function = "fanin4";
781		};
782		fanin5_pins: fanin5-pins {
783			groups = "fanin5";
784			function = "fanin5";
785		};
786		fanin6_pins: fanin6-pins {
787			groups = "fanin6";
788			function = "fanin6";
789		};
790		fanin7_pins: fanin7-pins {
791			groups = "fanin7";
792			function = "fanin7";
793		};
794		fanin8_pins: fanin8-pins {
795			groups = "fanin8";
796			function = "fanin8";
797		};
798		fanin9_pins: fanin9-pins {
799			groups = "fanin9";
800			function = "fanin9";
801		};
802		fanin10_pins: fanin10-pins {
803			groups = "fanin10";
804			function = "fanin10";
805		};
806		fanin11_pins: fanin11-pins {
807			groups = "fanin11";
808			function = "fanin11";
809		};
810		fanin12_pins: fanin12-pins {
811			groups = "fanin12";
812			function = "fanin12";
813		};
814		fanin13_pins: fanin13-pins {
815			groups = "fanin13";
816			function = "fanin13";
817		};
818		fanin14_pins: fanin14-pins {
819			groups = "fanin14";
820			function = "fanin14";
821		};
822		fanin15_pins: fanin15-pins {
823			groups = "fanin15";
824			function = "fanin15";
825		};
826		pwm0_pins: pwm0-pins {
827			groups = "pwm0";
828			function = "pwm0";
829		};
830		pwm1_pins: pwm1-pins {
831			groups = "pwm1";
832			function = "pwm1";
833		};
834		pwm2_pins: pwm2-pins {
835			groups = "pwm2";
836			function = "pwm2";
837		};
838		pwm3_pins: pwm3-pins {
839			groups = "pwm3";
840			function = "pwm3";
841		};
842		r2_pins: r2-pins {
843			groups = "r2";
844			function = "r2";
845		};
846		r2err_pins: r2err-pins {
847			groups = "r2err";
848			function = "r2err";
849		};
850		r2md_pins: r2md-pins {
851			groups = "r2md";
852			function = "r2md";
853		};
854		ga20kbc_pins: ga20kbc-pins {
855			groups = "ga20kbc";
856			function = "ga20kbc";
857		};
858		smb5d_pins: smb5d-pins {
859			groups = "smb5d";
860			function = "smb5d";
861		};
862		lpc_pins: lpc-pins {
863			groups = "lpc";
864			function = "lpc";
865		};
866		espi_pins: espi-pins {
867			groups = "espi";
868			function = "espi";
869		};
870		rg1_pins: rg1-pins {
871			groups = "rg1";
872			function = "rg1";
873		};
874		rg1mdio_pins: rg1mdio-pins {
875			groups = "rg1mdio";
876			function = "rg1mdio";
877		};
878		rg2_pins: rg2-pins {
879			groups = "rg2";
880			function = "rg2";
881		};
882		ddr_pins: ddr-pins {
883			groups = "ddr";
884			function = "ddr";
885		};
886		smb0_pins: smb0-pins {
887			groups = "smb0";
888			function = "smb0";
889		};
890		smb1_pins: smb1-pins {
891			groups = "smb1";
892			function = "smb1";
893		};
894		smb2_pins: smb2-pins {
895			groups = "smb2";
896			function = "smb2";
897		};
898		smb2c_pins: smb2c-pins {
899			groups = "smb2c";
900			function = "smb2c";
901		};
902		smb2b_pins: smb2b-pins {
903			groups = "smb2b";
904			function = "smb2b";
905		};
906		smb1c_pins: smb1c-pins {
907			groups = "smb1c";
908			function = "smb1c";
909		};
910		smb1b_pins: smb1b-pins {
911			groups = "smb1b";
912			function = "smb1b";
913		};
914		smb8_pins: smb8-pins {
915			groups = "smb8";
916			function = "smb8";
917		};
918		smb9_pins: smb9-pins {
919			groups = "smb9";
920			function = "smb9";
921		};
922		smb10_pins: smb10-pins {
923			groups = "smb10";
924			function = "smb10";
925		};
926		smb11_pins: smb11-pins {
927			groups = "smb11";
928			function = "smb11";
929		};
930		sd1_pins: sd1-pins {
931			groups = "sd1";
932			function = "sd1";
933		};
934		sd1pwr_pins: sd1pwr-pins {
935			groups = "sd1pwr";
936			function = "sd1pwr";
937		};
938		pwm4_pins: pwm4-pins {
939			groups = "pwm4";
940			function = "pwm4";
941		};
942		pwm5_pins: pwm5-pins {
943			groups = "pwm5";
944			function = "pwm5";
945		};
946		pwm6_pins: pwm6-pins {
947			groups = "pwm6";
948			function = "pwm6";
949		};
950		pwm7_pins: pwm7-pins {
951			groups = "pwm7";
952			function = "pwm7";
953		};
954		mmc8_pins: mmc8-pins {
955			groups = "mmc8";
956			function = "mmc8";
957		};
958		mmc_pins: mmc-pins {
959			groups = "mmc";
960			function = "mmc";
961		};
962		mmcwp_pins: mmcwp-pins {
963			groups = "mmcwp";
964			function = "mmcwp";
965		};
966		mmccd_pins: mmccd-pins {
967			groups = "mmccd";
968			function = "mmccd";
969		};
970		mmcrst_pins: mmcrst-pins {
971			groups = "mmcrst";
972			function = "mmcrst";
973		};
974		clkout_pins: clkout-pins {
975			groups = "clkout";
976			function = "clkout";
977		};
978		serirq_pins: serirq-pins {
979			groups = "serirq";
980			function = "serirq";
981		};
982		lpcclk_pins: lpcclk-pins {
983			groups = "lpcclk";
984			function = "lpcclk";
985		};
986		scipme_pins: scipme-pins {
987			groups = "scipme";
988			function = "scipme";
989		};
990		sci_pins: sci-pins {
991			groups = "sci";
992			function = "sci";
993		};
994		smb6_pins: smb6-pins {
995			groups = "smb6";
996			function = "smb6";
997		};
998		smb7_pins: smb7-pins {
999			groups = "smb7";
1000			function = "smb7";
1001		};
1002		pspi1_pins: pspi1-pins {
1003			groups = "pspi1";
1004			function = "pspi1";
1005		};
1006		faninx_pins: faninx-pins {
1007			groups = "faninx";
1008			function = "faninx";
1009		};
1010		r1_pins: r1-pins {
1011			groups = "r1";
1012			function = "r1";
1013		};
1014		spi3_pins: spi3-pins {
1015			groups = "spi3";
1016			function = "spi3";
1017		};
1018		spi3cs1_pins: spi3cs1-pins {
1019			groups = "spi3cs1";
1020			function = "spi3cs1";
1021		};
1022		spi3quad_pins: spi3quad-pins {
1023			groups = "spi3quad";
1024			function = "spi3quad";
1025		};
1026		spi3cs2_pins: spi3cs2-pins {
1027			groups = "spi3cs2";
1028			function = "spi3cs2";
1029		};
1030		spi3cs3_pins: spi3cs3-pins {
1031			groups = "spi3cs3";
1032			function = "spi3cs3";
1033		};
1034		nprd_smi_pins: nprd-smi-pins {
1035			groups = "nprd_smi";
1036			function = "nprd_smi";
1037		};
1038		smb0b_pins: smb0b-pins {
1039			groups = "smb0b";
1040			function = "smb0b";
1041		};
1042		smb0c_pins: smb0c-pins {
1043			groups = "smb0c";
1044			function = "smb0c";
1045		};
1046		smb0den_pins: smb0den-pins {
1047			groups = "smb0den";
1048			function = "smb0den";
1049		};
1050		smb0d_pins: smb0d-pins {
1051			groups = "smb0d";
1052			function = "smb0d";
1053		};
1054		ddc_pins: ddc-pins {
1055			groups = "ddc";
1056			function = "ddc";
1057		};
1058		rg2mdio_pins: rg2mdio-pins {
1059			groups = "rg2mdio";
1060			function = "rg2mdio";
1061		};
1062		wdog1_pins: wdog1-pins {
1063			groups = "wdog1";
1064			function = "wdog1";
1065		};
1066		wdog2_pins: wdog2-pins {
1067			groups = "wdog2";
1068			function = "wdog2";
1069		};
1070		smb12_pins: smb12-pins {
1071			groups = "smb12";
1072			function = "smb12";
1073		};
1074		smb13_pins: smb13-pins {
1075			groups = "smb13";
1076			function = "smb13";
1077		};
1078		spix_pins: spix-pins {
1079			groups = "spix";
1080			function = "spix";
1081		};
1082		spixcs1_pins: spixcs1-pins {
1083			groups = "spixcs1";
1084			function = "spixcs1";
1085		};
1086		clkreq_pins: clkreq-pins {
1087			groups = "clkreq";
1088			function = "clkreq";
1089		};
1090		hgpio0_pins: hgpio0-pins {
1091			groups = "hgpio0";
1092			function = "hgpio0";
1093		};
1094		hgpio1_pins: hgpio1-pins {
1095			groups = "hgpio1";
1096			function = "hgpio1";
1097		};
1098		hgpio2_pins: hgpio2-pins {
1099			groups = "hgpio2";
1100			function = "hgpio2";
1101		};
1102		hgpio3_pins: hgpio3-pins {
1103			groups = "hgpio3";
1104			function = "hgpio3";
1105		};
1106		hgpio4_pins: hgpio4-pins {
1107			groups = "hgpio4";
1108			function = "hgpio4";
1109		};
1110		hgpio5_pins: hgpio5-pins {
1111			groups = "hgpio5";
1112			function = "hgpio5";
1113		};
1114		hgpio6_pins: hgpio6-pins {
1115			groups = "hgpio6";
1116			function = "hgpio6";
1117		};
1118		hgpio7_pins: hgpio7-pins {
1119			groups = "hgpio7";
1120			function = "hgpio7";
1121		};
1122	};
1123};
1124