1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC 4 * 5 * Copyright (C) 2011 Atmel, 6 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, 7 * 2012 Joachim Eastwood <manabian@gmail.com> 8 * 9 * Based on at91sam9260.dtsi 10 */ 11 12#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/clock/at91.h> 16#include <dt-bindings/mfd/at91-usart.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 model = "Atmel AT91RM9200 family SoC"; 22 compatible = "atmel,at91rm9200"; 23 interrupt-parent = <&aic>; 24 25 aliases { 26 serial0 = &dbgu; 27 serial1 = &usart0; 28 serial2 = &usart1; 29 serial3 = &usart2; 30 serial4 = &usart3; 31 gpio0 = &pioA; 32 gpio1 = &pioB; 33 gpio2 = &pioC; 34 gpio3 = &pioD; 35 tcb0 = &tcb0; 36 tcb1 = &tcb1; 37 i2c0 = &i2c0; 38 ssc0 = &ssc0; 39 ssc1 = &ssc1; 40 ssc2 = &ssc2; 41 }; 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu@0 { 47 compatible = "arm,arm920t"; 48 device_type = "cpu"; 49 reg = <0>; 50 }; 51 }; 52 53 memory@20000000 { 54 device_type = "memory"; 55 reg = <0x20000000 0x04000000>; 56 }; 57 58 clocks { 59 slow_xtal: slow_xtal { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 63 }; 64 65 main_xtal: main_xtal { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <0>; 69 }; 70 }; 71 72 sram: sram@200000 { 73 compatible = "mmio-sram"; 74 reg = <0x00200000 0x4000>; 75 #address-cells = <1>; 76 #size-cells = <1>; 77 ranges = <0 0x00200000 0x4000>; 78 }; 79 80 ahb { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 apb { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges; 91 92 aic: interrupt-controller@fffff000 { 93 #interrupt-cells = <3>; 94 compatible = "atmel,at91rm9200-aic"; 95 interrupt-controller; 96 reg = <0xfffff000 0x200>; 97 atmel,external-irqs = <25 26 27 28 29 30 31>; 98 }; 99 100 ramc0: ramc@ffffff00 { 101 compatible = "atmel,at91rm9200-sdramc", "syscon"; 102 reg = <0xffffff00 0x100>; 103 }; 104 105 pmc: clock-controller@fffffc00 { 106 compatible = "atmel,at91rm9200-pmc", "syscon"; 107 reg = <0xfffffc00 0x100>; 108 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 109 #clock-cells = <2>; 110 clocks = <&slow_xtal>, <&main_xtal>; 111 clock-names = "slow_xtal", "main_xtal"; 112 }; 113 114 st: timer@fffffd00 { 115 compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; 116 reg = <0xfffffd00 0x100>; 117 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 118 clocks = <&slow_xtal>; 119 120 watchdog { 121 compatible = "atmel,at91rm9200-wdt"; 122 }; 123 }; 124 125 rtc: rtc@fffffe00 { 126 compatible = "atmel,at91rm9200-rtc"; 127 reg = <0xfffffe00 0x40>; 128 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 129 clocks = <&slow_xtal>; 130 status = "disabled"; 131 }; 132 133 tcb0: timer@fffa0000 { 134 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 reg = <0xfffa0000 0x100>; 138 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, 139 <18 IRQ_TYPE_LEVEL_HIGH 0>, 140 <19 IRQ_TYPE_LEVEL_HIGH 0>; 141 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; 142 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 143 }; 144 145 tcb1: timer@fffa4000 { 146 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 reg = <0xfffa4000 0x100>; 150 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>, 151 <21 IRQ_TYPE_LEVEL_HIGH 0>, 152 <22 IRQ_TYPE_LEVEL_HIGH 0>; 153 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; 154 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 155 }; 156 157 i2c0: i2c@fffb8000 { 158 compatible = "atmel,at91rm9200-i2c"; 159 reg = <0xfffb8000 0x4000>; 160 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_twi>; 163 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 status = "disabled"; 167 }; 168 169 mmc0: mmc@fffb4000 { 170 compatible = "atmel,hsmci"; 171 reg = <0xfffb4000 0x4000>; 172 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 173 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 174 clock-names = "mci_clk"; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 status = "disabled"; 178 }; 179 180 ssc0: ssc@fffd0000 { 181 compatible = "atmel,at91rm9200-ssc"; 182 reg = <0xfffd0000 0x4000>; 183 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 186 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 187 clock-names = "pclk"; 188 status = "disabled"; 189 }; 190 191 ssc1: ssc@fffd4000 { 192 compatible = "atmel,at91rm9200-ssc"; 193 reg = <0xfffd4000 0x4000>; 194 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 197 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 198 clock-names = "pclk"; 199 status = "disabled"; 200 }; 201 202 ssc2: ssc@fffd8000 { 203 compatible = "atmel,at91rm9200-ssc"; 204 reg = <0xfffd8000 0x4000>; 205 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; 208 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 209 clock-names = "pclk"; 210 status = "disabled"; 211 }; 212 213 macb0: ethernet@fffbc000 { 214 compatible = "cdns,at91rm9200-emac", "cdns,emac"; 215 reg = <0xfffbc000 0x4000>; 216 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 217 phy-mode = "rmii"; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_macb_rmii>; 220 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 221 clock-names = "ether_clk"; 222 status = "disabled"; 223 }; 224 225 pinctrl@fffff400 { 226 #address-cells = <1>; 227 #size-cells = <1>; 228 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 229 ranges = <0xfffff400 0xfffff400 0x800>; 230 231 atmel,mux-mask = < 232 /* A B */ 233 0xffffffff 0xffffffff /* pioA */ 234 0xffffffff 0x083fffff /* pioB */ 235 0xffff3fff 0x00000000 /* pioC */ 236 0x03ff87ff 0x0fffff80 /* pioD */ 237 >; 238 239 /* shared pinctrl settings */ 240 dbgu { 241 pinctrl_dbgu: dbgu-0 { 242 atmel,pins = 243 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 244 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 245 }; 246 }; 247 248 uart0 { 249 pinctrl_uart0: uart0-0 { 250 atmel,pins = 251 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE 252 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 253 }; 254 255 pinctrl_uart0_cts: uart0_cts-0 { 256 atmel,pins = 257 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ 258 }; 259 260 pinctrl_uart0_rts: uart0_rts-0 { 261 atmel,pins = 262 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 263 }; 264 }; 265 266 uart1 { 267 pinctrl_uart1: uart1-0 { 268 atmel,pins = 269 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE 270 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 271 }; 272 273 pinctrl_uart1_rts: uart1_rts-0 { 274 atmel,pins = 275 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */ 276 }; 277 278 pinctrl_uart1_cts: uart1_cts-0 { 279 atmel,pins = 280 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ 281 }; 282 283 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { 284 atmel,pins = 285 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ 286 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ 287 }; 288 289 pinctrl_uart1_dcd: uart1_dcd-0 { 290 atmel,pins = 291 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ 292 }; 293 294 pinctrl_uart1_ri: uart1_ri-0 { 295 atmel,pins = 296 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 297 }; 298 }; 299 300 uart2 { 301 pinctrl_uart2: uart2-0 { 302 atmel,pins = 303 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 304 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 305 }; 306 307 pinctrl_uart2_rts: uart2_rts-0 { 308 atmel,pins = 309 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 310 }; 311 312 pinctrl_uart2_cts: uart2_cts-0 { 313 atmel,pins = 314 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */ 315 }; 316 }; 317 318 uart3 { 319 pinctrl_uart3: uart3-0 { 320 atmel,pins = 321 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE 322 AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; 323 }; 324 325 pinctrl_uart3_rts: uart3_rts-0 { 326 atmel,pins = 327 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ 328 }; 329 330 pinctrl_uart3_cts: uart3_cts-0 { 331 atmel,pins = 332 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ 333 }; 334 }; 335 336 nand { 337 pinctrl_nand: nand-0 { 338 atmel,pins = 339 <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */ 340 AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */ 341 }; 342 }; 343 344 macb { 345 pinctrl_macb_rmii: macb_rmii-0 { 346 atmel,pins = 347 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */ 348 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */ 349 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ 350 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ 351 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ 352 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 353 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 354 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 355 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 356 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */ 357 }; 358 359 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 360 atmel,pins = 361 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */ 362 AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */ 363 AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */ 364 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */ 365 AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */ 366 AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */ 367 AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */ 368 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */ 369 }; 370 }; 371 372 mmc0 { 373 pinctrl_mmc0_clk: mmc0_clk-0 { 374 atmel,pins = 375 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ 376 }; 377 378 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 379 atmel,pins = 380 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ 381 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */ 382 }; 383 384 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 385 atmel,pins = 386 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */ 387 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */ 388 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */ 389 }; 390 391 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { 392 atmel,pins = 393 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */ 394 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */ 395 }; 396 397 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { 398 atmel,pins = 399 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */ 400 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ 401 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */ 402 }; 403 }; 404 405 ssc0 { 406 pinctrl_ssc0_tx: ssc0_tx-0 { 407 atmel,pins = 408 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ 409 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ 410 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */ 411 }; 412 413 pinctrl_ssc0_rx: ssc0_rx-0 { 414 atmel,pins = 415 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ 416 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ 417 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ 418 }; 419 }; 420 421 ssc1 { 422 pinctrl_ssc1_tx: ssc1_tx-0 { 423 atmel,pins = 424 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ 425 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ 426 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ 427 }; 428 429 pinctrl_ssc1_rx: ssc1_rx-0 { 430 atmel,pins = 431 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ 432 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ 433 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ 434 }; 435 }; 436 437 ssc2 { 438 pinctrl_ssc2_tx: ssc2_tx-0 { 439 atmel,pins = 440 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ 441 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ 442 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */ 443 }; 444 445 pinctrl_ssc2_rx: ssc2_rx-0 { 446 atmel,pins = 447 <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ 448 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ 449 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ 450 }; 451 }; 452 453 twi { 454 pinctrl_twi: twi-0 { 455 atmel,pins = 456 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */ 457 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */ 458 }; 459 460 pinctrl_twi_gpio: twi_gpio-0 { 461 atmel,pins = 462 <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */ 463 AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */ 464 }; 465 }; 466 467 tcb0 { 468 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 469 atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; 470 }; 471 472 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 473 atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 474 }; 475 476 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 477 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; 478 }; 479 480 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 481 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; 482 }; 483 484 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 485 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 486 }; 487 488 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 489 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; 490 }; 491 492 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 493 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 494 }; 495 496 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 497 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; 498 }; 499 500 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 501 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 502 }; 503 }; 504 505 tcb1 { 506 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 507 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; 508 }; 509 510 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 511 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; 512 }; 513 514 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 515 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; 516 }; 517 518 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 519 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; 520 }; 521 522 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 523 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 524 }; 525 526 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 527 atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 528 }; 529 530 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 531 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 532 }; 533 534 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 535 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 536 }; 537 538 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 539 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; 540 }; 541 }; 542 543 spi0 { 544 pinctrl_spi0: spi0-0 { 545 atmel,pins = 546 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ 547 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ 548 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ 549 }; 550 }; 551 552 pioA: gpio@fffff400 { 553 compatible = "atmel,at91rm9200-gpio"; 554 reg = <0xfffff400 0x200>; 555 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 556 #gpio-cells = <2>; 557 gpio-controller; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 561 }; 562 563 pioB: gpio@fffff600 { 564 compatible = "atmel,at91rm9200-gpio"; 565 reg = <0xfffff600 0x200>; 566 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 567 #gpio-cells = <2>; 568 gpio-controller; 569 interrupt-controller; 570 #interrupt-cells = <2>; 571 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 572 }; 573 574 pioC: gpio@fffff800 { 575 compatible = "atmel,at91rm9200-gpio"; 576 reg = <0xfffff800 0x200>; 577 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 578 #gpio-cells = <2>; 579 gpio-controller; 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 583 }; 584 585 pioD: gpio@fffffa00 { 586 compatible = "atmel,at91rm9200-gpio"; 587 reg = <0xfffffa00 0x200>; 588 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 589 #gpio-cells = <2>; 590 gpio-controller; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 594 }; 595 }; 596 597 dbgu: serial@fffff200 { 598 compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; 599 reg = <0xfffff200 0x200>; 600 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 601 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_dbgu>; 604 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 605 clock-names = "usart"; 606 status = "disabled"; 607 }; 608 609 usart0: serial@fffc0000 { 610 compatible = "atmel,at91rm9200-usart"; 611 reg = <0xfffc0000 0x200>; 612 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 613 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 614 atmel,use-dma-rx; 615 atmel,use-dma-tx; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&pinctrl_uart0>; 618 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 619 clock-names = "usart"; 620 status = "disabled"; 621 }; 622 623 usart1: serial@fffc4000 { 624 compatible = "atmel,at91rm9200-usart"; 625 reg = <0xfffc4000 0x200>; 626 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 627 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 628 atmel,use-dma-rx; 629 atmel,use-dma-tx; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pinctrl_uart1>; 632 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 633 clock-names = "usart"; 634 status = "disabled"; 635 }; 636 637 usart2: serial@fffc8000 { 638 compatible = "atmel,at91rm9200-usart"; 639 reg = <0xfffc8000 0x200>; 640 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 641 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 642 atmel,use-dma-rx; 643 atmel,use-dma-tx; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_uart2>; 646 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 647 clock-names = "usart"; 648 status = "disabled"; 649 }; 650 651 usart3: serial@fffcc000 { 652 compatible = "atmel,at91rm9200-usart"; 653 reg = <0xfffcc000 0x200>; 654 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 655 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; 656 atmel,use-dma-rx; 657 atmel,use-dma-tx; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&pinctrl_uart3>; 660 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 661 clock-names = "usart"; 662 status = "disabled"; 663 }; 664 665 usb1: gadget@fffb0000 { 666 compatible = "atmel,at91rm9200-udc"; 667 reg = <0xfffb0000 0x4000>; 668 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; 669 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>; 670 clock-names = "pclk", "hclk"; 671 status = "disabled"; 672 }; 673 674 spi0: spi@fffe0000 { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 compatible = "atmel,at91rm9200-spi"; 678 reg = <0xfffe0000 0x200>; 679 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_spi0>; 682 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 683 clock-names = "spi_clk"; 684 status = "disabled"; 685 }; 686 }; 687 688 nand0: nand@40000000 { 689 compatible = "atmel,at91rm9200-nand"; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 reg = <0x40000000 0x10000000>; 693 atmel,nand-addr-offset = <21>; 694 atmel,nand-cmd-offset = <22>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pinctrl_nand>; 697 nand-ecc-mode = "soft"; 698 gpios = <&pioC 2 GPIO_ACTIVE_HIGH 699 0 700 &pioB 1 GPIO_ACTIVE_HIGH 701 >; 702 status = "disabled"; 703 }; 704 705 usb0: ohci@300000 { 706 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 707 reg = <0x00300000 0x100000>; 708 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 709 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>; 710 clock-names = "ohci_clk", "hclk", "uhpck"; 711 status = "disabled"; 712 }; 713 }; 714 715 i2c-gpio-0 { 716 compatible = "i2c-gpio"; 717 gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ 718 &pioA 26 GPIO_ACTIVE_HIGH /* scl */ 719 >; 720 i2c-gpio,sda-open-drain; 721 i2c-gpio,scl-open-drain; 722 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_twi_gpio>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 }; 729}; 730