1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017-2018 MediaTek Inc. 4 * Author: John Crispin <john@phrozen.org> 5 * Sean Wang <sean.wang@mediatek.com> 6 * Ryder Lee <ryder.lee@mediatek.com> 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/clock/mt2701-clk.h> 13#include <dt-bindings/pinctrl/mt7623-pinfunc.h> 14#include <dt-bindings/power/mt2701-power.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/phy/phy.h> 17#include <dt-bindings/reset/mt2701-resets.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 compatible = "mediatek,mt7623"; 22 interrupt-parent = <&sysirq>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 cpu_opp_table: opp-table { 27 compatible = "operating-points-v2"; 28 opp-shared; 29 30 opp-98000000 { 31 opp-hz = /bits/ 64 <98000000>; 32 opp-microvolt = <1050000>; 33 }; 34 35 opp-198000000 { 36 opp-hz = /bits/ 64 <198000000>; 37 opp-microvolt = <1050000>; 38 }; 39 40 opp-398000000 { 41 opp-hz = /bits/ 64 <398000000>; 42 opp-microvolt = <1050000>; 43 }; 44 45 opp-598000000 { 46 opp-hz = /bits/ 64 <598000000>; 47 opp-microvolt = <1050000>; 48 }; 49 50 opp-747500000 { 51 opp-hz = /bits/ 64 <747500000>; 52 opp-microvolt = <1050000>; 53 }; 54 55 opp-1040000000 { 56 opp-hz = /bits/ 64 <1040000000>; 57 opp-microvolt = <1150000>; 58 }; 59 60 opp-1196000000 { 61 opp-hz = /bits/ 64 <1196000000>; 62 opp-microvolt = <1200000>; 63 }; 64 65 opp-1300000000 { 66 opp-hz = /bits/ 64 <1300000000>; 67 opp-microvolt = <1300000>; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 enable-method = "mediatek,mt6589-smp"; 75 76 cpu0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <0x0>; 80 clocks = <&infracfg CLK_INFRA_CPUSEL>, 81 <&apmixedsys CLK_APMIXED_MAINPLL>; 82 clock-names = "cpu", "intermediate"; 83 operating-points-v2 = <&cpu_opp_table>; 84 #cooling-cells = <2>; 85 clock-frequency = <1300000000>; 86 }; 87 88 cpu1: cpu@1 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 reg = <0x1>; 92 clocks = <&infracfg CLK_INFRA_CPUSEL>, 93 <&apmixedsys CLK_APMIXED_MAINPLL>; 94 clock-names = "cpu", "intermediate"; 95 operating-points-v2 = <&cpu_opp_table>; 96 #cooling-cells = <2>; 97 clock-frequency = <1300000000>; 98 }; 99 100 cpu2: cpu@2 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a7"; 103 reg = <0x2>; 104 clocks = <&infracfg CLK_INFRA_CPUSEL>, 105 <&apmixedsys CLK_APMIXED_MAINPLL>; 106 clock-names = "cpu", "intermediate"; 107 operating-points-v2 = <&cpu_opp_table>; 108 #cooling-cells = <2>; 109 clock-frequency = <1300000000>; 110 }; 111 112 cpu3: cpu@3 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a7"; 115 reg = <0x3>; 116 clocks = <&infracfg CLK_INFRA_CPUSEL>, 117 <&apmixedsys CLK_APMIXED_MAINPLL>; 118 clock-names = "cpu", "intermediate"; 119 operating-points-v2 = <&cpu_opp_table>; 120 #cooling-cells = <2>; 121 clock-frequency = <1300000000>; 122 }; 123 }; 124 125 pmu { 126 compatible = "arm,cortex-a7-pmu"; 127 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, 128 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, 129 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, 130 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; 131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 132 }; 133 134 system_clk: dummy13m { 135 compatible = "fixed-clock"; 136 clock-frequency = <13000000>; 137 #clock-cells = <0>; 138 }; 139 140 rtc32k: oscillator-1 { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <32000>; 144 clock-output-names = "rtc32k"; 145 }; 146 147 clk26m: oscillator-0 { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <26000000>; 151 clock-output-names = "clk26m"; 152 }; 153 154 thermal-zones { 155 cpu_thermal: cpu-thermal { 156 polling-delay-passive = <1000>; 157 polling-delay = <1000>; 158 159 thermal-sensors = <&thermal 0>; 160 161 trips { 162 cpu_passive: cpu-passive { 163 temperature = <57000>; 164 hysteresis = <2000>; 165 type = "passive"; 166 }; 167 168 cpu_active: cpu-active { 169 temperature = <67000>; 170 hysteresis = <2000>; 171 type = "active"; 172 }; 173 174 cpu_hot: cpu-hot { 175 temperature = <87000>; 176 hysteresis = <2000>; 177 type = "hot"; 178 }; 179 180 cpu-crit { 181 temperature = <107000>; 182 hysteresis = <2000>; 183 type = "critical"; 184 }; 185 }; 186 187 cooling-maps { 188 map0 { 189 trip = <&cpu_passive>; 190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 191 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 192 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 193 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 194 }; 195 196 map1 { 197 trip = <&cpu_active>; 198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 199 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 200 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 201 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 202 }; 203 204 map2 { 205 trip = <&cpu_hot>; 206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 210 }; 211 }; 212 }; 213 }; 214 215 timer { 216 compatible = "arm,armv7-timer"; 217 interrupt-parent = <&gic>; 218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 222 clock-frequency = <13000000>; 223 arm,cpu-registers-not-fw-configured; 224 }; 225 226 topckgen: syscon@10000000 { 227 compatible = "mediatek,mt7623-topckgen", 228 "mediatek,mt2701-topckgen", 229 "syscon"; 230 reg = <0 0x10000000 0 0x1000>; 231 #clock-cells = <1>; 232 }; 233 234 infracfg: syscon@10001000 { 235 compatible = "mediatek,mt7623-infracfg", 236 "mediatek,mt2701-infracfg", 237 "syscon"; 238 reg = <0 0x10001000 0 0x1000>; 239 #clock-cells = <1>; 240 #reset-cells = <1>; 241 }; 242 243 pericfg: syscon@10003000 { 244 compatible = "mediatek,mt7623-pericfg", 245 "mediatek,mt2701-pericfg", 246 "syscon"; 247 reg = <0 0x10003000 0 0x1000>; 248 #clock-cells = <1>; 249 #reset-cells = <1>; 250 }; 251 252 pio: pinctrl@10005000 { 253 compatible = "mediatek,mt7623-pinctrl"; 254 reg = <0 0x1000b000 0 0x1000>; 255 mediatek,pctl-regmap = <&syscfg_pctl_a>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 interrupt-controller; 259 interrupt-parent = <&gic>; 260 #interrupt-cells = <2>; 261 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 263 }; 264 265 syscfg_pctl_a: syscfg@10005000 { 266 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; 267 reg = <0 0x10005000 0 0x1000>; 268 }; 269 270 scpsys: power-controller@10006000 { 271 compatible = "mediatek,mt7623-scpsys", 272 "mediatek,mt2701-scpsys", 273 "syscon"; 274 #power-domain-cells = <1>; 275 reg = <0 0x10006000 0 0x1000>; 276 infracfg = <&infracfg>; 277 clocks = <&topckgen CLK_TOP_MM_SEL>, 278 <&topckgen CLK_TOP_MFG_SEL>, 279 <&topckgen CLK_TOP_ETHIF_SEL>; 280 clock-names = "mm", "mfg", "ethif"; 281 }; 282 283 watchdog: watchdog@10007000 { 284 compatible = "mediatek,mt7623-wdt", 285 "mediatek,mt6589-wdt"; 286 reg = <0 0x10007000 0 0x100>; 287 }; 288 289 timer: timer@10008000 { 290 compatible = "mediatek,mt7623-timer", 291 "mediatek,mt6577-timer"; 292 reg = <0 0x10008000 0 0x80>; 293 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 294 clocks = <&system_clk>, <&rtc32k>; 295 clock-names = "system-clk", "rtc-clk"; 296 }; 297 298 pwrap: pwrap@1000d000 { 299 compatible = "mediatek,mt7623-pwrap", 300 "mediatek,mt2701-pwrap"; 301 reg = <0 0x1000d000 0 0x1000>; 302 reg-names = "pwrap"; 303 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 304 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; 305 reset-names = "pwrap"; 306 clocks = <&infracfg CLK_INFRA_PMICSPI>, 307 <&infracfg CLK_INFRA_PMICWRAP>; 308 clock-names = "spi", "wrap"; 309 }; 310 311 cir: cir@10013000 { 312 compatible = "mediatek,mt7623-cir"; 313 reg = <0 0x10013000 0 0x1000>; 314 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 315 clocks = <&infracfg CLK_INFRA_IRRX>; 316 clock-names = "clk"; 317 status = "disabled"; 318 }; 319 320 sysirq: interrupt-controller@10200100 { 321 compatible = "mediatek,mt7623-sysirq", 322 "mediatek,mt6577-sysirq"; 323 interrupt-controller; 324 #interrupt-cells = <3>; 325 interrupt-parent = <&gic>; 326 reg = <0 0x10200100 0 0x1c>; 327 }; 328 329 efuse: efuse@10206000 { 330 compatible = "mediatek,mt7623-efuse", 331 "mediatek,mt8173-efuse"; 332 reg = <0 0x10206000 0 0x1000>; 333 #address-cells = <1>; 334 #size-cells = <1>; 335 thermal_calibration_data: calib@424 { 336 reg = <0x424 0xc>; 337 }; 338 }; 339 340 apmixedsys: syscon@10209000 { 341 compatible = "mediatek,mt7623-apmixedsys", 342 "mediatek,mt2701-apmixedsys", 343 "syscon"; 344 reg = <0 0x10209000 0 0x1000>; 345 #clock-cells = <1>; 346 }; 347 348 rng: rng@1020f000 { 349 compatible = "mediatek,mt7623-rng"; 350 reg = <0 0x1020f000 0 0x1000>; 351 clocks = <&infracfg CLK_INFRA_TRNG>; 352 clock-names = "rng"; 353 }; 354 355 gic: interrupt-controller@10211000 { 356 compatible = "arm,cortex-a7-gic"; 357 interrupt-controller; 358 #interrupt-cells = <3>; 359 interrupt-parent = <&gic>; 360 reg = <0 0x10211000 0 0x1000>, 361 <0 0x10212000 0 0x2000>, 362 <0 0x10214000 0 0x2000>, 363 <0 0x10216000 0 0x2000>; 364 }; 365 366 auxadc: adc@11001000 { 367 compatible = "mediatek,mt7623-auxadc", 368 "mediatek,mt2701-auxadc"; 369 reg = <0 0x11001000 0 0x1000>; 370 clocks = <&pericfg CLK_PERI_AUXADC>; 371 clock-names = "main"; 372 #io-channel-cells = <1>; 373 }; 374 375 uart0: serial@11002000 { 376 compatible = "mediatek,mt7623-uart", 377 "mediatek,mt6577-uart"; 378 reg = <0 0x11002000 0 0x400>; 379 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 380 clocks = <&pericfg CLK_PERI_UART0_SEL>, 381 <&pericfg CLK_PERI_UART0>; 382 clock-names = "baud", "bus"; 383 status = "disabled"; 384 }; 385 386 uart1: serial@11003000 { 387 compatible = "mediatek,mt7623-uart", 388 "mediatek,mt6577-uart"; 389 reg = <0 0x11003000 0 0x400>; 390 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 391 clocks = <&pericfg CLK_PERI_UART1_SEL>, 392 <&pericfg CLK_PERI_UART1>; 393 clock-names = "baud", "bus"; 394 status = "disabled"; 395 }; 396 397 uart2: serial@11004000 { 398 compatible = "mediatek,mt7623-uart", 399 "mediatek,mt6577-uart"; 400 reg = <0 0x11004000 0 0x400>; 401 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 402 clocks = <&pericfg CLK_PERI_UART2_SEL>, 403 <&pericfg CLK_PERI_UART2>; 404 clock-names = "baud", "bus"; 405 status = "disabled"; 406 }; 407 408 uart3: serial@11005000 { 409 compatible = "mediatek,mt7623-uart", 410 "mediatek,mt6577-uart"; 411 reg = <0 0x11005000 0 0x400>; 412 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 413 clocks = <&pericfg CLK_PERI_UART3_SEL>, 414 <&pericfg CLK_PERI_UART3>; 415 clock-names = "baud", "bus"; 416 status = "disabled"; 417 }; 418 419 pwm: pwm@11006000 { 420 compatible = "mediatek,mt7623-pwm"; 421 reg = <0 0x11006000 0 0x1000>; 422 #pwm-cells = <2>; 423 clocks = <&topckgen CLK_TOP_PWM_SEL>, 424 <&pericfg CLK_PERI_PWM>, 425 <&pericfg CLK_PERI_PWM1>, 426 <&pericfg CLK_PERI_PWM2>, 427 <&pericfg CLK_PERI_PWM3>, 428 <&pericfg CLK_PERI_PWM4>, 429 <&pericfg CLK_PERI_PWM5>; 430 clock-names = "top", "main", "pwm1", "pwm2", 431 "pwm3", "pwm4", "pwm5"; 432 status = "disabled"; 433 }; 434 435 i2c0: i2c@11007000 { 436 compatible = "mediatek,mt7623-i2c", 437 "mediatek,mt6577-i2c"; 438 reg = <0 0x11007000 0 0x70>, 439 <0 0x11000200 0 0x80>; 440 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; 441 clock-div = <16>; 442 clocks = <&pericfg CLK_PERI_I2C0>, 443 <&pericfg CLK_PERI_AP_DMA>; 444 clock-names = "main", "dma"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 }; 449 450 i2c1: i2c@11008000 { 451 compatible = "mediatek,mt7623-i2c", 452 "mediatek,mt6577-i2c"; 453 reg = <0 0x11008000 0 0x70>, 454 <0 0x11000280 0 0x80>; 455 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; 456 clock-div = <16>; 457 clocks = <&pericfg CLK_PERI_I2C1>, 458 <&pericfg CLK_PERI_AP_DMA>; 459 clock-names = "main", "dma"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 status = "disabled"; 463 }; 464 465 i2c2: i2c@11009000 { 466 compatible = "mediatek,mt7623-i2c", 467 "mediatek,mt6577-i2c"; 468 reg = <0 0x11009000 0 0x70>, 469 <0 0x11000300 0 0x80>; 470 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>; 471 clock-div = <16>; 472 clocks = <&pericfg CLK_PERI_I2C2>, 473 <&pericfg CLK_PERI_AP_DMA>; 474 clock-names = "main", "dma"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 status = "disabled"; 478 }; 479 480 spi0: spi@1100a000 { 481 compatible = "mediatek,mt7623-spi", 482 "mediatek,mt2701-spi"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 reg = <0 0x1100a000 0 0x100>; 486 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 488 <&topckgen CLK_TOP_SPI0_SEL>, 489 <&pericfg CLK_PERI_SPI0>; 490 clock-names = "parent-clk", "sel-clk", "spi-clk"; 491 status = "disabled"; 492 }; 493 494 thermal: thermal@1100b000 { 495 #thermal-sensor-cells = <1>; 496 compatible = "mediatek,mt7623-thermal", 497 "mediatek,mt2701-thermal"; 498 reg = <0 0x1100b000 0 0x1000>; 499 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 500 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 501 clock-names = "therm", "auxadc"; 502 resets = <&pericfg MT2701_PERI_THERM_SW_RST>; 503 reset-names = "therm"; 504 mediatek,auxadc = <&auxadc>; 505 mediatek,apmixedsys = <&apmixedsys>; 506 nvmem-cells = <&thermal_calibration_data>; 507 nvmem-cell-names = "calibration-data"; 508 }; 509 510 btif: serial@1100c000 { 511 compatible = "mediatek,mt7623-btif", 512 "mediatek,mtk-btif"; 513 reg = <0 0x1100c000 0 0x1000>; 514 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>; 515 clocks = <&pericfg CLK_PERI_BTIF>; 516 clock-names = "main"; 517 reg-shift = <2>; 518 reg-io-width = <4>; 519 status = "disabled"; 520 }; 521 522 nandc: nfi@1100d000 { 523 compatible = "mediatek,mt7623-nfc", 524 "mediatek,mt2701-nfc"; 525 reg = <0 0x1100d000 0 0x1000>; 526 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; 527 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 528 clocks = <&pericfg CLK_PERI_NFI>, 529 <&pericfg CLK_PERI_NFI_PAD>; 530 clock-names = "nfi_clk", "pad_clk"; 531 status = "disabled"; 532 ecc-engine = <&bch>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 }; 536 537 bch: ecc@1100e000 { 538 compatible = "mediatek,mt7623-ecc", 539 "mediatek,mt2701-ecc"; 540 reg = <0 0x1100e000 0 0x1000>; 541 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&pericfg CLK_PERI_NFI_ECC>; 543 clock-names = "nfiecc_clk"; 544 status = "disabled"; 545 }; 546 547 nor_flash: spi@11014000 { 548 compatible = "mediatek,mt7623-nor", 549 "mediatek,mt8173-nor"; 550 reg = <0 0x11014000 0 0x1000>; 551 clocks = <&pericfg CLK_PERI_FLASH>, 552 <&topckgen CLK_TOP_FLASH_SEL>; 553 clock-names = "spi", "sf"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 spi1: spi@11016000 { 560 compatible = "mediatek,mt7623-spi", 561 "mediatek,mt2701-spi"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 reg = <0 0x11016000 0 0x100>; 565 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 566 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 567 <&topckgen CLK_TOP_SPI1_SEL>, 568 <&pericfg CLK_PERI_SPI1>; 569 clock-names = "parent-clk", "sel-clk", "spi-clk"; 570 status = "disabled"; 571 }; 572 573 spi2: spi@11017000 { 574 compatible = "mediatek,mt7623-spi", 575 "mediatek,mt2701-spi"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 reg = <0 0x11017000 0 0x1000>; 579 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>; 580 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 581 <&topckgen CLK_TOP_SPI2_SEL>, 582 <&pericfg CLK_PERI_SPI2>; 583 clock-names = "parent-clk", "sel-clk", "spi-clk"; 584 status = "disabled"; 585 }; 586 587 usb0: usb@11200000 { 588 compatible = "mediatek,mt7623-musb", 589 "mediatek,mtk-musb"; 590 reg = <0 0x11200000 0 0x1000>; 591 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; 592 interrupt-names = "mc"; 593 phys = <&u2port2 PHY_TYPE_USB2>; 594 dr_mode = "otg"; 595 clocks = <&pericfg CLK_PERI_USB0>, 596 <&pericfg CLK_PERI_USB0_MCU>, 597 <&pericfg CLK_PERI_USB_SLV>; 598 clock-names = "main","mcu","univpll"; 599 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 600 status = "disabled"; 601 }; 602 603 u2phy1: t-phy@11210000 { 604 compatible = "mediatek,mt7623-tphy", 605 "mediatek,generic-tphy-v1"; 606 reg = <0 0x11210000 0 0x0800>; 607 #address-cells = <2>; 608 #size-cells = <2>; 609 ranges; 610 status = "disabled"; 611 612 u2port2: usb-phy@11210800 { 613 reg = <0 0x11210800 0 0x0100>; 614 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 615 clock-names = "ref"; 616 #phy-cells = <1>; 617 }; 618 }; 619 620 audsys: clock-controller@11220000 { 621 compatible = "mediatek,mt7623-audsys", 622 "mediatek,mt2701-audsys", 623 "syscon"; 624 reg = <0 0x11220000 0 0x2000>; 625 #clock-cells = <1>; 626 627 afe: audio-controller { 628 compatible = "mediatek,mt7623-audio", 629 "mediatek,mt2701-audio"; 630 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 631 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 632 interrupt-names = "afe", "asys"; 633 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 634 635 clocks = <&infracfg CLK_INFRA_AUDIO>, 636 <&topckgen CLK_TOP_AUD_MUX1_SEL>, 637 <&topckgen CLK_TOP_AUD_MUX2_SEL>, 638 <&topckgen CLK_TOP_AUD_48K_TIMING>, 639 <&topckgen CLK_TOP_AUD_44K_TIMING>, 640 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, 641 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, 642 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, 643 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, 644 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, 645 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, 646 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, 647 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, 648 <&topckgen CLK_TOP_AUD_I2S1_MCLK>, 649 <&topckgen CLK_TOP_AUD_I2S2_MCLK>, 650 <&topckgen CLK_TOP_AUD_I2S3_MCLK>, 651 <&topckgen CLK_TOP_AUD_I2S4_MCLK>, 652 <&audsys CLK_AUD_I2SO1>, 653 <&audsys CLK_AUD_I2SO2>, 654 <&audsys CLK_AUD_I2SO3>, 655 <&audsys CLK_AUD_I2SO4>, 656 <&audsys CLK_AUD_I2SIN1>, 657 <&audsys CLK_AUD_I2SIN2>, 658 <&audsys CLK_AUD_I2SIN3>, 659 <&audsys CLK_AUD_I2SIN4>, 660 <&audsys CLK_AUD_ASRCO1>, 661 <&audsys CLK_AUD_ASRCO2>, 662 <&audsys CLK_AUD_ASRCO3>, 663 <&audsys CLK_AUD_ASRCO4>, 664 <&audsys CLK_AUD_AFE>, 665 <&audsys CLK_AUD_AFE_CONN>, 666 <&audsys CLK_AUD_A1SYS>, 667 <&audsys CLK_AUD_A2SYS>, 668 <&audsys CLK_AUD_AFE_MRGIF>; 669 670 clock-names = "infra_sys_audio_clk", 671 "top_audio_mux1_sel", 672 "top_audio_mux2_sel", 673 "top_audio_a1sys_hp", 674 "top_audio_a2sys_hp", 675 "i2s0_src_sel", 676 "i2s1_src_sel", 677 "i2s2_src_sel", 678 "i2s3_src_sel", 679 "i2s0_src_div", 680 "i2s1_src_div", 681 "i2s2_src_div", 682 "i2s3_src_div", 683 "i2s0_mclk_en", 684 "i2s1_mclk_en", 685 "i2s2_mclk_en", 686 "i2s3_mclk_en", 687 "i2so0_hop_ck", 688 "i2so1_hop_ck", 689 "i2so2_hop_ck", 690 "i2so3_hop_ck", 691 "i2si0_hop_ck", 692 "i2si1_hop_ck", 693 "i2si2_hop_ck", 694 "i2si3_hop_ck", 695 "asrc0_out_ck", 696 "asrc1_out_ck", 697 "asrc2_out_ck", 698 "asrc3_out_ck", 699 "audio_afe_pd", 700 "audio_afe_conn_pd", 701 "audio_a1sys_pd", 702 "audio_a2sys_pd", 703 "audio_mrgif_pd"; 704 705 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, 706 <&topckgen CLK_TOP_AUD_MUX2_SEL>, 707 <&topckgen CLK_TOP_AUD_MUX1_DIV>, 708 <&topckgen CLK_TOP_AUD_MUX2_DIV>; 709 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, 710 <&topckgen CLK_TOP_AUD2PLL_90M>; 711 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; 712 }; 713 }; 714 715 mmc0: mmc@11230000 { 716 compatible = "mediatek,mt7623-mmc", 717 "mediatek,mt2701-mmc"; 718 reg = <0 0x11230000 0 0x1000>; 719 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; 720 clocks = <&pericfg CLK_PERI_MSDC30_0>, 721 <&topckgen CLK_TOP_MSDC30_0_SEL>; 722 clock-names = "source", "hclk"; 723 status = "disabled"; 724 }; 725 726 mmc1: mmc@11240000 { 727 compatible = "mediatek,mt7623-mmc", 728 "mediatek,mt2701-mmc"; 729 reg = <0 0x11240000 0 0x1000>; 730 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>; 731 clocks = <&pericfg CLK_PERI_MSDC30_1>, 732 <&topckgen CLK_TOP_MSDC30_1_SEL>; 733 clock-names = "source", "hclk"; 734 status = "disabled"; 735 }; 736 737 vdecsys: syscon@16000000 { 738 compatible = "mediatek,mt7623-vdecsys", 739 "mediatek,mt2701-vdecsys", 740 "syscon"; 741 reg = <0 0x16000000 0 0x1000>; 742 #clock-cells = <1>; 743 }; 744 745 hifsys: syscon@1a000000 { 746 compatible = "mediatek,mt7623-hifsys", 747 "mediatek,mt2701-hifsys", 748 "syscon"; 749 reg = <0 0x1a000000 0 0x1000>; 750 #clock-cells = <1>; 751 #reset-cells = <1>; 752 }; 753 754 pcie: pcie@1a140000 { 755 compatible = "mediatek,mt7623-pcie"; 756 device_type = "pci"; 757 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ 758 <0 0x1a142000 0 0x1000>, /* Port0 registers */ 759 <0 0x1a143000 0 0x1000>, /* Port1 registers */ 760 <0 0x1a144000 0 0x1000>; /* Port2 registers */ 761 reg-names = "subsys", "port0", "port1", "port2"; 762 #address-cells = <3>; 763 #size-cells = <2>; 764 #interrupt-cells = <1>; 765 interrupt-map-mask = <0xf800 0 0 0>; 766 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, 767 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, 768 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 769 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 770 <&hifsys CLK_HIFSYS_PCIE0>, 771 <&hifsys CLK_HIFSYS_PCIE1>, 772 <&hifsys CLK_HIFSYS_PCIE2>; 773 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; 774 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, 775 <&hifsys MT2701_HIFSYS_PCIE1_RST>, 776 <&hifsys MT2701_HIFSYS_PCIE2_RST>; 777 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; 778 phys = <&pcie0_port PHY_TYPE_PCIE>, 779 <&pcie1_port PHY_TYPE_PCIE>, 780 <&u3port1 PHY_TYPE_PCIE>; 781 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; 782 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 783 bus-range = <0x00 0xff>; 784 status = "disabled"; 785 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 786 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; 787 788 pcie@0,0 { 789 reg = <0x0000 0 0 0 0>; 790 #address-cells = <3>; 791 #size-cells = <2>; 792 #interrupt-cells = <1>; 793 interrupt-map-mask = <0 0 0 0>; 794 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 795 ranges; 796 status = "disabled"; 797 }; 798 799 pcie@1,0 { 800 reg = <0x0800 0 0 0 0>; 801 #address-cells = <3>; 802 #size-cells = <2>; 803 #interrupt-cells = <1>; 804 interrupt-map-mask = <0 0 0 0>; 805 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 806 ranges; 807 status = "disabled"; 808 }; 809 810 pcie@2,0 { 811 reg = <0x1000 0 0 0 0>; 812 #address-cells = <3>; 813 #size-cells = <2>; 814 #interrupt-cells = <1>; 815 interrupt-map-mask = <0 0 0 0>; 816 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 817 ranges; 818 status = "disabled"; 819 }; 820 }; 821 822 pcie0_phy: t-phy@1a149000 { 823 compatible = "mediatek,mt7623-tphy", 824 "mediatek,generic-tphy-v1"; 825 reg = <0 0x1a149000 0 0x0700>; 826 #address-cells = <2>; 827 #size-cells = <2>; 828 ranges; 829 status = "disabled"; 830 831 pcie0_port: pcie-phy@1a149900 { 832 reg = <0 0x1a149900 0 0x0700>; 833 clocks = <&clk26m>; 834 clock-names = "ref"; 835 #phy-cells = <1>; 836 status = "okay"; 837 }; 838 }; 839 840 pcie1_phy: t-phy@1a14a000 { 841 compatible = "mediatek,mt7623-tphy", 842 "mediatek,generic-tphy-v1"; 843 reg = <0 0x1a14a000 0 0x0700>; 844 #address-cells = <2>; 845 #size-cells = <2>; 846 ranges; 847 status = "disabled"; 848 849 pcie1_port: pcie-phy@1a14a900 { 850 reg = <0 0x1a14a900 0 0x0700>; 851 clocks = <&clk26m>; 852 clock-names = "ref"; 853 #phy-cells = <1>; 854 status = "okay"; 855 }; 856 }; 857 858 usb1: usb@1a1c0000 { 859 compatible = "mediatek,mt7623-xhci", 860 "mediatek,mtk-xhci"; 861 reg = <0 0x1a1c0000 0 0x1000>, 862 <0 0x1a1c4700 0 0x0100>; 863 reg-names = "mac", "ippc"; 864 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; 865 clocks = <&hifsys CLK_HIFSYS_USB0PHY>, 866 <&topckgen CLK_TOP_ETHIF_SEL>; 867 clock-names = "sys_ck", "ref_ck"; 868 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 869 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 870 status = "disabled"; 871 }; 872 873 u3phy1: t-phy@1a1c4000 { 874 compatible = "mediatek,mt7623-tphy", 875 "mediatek,generic-tphy-v1"; 876 reg = <0 0x1a1c4000 0 0x0700>; 877 #address-cells = <2>; 878 #size-cells = <2>; 879 ranges; 880 status = "disabled"; 881 882 u2port0: usb-phy@1a1c4800 { 883 reg = <0 0x1a1c4800 0 0x0100>; 884 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 885 clock-names = "ref"; 886 #phy-cells = <1>; 887 status = "okay"; 888 }; 889 890 u3port0: usb-phy@1a1c4900 { 891 reg = <0 0x1a1c4900 0 0x0700>; 892 clocks = <&clk26m>; 893 clock-names = "ref"; 894 #phy-cells = <1>; 895 status = "okay"; 896 }; 897 }; 898 899 usb2: usb@1a240000 { 900 compatible = "mediatek,mt7623-xhci", 901 "mediatek,mtk-xhci"; 902 reg = <0 0x1a240000 0 0x1000>, 903 <0 0x1a244700 0 0x0100>; 904 reg-names = "mac", "ippc"; 905 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 906 clocks = <&hifsys CLK_HIFSYS_USB1PHY>, 907 <&topckgen CLK_TOP_ETHIF_SEL>; 908 clock-names = "sys_ck", "ref_ck"; 909 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 910 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 911 status = "disabled"; 912 }; 913 914 u3phy2: t-phy@1a244000 { 915 compatible = "mediatek,mt7623-tphy", 916 "mediatek,generic-tphy-v1"; 917 reg = <0 0x1a244000 0 0x0700>; 918 #address-cells = <2>; 919 #size-cells = <2>; 920 ranges; 921 status = "disabled"; 922 923 u2port1: usb-phy@1a244800 { 924 reg = <0 0x1a244800 0 0x0100>; 925 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 926 clock-names = "ref"; 927 #phy-cells = <1>; 928 status = "okay"; 929 }; 930 931 u3port1: usb-phy@1a244900 { 932 reg = <0 0x1a244900 0 0x0700>; 933 clocks = <&clk26m>; 934 clock-names = "ref"; 935 #phy-cells = <1>; 936 status = "okay"; 937 }; 938 }; 939 940 ethsys: syscon@1b000000 { 941 compatible = "mediatek,mt7623-ethsys", 942 "mediatek,mt2701-ethsys", 943 "syscon"; 944 reg = <0 0x1b000000 0 0x1000>; 945 #clock-cells = <1>; 946 #reset-cells = <1>; 947 }; 948 949 hsdma: dma-controller@1b007000 { 950 compatible = "mediatek,mt7623-hsdma"; 951 reg = <0 0x1b007000 0 0x1000>; 952 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>; 953 clocks = <ðsys CLK_ETHSYS_HSDMA>; 954 clock-names = "hsdma"; 955 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 956 #dma-cells = <1>; 957 }; 958 959 eth: ethernet@1b100000 { 960 compatible = "mediatek,mt7623-eth", 961 "mediatek,mt2701-eth", 962 "syscon"; 963 reg = <0 0x1b100000 0 0x20000>; 964 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>, 965 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>, 966 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 967 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 968 <ðsys CLK_ETHSYS_ESW>, 969 <ðsys CLK_ETHSYS_GP1>, 970 <ðsys CLK_ETHSYS_GP2>, 971 <&apmixedsys CLK_APMIXED_TRGPLL>; 972 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; 973 resets = <ðsys MT2701_ETHSYS_FE_RST>, 974 <ðsys MT2701_ETHSYS_GMAC_RST>, 975 <ðsys MT2701_ETHSYS_PPE_RST>; 976 reset-names = "fe", "gmac", "ppe"; 977 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 978 mediatek,ethsys = <ðsys>; 979 mediatek,pctl = <&syscfg_pctl_a>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 status = "disabled"; 983 984 gmac0: mac@0 { 985 compatible = "mediatek,eth-mac"; 986 reg = <0>; 987 status = "disabled"; 988 }; 989 990 gmac1: mac@1 { 991 compatible = "mediatek,eth-mac"; 992 reg = <1>; 993 status = "disabled"; 994 }; 995 }; 996 997 crypto: crypto@1b240000 { 998 compatible = "mediatek,eip97-crypto"; 999 reg = <0 0x1b240000 0 0x20000>; 1000 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, 1001 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, 1002 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, 1003 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, 1004 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 1005 clocks = <ðsys CLK_ETHSYS_CRYPTO>; 1006 clock-names = "cryp"; 1007 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 1008 status = "disabled"; 1009 }; 1010 1011 bdpsys: syscon@1c000000 { 1012 compatible = "mediatek,mt7623-bdpsys", 1013 "mediatek,mt2701-bdpsys", 1014 "syscon"; 1015 reg = <0 0x1c000000 0 0x1000>; 1016 #clock-cells = <1>; 1017 }; 1018}; 1019 1020&pio { 1021 cir_pins_a:cir-default { 1022 pins-cir { 1023 pinmux = <MT7623_PIN_46_IR_FUNC_IR>; 1024 bias-disable; 1025 }; 1026 }; 1027 1028 i2c0_pins_a: i2c0-default { 1029 pins-i2c0 { 1030 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, 1031 <MT7623_PIN_76_SCL0_FUNC_SCL0>; 1032 bias-disable; 1033 }; 1034 }; 1035 1036 i2c1_pins_a: i2c1-default { 1037 pin-i2c1 { 1038 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, 1039 <MT7623_PIN_58_SCL1_FUNC_SCL1>; 1040 bias-disable; 1041 }; 1042 }; 1043 1044 i2c1_pins_b: i2c1-alt { 1045 pin-i2c1 { 1046 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>, 1047 <MT7623_PIN_243_UCTS2_FUNC_SDA1>; 1048 bias-disable; 1049 }; 1050 }; 1051 1052 i2c2_pins_a: i2c2-default { 1053 pin-i2c2 { 1054 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>, 1055 <MT7623_PIN_78_SCL2_FUNC_SCL2>; 1056 bias-disable; 1057 }; 1058 }; 1059 1060 i2c2_pins_b: i2c2-alt { 1061 pin-i2c2 { 1062 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>, 1063 <MT7623_PIN_123_HTPLG_FUNC_SCL2>; 1064 bias-disable; 1065 }; 1066 }; 1067 1068 i2s0_pins_a: i2s0-default { 1069 pin-i2s0 { 1070 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, 1071 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, 1072 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, 1073 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>, 1074 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>; 1075 drive-strength = <MTK_DRIVE_12mA>; 1076 bias-pull-down; 1077 }; 1078 }; 1079 1080 i2s1_pins_a: i2s1-default { 1081 pin-i2s1 { 1082 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, 1083 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, 1084 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, 1085 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>, 1086 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>; 1087 drive-strength = <MTK_DRIVE_12mA>; 1088 bias-pull-down; 1089 }; 1090 }; 1091 1092 key_pins_a: keys-alt { 1093 pins-keys { 1094 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, 1095 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ; 1096 input-enable; 1097 }; 1098 }; 1099 1100 led_pins_a: leds-alt { 1101 pins-leds { 1102 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>, 1103 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>, 1104 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>; 1105 }; 1106 }; 1107 1108 mmc0_pins_default: mmc0default { 1109 pins-cmd-dat { 1110 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, 1111 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, 1112 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, 1113 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, 1114 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, 1115 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, 1116 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, 1117 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, 1118 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; 1119 input-enable; 1120 bias-pull-up; 1121 }; 1122 1123 pins-clk { 1124 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; 1125 bias-pull-down; 1126 }; 1127 1128 pins-rst { 1129 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; 1130 bias-pull-up; 1131 }; 1132 }; 1133 1134 mmc0_pins_uhs: mmc0 { 1135 pins-cmd-dat { 1136 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, 1137 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, 1138 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, 1139 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, 1140 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, 1141 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, 1142 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, 1143 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, 1144 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; 1145 input-enable; 1146 drive-strength = <MTK_DRIVE_2mA>; 1147 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1148 }; 1149 1150 pins-clk { 1151 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; 1152 drive-strength = <MTK_DRIVE_2mA>; 1153 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1154 }; 1155 1156 pins-rst { 1157 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; 1158 bias-pull-up; 1159 }; 1160 }; 1161 1162 mmc1_pins_default: mmc1default { 1163 pins-cmd-dat { 1164 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, 1165 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, 1166 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, 1167 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, 1168 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; 1169 input-enable; 1170 drive-strength = <MTK_DRIVE_4mA>; 1171 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1172 }; 1173 1174 pins-clk { 1175 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; 1176 bias-pull-down; 1177 drive-strength = <MTK_DRIVE_4mA>; 1178 }; 1179 1180 pins-wp { 1181 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>; 1182 input-enable; 1183 bias-pull-up; 1184 }; 1185 1186 pins-insert { 1187 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>; 1188 bias-pull-up; 1189 }; 1190 }; 1191 1192 mmc1_pins_uhs: mmc1 { 1193 pins-cmd-dat { 1194 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, 1195 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, 1196 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, 1197 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, 1198 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; 1199 input-enable; 1200 drive-strength = <MTK_DRIVE_4mA>; 1201 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1202 }; 1203 1204 pins-clk { 1205 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; 1206 drive-strength = <MTK_DRIVE_4mA>; 1207 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1208 }; 1209 }; 1210 1211 nand_pins_default: nanddefault { 1212 pins-ale { 1213 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>; 1214 drive-strength = <MTK_DRIVE_8mA>; 1215 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1216 }; 1217 1218 pins-dat { 1219 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>, 1220 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>, 1221 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>, 1222 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>, 1223 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>, 1224 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>, 1225 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>, 1226 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>, 1227 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>; 1228 input-enable; 1229 drive-strength = <MTK_DRIVE_8mA>; 1230 bias-pull-up; 1231 }; 1232 1233 pins-we { 1234 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>; 1235 drive-strength = <MTK_DRIVE_8mA>; 1236 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1237 }; 1238 }; 1239 1240 pcie_default: pcie_pin_default { 1241 pins_cmd_dat { 1242 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, 1243 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; 1244 bias-disable; 1245 }; 1246 }; 1247 1248 pwm_pins_a: pwm-default { 1249 pins-pwm { 1250 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, 1251 <MT7623_PIN_204_PWM1_FUNC_PWM1>, 1252 <MT7623_PIN_205_PWM2_FUNC_PWM2>, 1253 <MT7623_PIN_206_PWM3_FUNC_PWM3>, 1254 <MT7623_PIN_207_PWM4_FUNC_PWM4>; 1255 }; 1256 }; 1257 1258 spi0_pins_a: spi0-default { 1259 pins-spi { 1260 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, 1261 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, 1262 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>, 1263 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>; 1264 bias-disable; 1265 }; 1266 }; 1267 1268 spi1_pins_a: spi1-default { 1269 pins-spi { 1270 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>, 1271 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>, 1272 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>, 1273 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>; 1274 }; 1275 }; 1276 1277 spi2_pins_a: spi2-default { 1278 pins-spi { 1279 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>, 1280 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>, 1281 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>, 1282 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>; 1283 }; 1284 }; 1285 1286 uart0_pins_a: uart0-default { 1287 pins-dat { 1288 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, 1289 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; 1290 }; 1291 }; 1292 1293 uart1_pins_a: uart1-default { 1294 pins-dat { 1295 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, 1296 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; 1297 }; 1298 }; 1299 1300 uart2_pins_a: uart2-default { 1301 pins-dat { 1302 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>, 1303 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>; 1304 }; 1305 }; 1306 1307 uart2_pins_b: uart2-alt { 1308 pins-dat { 1309 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>, 1310 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>; 1311 }; 1312 }; 1313}; 1314