1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Howard Chen <ibanezchen@gmail.com> 5 * 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 compatible = "mediatek,mt6592"; 15 interrupt-parent = <&sysirq>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a7"; 24 reg = <0x0>; 25 }; 26 cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a7"; 29 reg = <0x1>; 30 }; 31 cpu@2 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0x2>; 35 }; 36 cpu@3 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a7"; 39 reg = <0x3>; 40 }; 41 cpu@4 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a7"; 44 reg = <0x4>; 45 }; 46 cpu@5 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0x5>; 50 }; 51 cpu@6 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0x6>; 55 }; 56 cpu@7 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a7"; 59 reg = <0x7>; 60 }; 61 }; 62 63 system_clk: dummy13m { 64 compatible = "fixed-clock"; 65 clock-frequency = <13000000>; 66 #clock-cells = <0>; 67 }; 68 69 rtc_clk: dummy32k { 70 compatible = "fixed-clock"; 71 clock-frequency = <32000>; 72 #clock-cells = <0>; 73 }; 74 75 uart_clk: dummy26m { 76 compatible = "fixed-clock"; 77 clock-frequency = <26000000>; 78 #clock-cells = <0>; 79 }; 80 81 timer: timer@10008000 { 82 compatible = "mediatek,mt6577-timer"; 83 reg = <0x10008000 0x80>; 84 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 85 clocks = <&system_clk>, <&rtc_clk>; 86 clock-names = "system-clk", "rtc-clk"; 87 }; 88 89 sysirq: interrupt-controller@10200220 { 90 compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; 91 interrupt-controller; 92 #interrupt-cells = <3>; 93 interrupt-parent = <&gic>; 94 reg = <0x10200220 0x1c>; 95 }; 96 97 gic: interrupt-controller@10211000 { 98 compatible = "arm,cortex-a7-gic"; 99 interrupt-controller; 100 #interrupt-cells = <3>; 101 interrupt-parent = <&gic>; 102 reg = <0x10211000 0x1000>, 103 <0x10212000 0x1000>; 104 }; 105 106 uart0: serial@11002000 { 107 compatible = "mediatek,mt6577-uart"; 108 reg = <0x11002000 0x400>; 109 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 110 clocks = <&uart_clk>; 111 status = "disabled"; 112 }; 113 114 uart1: serial@11003000 { 115 compatible = "mediatek,mt6577-uart"; 116 reg = <0x11003000 0x400>; 117 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 118 clocks = <&uart_clk>; 119 status = "disabled"; 120 }; 121 122 uart2: serial@11004000 { 123 compatible = "mediatek,mt6577-uart"; 124 reg = <0x11004000 0x400>; 125 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 126 clocks = <&uart_clk>; 127 status = "disabled"; 128 }; 129 130 uart3: serial@11005000 { 131 compatible = "mediatek,mt6577-uart"; 132 reg = <0x11005000 0x400>; 133 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 134 clocks = <&uart_clk>; 135 status = "disabled"; 136 }; 137}; 138