xref: /freebsd/sys/contrib/device-tree/src/arm/mediatek/mt2701-pinfunc.h (revision f126890ac5386406dadf7c4cfa9566cbb56537c5)
1*f126890aSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */
2*f126890aSEmmanuel Vadot /*
3*f126890aSEmmanuel Vadot  * Copyright (c) 2015 MediaTek Inc.
4*f126890aSEmmanuel Vadot  * Author: Biao Huang <biao.huang@mediatek.com>
5*f126890aSEmmanuel Vadot  */
6*f126890aSEmmanuel Vadot 
7*f126890aSEmmanuel Vadot #ifndef __DTS_MT2701_PINFUNC_H
8*f126890aSEmmanuel Vadot #define __DTS_MT2701_PINFUNC_H
9*f126890aSEmmanuel Vadot 
10*f126890aSEmmanuel Vadot #include <dt-bindings/pinctrl/mt65xx.h>
11*f126890aSEmmanuel Vadot 
12*f126890aSEmmanuel Vadot #define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
13*f126890aSEmmanuel Vadot #define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
14*f126890aSEmmanuel Vadot #define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
15*f126890aSEmmanuel Vadot 
16*f126890aSEmmanuel Vadot #define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
17*f126890aSEmmanuel Vadot #define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
18*f126890aSEmmanuel Vadot #define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
19*f126890aSEmmanuel Vadot 
20*f126890aSEmmanuel Vadot #define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
21*f126890aSEmmanuel Vadot #define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
22*f126890aSEmmanuel Vadot 
23*f126890aSEmmanuel Vadot #define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
24*f126890aSEmmanuel Vadot #define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
25*f126890aSEmmanuel Vadot 
26*f126890aSEmmanuel Vadot #define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
27*f126890aSEmmanuel Vadot #define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
28*f126890aSEmmanuel Vadot 
29*f126890aSEmmanuel Vadot #define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
30*f126890aSEmmanuel Vadot #define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
31*f126890aSEmmanuel Vadot #define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
32*f126890aSEmmanuel Vadot 
33*f126890aSEmmanuel Vadot #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
34*f126890aSEmmanuel Vadot #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
35*f126890aSEmmanuel Vadot #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
36*f126890aSEmmanuel Vadot #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
37*f126890aSEmmanuel Vadot 
38*f126890aSEmmanuel Vadot #define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
39*f126890aSEmmanuel Vadot #define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
40*f126890aSEmmanuel Vadot #define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
41*f126890aSEmmanuel Vadot #define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
42*f126890aSEmmanuel Vadot 
43*f126890aSEmmanuel Vadot #define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
44*f126890aSEmmanuel Vadot #define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
45*f126890aSEmmanuel Vadot #define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
46*f126890aSEmmanuel Vadot #define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
47*f126890aSEmmanuel Vadot #define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
48*f126890aSEmmanuel Vadot 
49*f126890aSEmmanuel Vadot #define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
50*f126890aSEmmanuel Vadot #define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
51*f126890aSEmmanuel Vadot #define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
52*f126890aSEmmanuel Vadot #define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
53*f126890aSEmmanuel Vadot #define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
54*f126890aSEmmanuel Vadot #define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
55*f126890aSEmmanuel Vadot 
56*f126890aSEmmanuel Vadot #define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
57*f126890aSEmmanuel Vadot #define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
58*f126890aSEmmanuel Vadot 
59*f126890aSEmmanuel Vadot #define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
60*f126890aSEmmanuel Vadot #define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
61*f126890aSEmmanuel Vadot 
62*f126890aSEmmanuel Vadot #define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
63*f126890aSEmmanuel Vadot #define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
64*f126890aSEmmanuel Vadot 
65*f126890aSEmmanuel Vadot #define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
66*f126890aSEmmanuel Vadot #define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
67*f126890aSEmmanuel Vadot 
68*f126890aSEmmanuel Vadot #define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
69*f126890aSEmmanuel Vadot #define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
70*f126890aSEmmanuel Vadot #define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
71*f126890aSEmmanuel Vadot #define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
72*f126890aSEmmanuel Vadot #define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
73*f126890aSEmmanuel Vadot 
74*f126890aSEmmanuel Vadot #define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
75*f126890aSEmmanuel Vadot #define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
76*f126890aSEmmanuel Vadot #define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
77*f126890aSEmmanuel Vadot #define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
78*f126890aSEmmanuel Vadot 
79*f126890aSEmmanuel Vadot #define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
80*f126890aSEmmanuel Vadot #define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
81*f126890aSEmmanuel Vadot #define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
82*f126890aSEmmanuel Vadot #define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
83*f126890aSEmmanuel Vadot #define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
84*f126890aSEmmanuel Vadot #define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
85*f126890aSEmmanuel Vadot #define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
86*f126890aSEmmanuel Vadot 
87*f126890aSEmmanuel Vadot #define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
88*f126890aSEmmanuel Vadot #define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
89*f126890aSEmmanuel Vadot #define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
90*f126890aSEmmanuel Vadot #define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
91*f126890aSEmmanuel Vadot #define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
92*f126890aSEmmanuel Vadot #define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
93*f126890aSEmmanuel Vadot 
94*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
95*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
96*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
97*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
98*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
99*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
100*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
101*f126890aSEmmanuel Vadot #define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
102*f126890aSEmmanuel Vadot 
103*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
104*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
105*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
106*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
107*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
108*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
109*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
110*f126890aSEmmanuel Vadot #define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
111*f126890aSEmmanuel Vadot 
112*f126890aSEmmanuel Vadot #define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
113*f126890aSEmmanuel Vadot #define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
114*f126890aSEmmanuel Vadot #define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
115*f126890aSEmmanuel Vadot #define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
116*f126890aSEmmanuel Vadot #define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
117*f126890aSEmmanuel Vadot #define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
118*f126890aSEmmanuel Vadot #define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
119*f126890aSEmmanuel Vadot 
120*f126890aSEmmanuel Vadot #define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
121*f126890aSEmmanuel Vadot #define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
122*f126890aSEmmanuel Vadot #define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
123*f126890aSEmmanuel Vadot #define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
124*f126890aSEmmanuel Vadot #define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
125*f126890aSEmmanuel Vadot #define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
126*f126890aSEmmanuel Vadot #define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
127*f126890aSEmmanuel Vadot 
128*f126890aSEmmanuel Vadot #define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
129*f126890aSEmmanuel Vadot #define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
130*f126890aSEmmanuel Vadot #define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
131*f126890aSEmmanuel Vadot #define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
132*f126890aSEmmanuel Vadot #define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
133*f126890aSEmmanuel Vadot #define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
134*f126890aSEmmanuel Vadot 
135*f126890aSEmmanuel Vadot #define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
136*f126890aSEmmanuel Vadot #define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
137*f126890aSEmmanuel Vadot #define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
138*f126890aSEmmanuel Vadot #define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
139*f126890aSEmmanuel Vadot #define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
140*f126890aSEmmanuel Vadot 
141*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
142*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
143*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
144*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
145*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
146*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
147*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
148*f126890aSEmmanuel Vadot #define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
149*f126890aSEmmanuel Vadot 
150*f126890aSEmmanuel Vadot #define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
151*f126890aSEmmanuel Vadot #define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
152*f126890aSEmmanuel Vadot #define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
153*f126890aSEmmanuel Vadot #define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
154*f126890aSEmmanuel Vadot #define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
155*f126890aSEmmanuel Vadot #define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
156*f126890aSEmmanuel Vadot #define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
157*f126890aSEmmanuel Vadot 
158*f126890aSEmmanuel Vadot #define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
159*f126890aSEmmanuel Vadot #define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
160*f126890aSEmmanuel Vadot #define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
161*f126890aSEmmanuel Vadot #define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
162*f126890aSEmmanuel Vadot #define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
163*f126890aSEmmanuel Vadot #define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
164*f126890aSEmmanuel Vadot 
165*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
166*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
167*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
168*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
169*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
170*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
171*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
172*f126890aSEmmanuel Vadot #define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
173*f126890aSEmmanuel Vadot 
174*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
175*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
176*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
177*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
178*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
179*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
180*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
181*f126890aSEmmanuel Vadot #define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
182*f126890aSEmmanuel Vadot 
183*f126890aSEmmanuel Vadot #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
184*f126890aSEmmanuel Vadot #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
185*f126890aSEmmanuel Vadot #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
186*f126890aSEmmanuel Vadot #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
187*f126890aSEmmanuel Vadot #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
188*f126890aSEmmanuel Vadot #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
189*f126890aSEmmanuel Vadot #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
190*f126890aSEmmanuel Vadot 
191*f126890aSEmmanuel Vadot #define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
192*f126890aSEmmanuel Vadot #define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
193*f126890aSEmmanuel Vadot #define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
194*f126890aSEmmanuel Vadot #define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
195*f126890aSEmmanuel Vadot #define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
196*f126890aSEmmanuel Vadot #define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
197*f126890aSEmmanuel Vadot 
198*f126890aSEmmanuel Vadot #define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
199*f126890aSEmmanuel Vadot #define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
200*f126890aSEmmanuel Vadot #define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
201*f126890aSEmmanuel Vadot #define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
202*f126890aSEmmanuel Vadot #define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
203*f126890aSEmmanuel Vadot #define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
204*f126890aSEmmanuel Vadot 
205*f126890aSEmmanuel Vadot #define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
206*f126890aSEmmanuel Vadot #define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
207*f126890aSEmmanuel Vadot #define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
208*f126890aSEmmanuel Vadot #define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
209*f126890aSEmmanuel Vadot 
210*f126890aSEmmanuel Vadot #define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
211*f126890aSEmmanuel Vadot #define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
212*f126890aSEmmanuel Vadot #define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
213*f126890aSEmmanuel Vadot #define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
214*f126890aSEmmanuel Vadot #define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
215*f126890aSEmmanuel Vadot 
216*f126890aSEmmanuel Vadot #define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
217*f126890aSEmmanuel Vadot #define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
218*f126890aSEmmanuel Vadot #define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
219*f126890aSEmmanuel Vadot #define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
220*f126890aSEmmanuel Vadot #define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
221*f126890aSEmmanuel Vadot 
222*f126890aSEmmanuel Vadot #define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
223*f126890aSEmmanuel Vadot #define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
224*f126890aSEmmanuel Vadot #define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
225*f126890aSEmmanuel Vadot #define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
226*f126890aSEmmanuel Vadot 
227*f126890aSEmmanuel Vadot #define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
228*f126890aSEmmanuel Vadot #define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
229*f126890aSEmmanuel Vadot #define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
230*f126890aSEmmanuel Vadot #define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
231*f126890aSEmmanuel Vadot 
232*f126890aSEmmanuel Vadot #define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
233*f126890aSEmmanuel Vadot #define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
234*f126890aSEmmanuel Vadot #define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
235*f126890aSEmmanuel Vadot 
236*f126890aSEmmanuel Vadot #define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
237*f126890aSEmmanuel Vadot #define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
238*f126890aSEmmanuel Vadot #define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
239*f126890aSEmmanuel Vadot 
240*f126890aSEmmanuel Vadot #define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
241*f126890aSEmmanuel Vadot #define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
242*f126890aSEmmanuel Vadot #define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
243*f126890aSEmmanuel Vadot 
244*f126890aSEmmanuel Vadot #define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
245*f126890aSEmmanuel Vadot #define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
246*f126890aSEmmanuel Vadot 
247*f126890aSEmmanuel Vadot #define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
248*f126890aSEmmanuel Vadot #define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
249*f126890aSEmmanuel Vadot #define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
250*f126890aSEmmanuel Vadot 
251*f126890aSEmmanuel Vadot #define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
252*f126890aSEmmanuel Vadot #define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
253*f126890aSEmmanuel Vadot #define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
254*f126890aSEmmanuel Vadot 
255*f126890aSEmmanuel Vadot #define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
256*f126890aSEmmanuel Vadot #define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
257*f126890aSEmmanuel Vadot #define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
258*f126890aSEmmanuel Vadot #define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
259*f126890aSEmmanuel Vadot #define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
260*f126890aSEmmanuel Vadot #define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
261*f126890aSEmmanuel Vadot 
262*f126890aSEmmanuel Vadot #define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
263*f126890aSEmmanuel Vadot #define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
264*f126890aSEmmanuel Vadot #define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
265*f126890aSEmmanuel Vadot #define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
266*f126890aSEmmanuel Vadot #define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
267*f126890aSEmmanuel Vadot #define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
268*f126890aSEmmanuel Vadot 
269*f126890aSEmmanuel Vadot #define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
270*f126890aSEmmanuel Vadot #define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
271*f126890aSEmmanuel Vadot #define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
272*f126890aSEmmanuel Vadot #define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
273*f126890aSEmmanuel Vadot #define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
274*f126890aSEmmanuel Vadot 
275*f126890aSEmmanuel Vadot #define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
276*f126890aSEmmanuel Vadot #define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
277*f126890aSEmmanuel Vadot #define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
278*f126890aSEmmanuel Vadot #define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
279*f126890aSEmmanuel Vadot #define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
280*f126890aSEmmanuel Vadot #define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
281*f126890aSEmmanuel Vadot #define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
282*f126890aSEmmanuel Vadot 
283*f126890aSEmmanuel Vadot #define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
284*f126890aSEmmanuel Vadot #define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
285*f126890aSEmmanuel Vadot #define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
286*f126890aSEmmanuel Vadot #define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
287*f126890aSEmmanuel Vadot #define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
288*f126890aSEmmanuel Vadot 
289*f126890aSEmmanuel Vadot #define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
290*f126890aSEmmanuel Vadot #define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
291*f126890aSEmmanuel Vadot 
292*f126890aSEmmanuel Vadot #define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
293*f126890aSEmmanuel Vadot #define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
294*f126890aSEmmanuel Vadot 
295*f126890aSEmmanuel Vadot #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
296*f126890aSEmmanuel Vadot #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
297*f126890aSEmmanuel Vadot #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
298*f126890aSEmmanuel Vadot #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
299*f126890aSEmmanuel Vadot #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
300*f126890aSEmmanuel Vadot #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
301*f126890aSEmmanuel Vadot #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
302*f126890aSEmmanuel Vadot 
303*f126890aSEmmanuel Vadot #define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
304*f126890aSEmmanuel Vadot #define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
305*f126890aSEmmanuel Vadot #define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
306*f126890aSEmmanuel Vadot #define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
307*f126890aSEmmanuel Vadot #define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
308*f126890aSEmmanuel Vadot 
309*f126890aSEmmanuel Vadot #define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
310*f126890aSEmmanuel Vadot #define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
311*f126890aSEmmanuel Vadot #define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
312*f126890aSEmmanuel Vadot #define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
313*f126890aSEmmanuel Vadot #define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
314*f126890aSEmmanuel Vadot 
315*f126890aSEmmanuel Vadot #define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
316*f126890aSEmmanuel Vadot #define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
317*f126890aSEmmanuel Vadot 
318*f126890aSEmmanuel Vadot #define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
319*f126890aSEmmanuel Vadot #define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
320*f126890aSEmmanuel Vadot 
321*f126890aSEmmanuel Vadot #define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
322*f126890aSEmmanuel Vadot #define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
323*f126890aSEmmanuel Vadot 
324*f126890aSEmmanuel Vadot #define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
325*f126890aSEmmanuel Vadot #define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
326*f126890aSEmmanuel Vadot 
327*f126890aSEmmanuel Vadot #define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
328*f126890aSEmmanuel Vadot #define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
329*f126890aSEmmanuel Vadot #define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
330*f126890aSEmmanuel Vadot #define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
331*f126890aSEmmanuel Vadot 
332*f126890aSEmmanuel Vadot #define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
333*f126890aSEmmanuel Vadot #define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
334*f126890aSEmmanuel Vadot #define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
335*f126890aSEmmanuel Vadot 
336*f126890aSEmmanuel Vadot #define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
337*f126890aSEmmanuel Vadot #define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
338*f126890aSEmmanuel Vadot #define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
339*f126890aSEmmanuel Vadot 
340*f126890aSEmmanuel Vadot #define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
341*f126890aSEmmanuel Vadot #define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
342*f126890aSEmmanuel Vadot #define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
343*f126890aSEmmanuel Vadot 
344*f126890aSEmmanuel Vadot #define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
345*f126890aSEmmanuel Vadot #define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
346*f126890aSEmmanuel Vadot #define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
347*f126890aSEmmanuel Vadot #define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
348*f126890aSEmmanuel Vadot 
349*f126890aSEmmanuel Vadot #define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
350*f126890aSEmmanuel Vadot #define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
351*f126890aSEmmanuel Vadot #define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
352*f126890aSEmmanuel Vadot 
353*f126890aSEmmanuel Vadot #define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
354*f126890aSEmmanuel Vadot #define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
355*f126890aSEmmanuel Vadot 
356*f126890aSEmmanuel Vadot #define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
357*f126890aSEmmanuel Vadot #define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
358*f126890aSEmmanuel Vadot 
359*f126890aSEmmanuel Vadot #define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
360*f126890aSEmmanuel Vadot #define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
361*f126890aSEmmanuel Vadot 
362*f126890aSEmmanuel Vadot #define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
363*f126890aSEmmanuel Vadot #define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
364*f126890aSEmmanuel Vadot 
365*f126890aSEmmanuel Vadot #define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
366*f126890aSEmmanuel Vadot #define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
367*f126890aSEmmanuel Vadot 
368*f126890aSEmmanuel Vadot #define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
369*f126890aSEmmanuel Vadot #define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
370*f126890aSEmmanuel Vadot 
371*f126890aSEmmanuel Vadot #define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
372*f126890aSEmmanuel Vadot #define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
373*f126890aSEmmanuel Vadot 
374*f126890aSEmmanuel Vadot #define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
375*f126890aSEmmanuel Vadot #define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
376*f126890aSEmmanuel Vadot 
377*f126890aSEmmanuel Vadot #define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
378*f126890aSEmmanuel Vadot #define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
379*f126890aSEmmanuel Vadot 
380*f126890aSEmmanuel Vadot #define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
381*f126890aSEmmanuel Vadot #define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
382*f126890aSEmmanuel Vadot 
383*f126890aSEmmanuel Vadot #define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
384*f126890aSEmmanuel Vadot #define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
385*f126890aSEmmanuel Vadot #define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
386*f126890aSEmmanuel Vadot #define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
387*f126890aSEmmanuel Vadot 
388*f126890aSEmmanuel Vadot #define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
389*f126890aSEmmanuel Vadot #define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
390*f126890aSEmmanuel Vadot #define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
391*f126890aSEmmanuel Vadot #define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
392*f126890aSEmmanuel Vadot #define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
393*f126890aSEmmanuel Vadot 
394*f126890aSEmmanuel Vadot #define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
395*f126890aSEmmanuel Vadot #define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
396*f126890aSEmmanuel Vadot #define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
397*f126890aSEmmanuel Vadot #define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
398*f126890aSEmmanuel Vadot #define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
399*f126890aSEmmanuel Vadot 
400*f126890aSEmmanuel Vadot #define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
401*f126890aSEmmanuel Vadot #define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
402*f126890aSEmmanuel Vadot #define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
403*f126890aSEmmanuel Vadot #define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
404*f126890aSEmmanuel Vadot 
405*f126890aSEmmanuel Vadot #define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
406*f126890aSEmmanuel Vadot #define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
407*f126890aSEmmanuel Vadot #define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
408*f126890aSEmmanuel Vadot #define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
409*f126890aSEmmanuel Vadot #define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
410*f126890aSEmmanuel Vadot #define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
411*f126890aSEmmanuel Vadot 
412*f126890aSEmmanuel Vadot #define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
413*f126890aSEmmanuel Vadot #define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
414*f126890aSEmmanuel Vadot #define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
415*f126890aSEmmanuel Vadot #define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
416*f126890aSEmmanuel Vadot #define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
417*f126890aSEmmanuel Vadot #define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
418*f126890aSEmmanuel Vadot 
419*f126890aSEmmanuel Vadot #define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
420*f126890aSEmmanuel Vadot #define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
421*f126890aSEmmanuel Vadot #define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
422*f126890aSEmmanuel Vadot #define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
423*f126890aSEmmanuel Vadot #define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
424*f126890aSEmmanuel Vadot #define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
425*f126890aSEmmanuel Vadot 
426*f126890aSEmmanuel Vadot #define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
427*f126890aSEmmanuel Vadot #define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
428*f126890aSEmmanuel Vadot #define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
429*f126890aSEmmanuel Vadot #define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
430*f126890aSEmmanuel Vadot #define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
431*f126890aSEmmanuel Vadot #define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
432*f126890aSEmmanuel Vadot #define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
433*f126890aSEmmanuel Vadot 
434*f126890aSEmmanuel Vadot #define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
435*f126890aSEmmanuel Vadot #define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
436*f126890aSEmmanuel Vadot #define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
437*f126890aSEmmanuel Vadot #define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
438*f126890aSEmmanuel Vadot #define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
439*f126890aSEmmanuel Vadot #define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
440*f126890aSEmmanuel Vadot #define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
441*f126890aSEmmanuel Vadot 
442*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
443*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
444*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
445*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
446*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
447*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
448*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
449*f126890aSEmmanuel Vadot #define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
450*f126890aSEmmanuel Vadot 
451*f126890aSEmmanuel Vadot #define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
452*f126890aSEmmanuel Vadot #define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
453*f126890aSEmmanuel Vadot #define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
454*f126890aSEmmanuel Vadot 
455*f126890aSEmmanuel Vadot #define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
456*f126890aSEmmanuel Vadot #define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
457*f126890aSEmmanuel Vadot #define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
458*f126890aSEmmanuel Vadot 
459*f126890aSEmmanuel Vadot #define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
460*f126890aSEmmanuel Vadot #define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
461*f126890aSEmmanuel Vadot #define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
462*f126890aSEmmanuel Vadot 
463*f126890aSEmmanuel Vadot #define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
464*f126890aSEmmanuel Vadot #define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
465*f126890aSEmmanuel Vadot #define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
466*f126890aSEmmanuel Vadot 
467*f126890aSEmmanuel Vadot #define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
468*f126890aSEmmanuel Vadot #define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
469*f126890aSEmmanuel Vadot #define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
470*f126890aSEmmanuel Vadot 
471*f126890aSEmmanuel Vadot #define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
472*f126890aSEmmanuel Vadot #define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
473*f126890aSEmmanuel Vadot #define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
474*f126890aSEmmanuel Vadot 
475*f126890aSEmmanuel Vadot #define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
476*f126890aSEmmanuel Vadot #define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
477*f126890aSEmmanuel Vadot #define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
478*f126890aSEmmanuel Vadot 
479*f126890aSEmmanuel Vadot #define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
480*f126890aSEmmanuel Vadot #define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
481*f126890aSEmmanuel Vadot #define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
482*f126890aSEmmanuel Vadot 
483*f126890aSEmmanuel Vadot #define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
484*f126890aSEmmanuel Vadot #define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
485*f126890aSEmmanuel Vadot #define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
486*f126890aSEmmanuel Vadot 
487*f126890aSEmmanuel Vadot #define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
488*f126890aSEmmanuel Vadot #define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
489*f126890aSEmmanuel Vadot #define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
490*f126890aSEmmanuel Vadot 
491*f126890aSEmmanuel Vadot #define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
492*f126890aSEmmanuel Vadot #define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
493*f126890aSEmmanuel Vadot #define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
494*f126890aSEmmanuel Vadot #define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
495*f126890aSEmmanuel Vadot 
496*f126890aSEmmanuel Vadot #define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
497*f126890aSEmmanuel Vadot #define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
498*f126890aSEmmanuel Vadot #define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
499*f126890aSEmmanuel Vadot #define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
500*f126890aSEmmanuel Vadot 
501*f126890aSEmmanuel Vadot #define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
502*f126890aSEmmanuel Vadot #define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
503*f126890aSEmmanuel Vadot #define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
504*f126890aSEmmanuel Vadot #define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
505*f126890aSEmmanuel Vadot 
506*f126890aSEmmanuel Vadot #define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
507*f126890aSEmmanuel Vadot #define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
508*f126890aSEmmanuel Vadot #define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
509*f126890aSEmmanuel Vadot #define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
510*f126890aSEmmanuel Vadot 
511*f126890aSEmmanuel Vadot #define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
512*f126890aSEmmanuel Vadot #define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
513*f126890aSEmmanuel Vadot #define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
514*f126890aSEmmanuel Vadot #define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
515*f126890aSEmmanuel Vadot 
516*f126890aSEmmanuel Vadot #define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
517*f126890aSEmmanuel Vadot #define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
518*f126890aSEmmanuel Vadot #define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
519*f126890aSEmmanuel Vadot #define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
520*f126890aSEmmanuel Vadot 
521*f126890aSEmmanuel Vadot #define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
522*f126890aSEmmanuel Vadot #define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
523*f126890aSEmmanuel Vadot #define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
524*f126890aSEmmanuel Vadot #define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
525*f126890aSEmmanuel Vadot #define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
526*f126890aSEmmanuel Vadot 
527*f126890aSEmmanuel Vadot #define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
528*f126890aSEmmanuel Vadot #define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
529*f126890aSEmmanuel Vadot #define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
530*f126890aSEmmanuel Vadot #define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
531*f126890aSEmmanuel Vadot #define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
532*f126890aSEmmanuel Vadot 
533*f126890aSEmmanuel Vadot #define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
534*f126890aSEmmanuel Vadot #define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
535*f126890aSEmmanuel Vadot #define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
536*f126890aSEmmanuel Vadot #define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
537*f126890aSEmmanuel Vadot #define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
538*f126890aSEmmanuel Vadot 
539*f126890aSEmmanuel Vadot #define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
540*f126890aSEmmanuel Vadot #define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
541*f126890aSEmmanuel Vadot 
542*f126890aSEmmanuel Vadot #define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
543*f126890aSEmmanuel Vadot #define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
544*f126890aSEmmanuel Vadot #define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
545*f126890aSEmmanuel Vadot #define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
546*f126890aSEmmanuel Vadot #define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
547*f126890aSEmmanuel Vadot #define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
548*f126890aSEmmanuel Vadot 
549*f126890aSEmmanuel Vadot #define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
550*f126890aSEmmanuel Vadot #define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
551*f126890aSEmmanuel Vadot #define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
552*f126890aSEmmanuel Vadot #define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
553*f126890aSEmmanuel Vadot #define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
554*f126890aSEmmanuel Vadot #define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
555*f126890aSEmmanuel Vadot 
556*f126890aSEmmanuel Vadot #define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
557*f126890aSEmmanuel Vadot #define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
558*f126890aSEmmanuel Vadot #define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
559*f126890aSEmmanuel Vadot #define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
560*f126890aSEmmanuel Vadot #define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
561*f126890aSEmmanuel Vadot 
562*f126890aSEmmanuel Vadot #define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
563*f126890aSEmmanuel Vadot #define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
564*f126890aSEmmanuel Vadot #define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
565*f126890aSEmmanuel Vadot #define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
566*f126890aSEmmanuel Vadot #define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
567*f126890aSEmmanuel Vadot #define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
568*f126890aSEmmanuel Vadot 
569*f126890aSEmmanuel Vadot #define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
570*f126890aSEmmanuel Vadot #define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
571*f126890aSEmmanuel Vadot #define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
572*f126890aSEmmanuel Vadot #define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
573*f126890aSEmmanuel Vadot #define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
574*f126890aSEmmanuel Vadot #define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
575*f126890aSEmmanuel Vadot 
576*f126890aSEmmanuel Vadot #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
577*f126890aSEmmanuel Vadot #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
578*f126890aSEmmanuel Vadot #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
579*f126890aSEmmanuel Vadot #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
580*f126890aSEmmanuel Vadot #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
581*f126890aSEmmanuel Vadot #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
582*f126890aSEmmanuel Vadot #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
583*f126890aSEmmanuel Vadot 
584*f126890aSEmmanuel Vadot #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
585*f126890aSEmmanuel Vadot #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
586*f126890aSEmmanuel Vadot #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
587*f126890aSEmmanuel Vadot #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
588*f126890aSEmmanuel Vadot #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
589*f126890aSEmmanuel Vadot #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
590*f126890aSEmmanuel Vadot 
591*f126890aSEmmanuel Vadot #define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
592*f126890aSEmmanuel Vadot #define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
593*f126890aSEmmanuel Vadot #define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
594*f126890aSEmmanuel Vadot #define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
595*f126890aSEmmanuel Vadot 
596*f126890aSEmmanuel Vadot #define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
597*f126890aSEmmanuel Vadot #define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
598*f126890aSEmmanuel Vadot #define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
599*f126890aSEmmanuel Vadot 
600*f126890aSEmmanuel Vadot #define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
601*f126890aSEmmanuel Vadot #define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
602*f126890aSEmmanuel Vadot #define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
603*f126890aSEmmanuel Vadot 
604*f126890aSEmmanuel Vadot #define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
605*f126890aSEmmanuel Vadot #define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
606*f126890aSEmmanuel Vadot #define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
607*f126890aSEmmanuel Vadot 
608*f126890aSEmmanuel Vadot #define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
609*f126890aSEmmanuel Vadot #define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
610*f126890aSEmmanuel Vadot 
611*f126890aSEmmanuel Vadot #define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
612*f126890aSEmmanuel Vadot #define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
613*f126890aSEmmanuel Vadot 
614*f126890aSEmmanuel Vadot #define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
615*f126890aSEmmanuel Vadot #define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
616*f126890aSEmmanuel Vadot #define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
617*f126890aSEmmanuel Vadot #define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
618*f126890aSEmmanuel Vadot #define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
619*f126890aSEmmanuel Vadot #define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
620*f126890aSEmmanuel Vadot 
621*f126890aSEmmanuel Vadot #define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
622*f126890aSEmmanuel Vadot #define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
623*f126890aSEmmanuel Vadot #define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
624*f126890aSEmmanuel Vadot #define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
625*f126890aSEmmanuel Vadot #define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
626*f126890aSEmmanuel Vadot #define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
627*f126890aSEmmanuel Vadot 
628*f126890aSEmmanuel Vadot #define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
629*f126890aSEmmanuel Vadot #define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
630*f126890aSEmmanuel Vadot 
631*f126890aSEmmanuel Vadot #define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
632*f126890aSEmmanuel Vadot #define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
633*f126890aSEmmanuel Vadot 
634*f126890aSEmmanuel Vadot #define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
635*f126890aSEmmanuel Vadot 
636*f126890aSEmmanuel Vadot #define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
637*f126890aSEmmanuel Vadot #define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
638*f126890aSEmmanuel Vadot 
639*f126890aSEmmanuel Vadot #define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
640*f126890aSEmmanuel Vadot #define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
641*f126890aSEmmanuel Vadot 
642*f126890aSEmmanuel Vadot #define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
643*f126890aSEmmanuel Vadot 
644*f126890aSEmmanuel Vadot #define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
645*f126890aSEmmanuel Vadot #define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
646*f126890aSEmmanuel Vadot 
647*f126890aSEmmanuel Vadot #define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
648*f126890aSEmmanuel Vadot #define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
649*f126890aSEmmanuel Vadot 
650*f126890aSEmmanuel Vadot #define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
651*f126890aSEmmanuel Vadot #define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
652*f126890aSEmmanuel Vadot 
653*f126890aSEmmanuel Vadot #define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
654*f126890aSEmmanuel Vadot #define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
655*f126890aSEmmanuel Vadot 
656*f126890aSEmmanuel Vadot #define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
657*f126890aSEmmanuel Vadot #define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
658*f126890aSEmmanuel Vadot 
659*f126890aSEmmanuel Vadot #define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
660*f126890aSEmmanuel Vadot #define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
661*f126890aSEmmanuel Vadot 
662*f126890aSEmmanuel Vadot #define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
663*f126890aSEmmanuel Vadot 
664*f126890aSEmmanuel Vadot #define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
665*f126890aSEmmanuel Vadot 
666*f126890aSEmmanuel Vadot #define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
667*f126890aSEmmanuel Vadot 
668*f126890aSEmmanuel Vadot #define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
669*f126890aSEmmanuel Vadot 
670*f126890aSEmmanuel Vadot #define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
671*f126890aSEmmanuel Vadot 
672*f126890aSEmmanuel Vadot #define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
673*f126890aSEmmanuel Vadot #define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
674*f126890aSEmmanuel Vadot #define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
675*f126890aSEmmanuel Vadot 
676*f126890aSEmmanuel Vadot #define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
677*f126890aSEmmanuel Vadot #define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
678*f126890aSEmmanuel Vadot 
679*f126890aSEmmanuel Vadot #define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
680*f126890aSEmmanuel Vadot #define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
681*f126890aSEmmanuel Vadot #define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
682*f126890aSEmmanuel Vadot 
683*f126890aSEmmanuel Vadot #define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
684*f126890aSEmmanuel Vadot #define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
685*f126890aSEmmanuel Vadot #define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
686*f126890aSEmmanuel Vadot 
687*f126890aSEmmanuel Vadot #define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
688*f126890aSEmmanuel Vadot #define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
689*f126890aSEmmanuel Vadot #define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
690*f126890aSEmmanuel Vadot 
691*f126890aSEmmanuel Vadot #define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
692*f126890aSEmmanuel Vadot #define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
693*f126890aSEmmanuel Vadot #define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
694*f126890aSEmmanuel Vadot 
695*f126890aSEmmanuel Vadot #define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
696*f126890aSEmmanuel Vadot #define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
697*f126890aSEmmanuel Vadot 
698*f126890aSEmmanuel Vadot #define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
699*f126890aSEmmanuel Vadot #define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
700*f126890aSEmmanuel Vadot 
701*f126890aSEmmanuel Vadot #define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
702*f126890aSEmmanuel Vadot #define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
703*f126890aSEmmanuel Vadot 
704*f126890aSEmmanuel Vadot #define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
705*f126890aSEmmanuel Vadot #define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
706*f126890aSEmmanuel Vadot 
707*f126890aSEmmanuel Vadot #define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
708*f126890aSEmmanuel Vadot #define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
709*f126890aSEmmanuel Vadot 
710*f126890aSEmmanuel Vadot #define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
711*f126890aSEmmanuel Vadot #define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
712*f126890aSEmmanuel Vadot 
713*f126890aSEmmanuel Vadot #define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
714*f126890aSEmmanuel Vadot #define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
715*f126890aSEmmanuel Vadot 
716*f126890aSEmmanuel Vadot #define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
717*f126890aSEmmanuel Vadot #define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
718*f126890aSEmmanuel Vadot #define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
719*f126890aSEmmanuel Vadot 
720*f126890aSEmmanuel Vadot #define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
721*f126890aSEmmanuel Vadot #define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
722*f126890aSEmmanuel Vadot #define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
723*f126890aSEmmanuel Vadot 
724*f126890aSEmmanuel Vadot #define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
725*f126890aSEmmanuel Vadot #define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
726*f126890aSEmmanuel Vadot 
727*f126890aSEmmanuel Vadot #endif /* __DTS_MT2701_PINFUNC_H */
728