xref: /freebsd/sys/contrib/device-tree/src/arm/marvell/armada-381-netgear-gs110emx.dts (revision a8089ea5aee578e08acab2438e82fc9a9ae50ed8) 
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
3
4/dts-v1/;
5#include "armada-385.dtsi"
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8
9/ {
10	model = "Netgear GS110EMX";
11	compatible = "netgear,gs110emx", "marvell,armada380";
12
13	aliases {
14		/* So that mvebu u-boot can update the MAC addresses */
15		ethernet1 = &eth0;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	gpio-keys {
23		compatible = "gpio-keys";
24		pinctrl-0 = <&front_button_pins>;
25		pinctrl-names = "default";
26
27		key-factory-default {
28			label = "Factory Default";
29			gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
30			linux,code = <KEY_RESTART>;
31		};
32	};
33
34	memory {
35		device_type = "memory";
36		reg = <0x00000000 0x08000000>; /* 128 MB */
37	};
38
39	soc {
40		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
42			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
43			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
44			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
45
46		internal-regs {
47			rtc@a3800 {
48				/*
49				 * If the rtc doesn't work, run "date reset"
50				 * twice in u-boot.
51				 */
52				status = "okay";
53			};
54		};
55	};
56};
57
58&eth0 {
59	/* ethernet@70000 */
60	bm,pool-long = <0>;
61	bm,pool-short = <1>;
62	buffer-manager = <&bm>;
63	phy-mode = "rgmii-id";
64	pinctrl-0 = <&ge0_rgmii_pins>;
65	pinctrl-names = "default";
66	status = "okay";
67
68	fixed-link {
69		full-duplex;
70		pause;
71		speed = <1000>;
72	};
73};
74
75&mdio {
76	pinctrl-names = "default";
77	pinctrl-0 = <&mdio_pins>;
78	status = "okay";
79
80	switch@0 {
81		compatible = "marvell,mv88e6190";
82		#address-cells = <1>;
83		#interrupt-cells = <2>;
84		interrupt-controller;
85		interrupt-parent = <&gpio1>;
86		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
87		pinctrl-0 = <&switch_interrupt_pins>;
88		pinctrl-names = "default";
89		#size-cells = <0>;
90		reg = <0>;
91
92		mdio {
93			#address-cells = <1>;
94			#size-cells = <0>;
95
96			switch0phy1: switch0phy1@1 {
97				reg = <0x1>;
98			};
99
100			switch0phy2: switch0phy2@2 {
101				reg = <0x2>;
102			};
103
104			switch0phy3: switch0phy3@3 {
105				reg = <0x3>;
106			};
107
108			switch0phy4: switch0phy4@4 {
109				reg = <0x4>;
110			};
111
112			switch0phy5: switch0phy5@5 {
113				reg = <0x5>;
114			};
115
116			switch0phy6: switch0phy6@6 {
117				reg = <0x6>;
118			};
119
120			switch0phy7: switch0phy7@7 {
121				reg = <0x7>;
122			};
123
124			switch0phy8: switch0phy8@8 {
125				reg = <0x8>;
126			};
127		};
128
129		mdio-external {
130			compatible = "marvell,mv88e6xxx-mdio-external";
131			#address-cells = <1>;
132			#size-cells = <0>;
133
134			phy1: ethernet-phy@b {
135				reg = <0xb>;
136				compatible = "ethernet-phy-ieee802.3-c45";
137			};
138
139			phy2: ethernet-phy@c {
140				reg = <0xc>;
141				compatible = "ethernet-phy-ieee802.3-c45";
142			};
143		};
144
145		ports {
146			#address-cells = <1>;
147			#size-cells = <0>;
148
149			port@0 {
150				ethernet = <&eth0>;
151				phy-mode = "rgmii";
152				reg = <0>;
153
154				fixed-link {
155					full-duplex;
156					pause;
157					speed = <1000>;
158				};
159			};
160
161			port@1 {
162				label = "lan1";
163				phy-handle = <&switch0phy1>;
164				reg = <1>;
165			};
166
167			port@2 {
168				label = "lan2";
169				phy-handle = <&switch0phy2>;
170				reg = <2>;
171			};
172
173			port@3 {
174				label = "lan3";
175				phy-handle = <&switch0phy3>;
176				reg = <3>;
177			};
178
179			port@4 {
180				label = "lan4";
181				phy-handle = <&switch0phy4>;
182				reg = <4>;
183			};
184
185			port@5 {
186				label = "lan5";
187				phy-handle = <&switch0phy5>;
188				reg = <5>;
189			};
190
191			port@6 {
192				label = "lan6";
193				phy-handle = <&switch0phy6>;
194				reg = <6>;
195			};
196
197			port@7 {
198				label = "lan7";
199				phy-handle = <&switch0phy7>;
200				reg = <7>;
201			};
202
203			port@8 {
204				label = "lan8";
205				phy-handle = <&switch0phy8>;
206				reg = <8>;
207			};
208
209			port@9 {
210				/* 88X3310P external phy */
211				label = "lan9";
212				phy-handle = <&phy1>;
213				phy-mode = "xaui";
214				reg = <9>;
215			};
216
217			port@a {
218				/* 88X3310P external phy */
219				label = "lan10";
220				phy-handle = <&phy2>;
221				phy-mode = "xaui";
222				reg = <0xa>;
223			};
224		};
225	};
226};
227
228&pinctrl {
229	front_button_pins: front-button-pins {
230		marvell,pins = "mpp38";
231		marvell,function = "gpio";
232	};
233
234	switch_interrupt_pins: switch-interrupt-pins {
235		marvell,pins = "mpp39";
236		marvell,function = "gpio";
237	};
238};
239
240&spi0 {
241	pinctrl-0 = <&spi0_pins>;
242	pinctrl-names = "default";
243	status = "okay";
244
245	flash@0 {
246		#address-cells = <1>;
247		#size-cells = <1>;
248		compatible = "jedec,spi-nor";
249		reg = <0>; /* Chip select 0 */
250		spi-max-frequency = <3000000>;
251
252		partitions {
253			compatible = "fixed-partitions";
254			#address-cells = <1>;
255			#size-cells = <1>;
256
257			partition@0 {
258				label = "boot";
259				read-only;
260				reg = <0x00000000 0x00100000>;
261			};
262
263			partition@100000 {
264				label = "env";
265				reg = <0x00100000 0x00010000>;
266			};
267
268			partition@200000 {
269				label = "rsv";
270				reg = <0x00110000 0x00010000>;
271			};
272
273			partition@300000 {
274				label = "image0";
275				reg = <0x00120000 0x00900000>;
276			};
277
278			partition@400000 {
279				label = "config";
280				reg = <0x00a20000 0x00300000>;
281			};
282
283			partition@480000 {
284				label = "debug";
285				reg = <0x00d20000 0x002e0000>;
286			};
287		};
288	};
289};
290
291&uart0 {
292	pinctrl-0 = <&uart0_pins>;
293	pinctrl-names = "default";
294	status = "okay";
295};
296