1// SPDX-License-Identifier: ISC 2/* 3 * Device Tree include file for Intel reference designs for the 4 * XScale Network Processors in the IXP 4xx series. Common device 5 * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465. 6 */ 7 8/ { 9 memory@0 { 10 /* 11 * The board supports up to 256 MB of memory. Here we put in 12 * 64 MB and this may be modified by the boot loader. 13 */ 14 device_type = "memory"; 15 reg = <0x00000000 0x4000000>; 16 }; 17 18 chosen { 19 bootargs = "console=ttyS0,115200n8"; 20 stdout-path = "uart0:115200n8"; 21 }; 22 23 aliases { 24 serial0 = &uart0; 25 }; 26 27 i2c { 28 compatible = "i2c-gpio"; 29 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 30 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 eeprom@50 { 35 /* 36 * Philips PCF8582C-2T/03 512byte I2C EEPROM 37 * should behave like an Atmel 24c04. 38 */ 39 compatible = "atmel,24c04"; 40 reg = <0x50>; 41 pagesize = <16>; 42 size = <512>; 43 read-only; 44 }; 45 }; 46 47 soc { 48 bus@c4000000 { 49 /* Flash memory defined per-variant */ 50 nand-controller@3,0 { 51 /* Some designs have a NAND on CS3 enable it here if present */ 52 status = "disabled"; 53 54 /* 55 * gen_nand needs to be extended and documented to get 56 * command byte = 1 and address byte = 2 from the device 57 * tree. 58 */ 59 compatible = "gen_nand"; 60 61 /* Expansion bus set-up */ 62 intel,ixp4xx-eb-t1 = <0>; 63 intel,ixp4xx-eb-t2 = <0>; 64 intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase 65 intel,ixp4xx-eb-t4 = <0>; 66 intel,ixp4xx-eb-t5 = <0>; 67 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type 68 intel,ixp4xx-eb-byte-access-on-halfword = <0>; 69 intel,ixp4xx-eb-mux-address-and-data = <0>; 70 intel,ixp4xx-eb-ahb-split-transfers = <0>; 71 intel,ixp4xx-eb-write-enable = <1>; 72 intel,ixp4xx-eb-byte-access = <1>; 73 74 /* 512 bytes memory window */ 75 reg = <3 0x00000000 0x200>; 76 nand-on-flash-bbt; 77 nand-ecc-mode = "soft_bch"; 78 nand-ecc-step-size = <512>; 79 nand-ecc-strength = <4>; 80 nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */ 81 82 label = "ixp400 NAND"; 83 84 partitions { 85 compatible = "fixed-partitions"; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 89 fs@0 { 90 label = "ixp400 NAND FS 0"; 91 reg = <0x0 0x800000>; 92 }; 93 fs@800000 { 94 label = "ixp400 NAND FS 1"; 95 reg = <0x800000 0x0>; 96 }; 97 }; 98 }; 99 }; 100 101 pci@c0000000 { 102 status = "okay"; 103 104 /* 105 * Taken from IXDP425 PCI boardfile. 106 * PCI slots on the BIXMB425BD base card. 107 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. 108 */ 109 #interrupt-cells = <1>; 110 interrupt-map-mask = <0xf800 0 0 7>; 111 interrupt-map = 112 /* IDSEL 1 */ 113 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ 114 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ 115 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ 116 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ 117 /* IDSEL 2 */ 118 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ 119 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ 120 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ 121 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ 122 /* IDSEL 3 */ 123 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ 124 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ 125 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ 126 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ 127 /* IDSEL 4 */ 128 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ 129 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ 130 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ 131 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ 132 }; 133 }; 134}; 135