1// SPDX-License-Identifier: ISC 2/* 3 * Device Tree file for the Intel IXDPG425 reference design. 4 * Derived from boardfiles written by MontaVista software. 5 * Ethernet set-up from OpenWrt. 6 * 7 * The device has 4 x FXS RJ11 ports for analog phones for 8 * internet telephony. (Not supported yet.) 9 * 10 * The device has 9 status LEDs we do not support yet. 11 * 12 * This device is very similar to ADI engingeering Coyote. 13 */ 14 15/dts-v1/; 16 17#include "intel-ixp42x.dtsi" 18#include <dt-bindings/input/input.h> 19 20/ { 21 model = "Intel IXDPG425 reference design"; 22 compatible = "intel,ixdpg425", "intel,ixp42x"; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 memory@0 { 27 /* 32 MB SDRAM */ 28 device_type = "memory"; 29 reg = <0x00000000 0x02000000>; 30 }; 31 32 chosen { 33 bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; 34 stdout-path = "uart0:115200n8"; 35 }; 36 37 aliases { 38 serial0 = &uart0; 39 }; 40 41 soc { 42 bus@c4000000 { 43 flash@0,0 { 44 compatible = "intel,ixp4xx-flash", "cfi-flash"; 45 bank-width = <2>; 46 /* 47 * CHECKME: the product brief says 16MB in a flash 48 * socket. 49 */ 50 reg = <0 0x00000000 0x1000000>; 51 52 /* Configure expansion bus to allow writes */ 53 intel,ixp4xx-eb-write-enable = <1>; 54 55 partitions { 56 compatible = "redboot-fis"; 57 /* CHECKME: guess this is Redboot FIS */ 58 fis-index-block = <0x7f>; 59 }; 60 }; 61 }; 62 63 pci@c0000000 { 64 status = "okay"; 65 66 /* 67 * Taken from IXDPG425 PCI boardfile. 68 * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ 69 * for 12 & 13 and one for 14. 70 */ 71 #interrupt-cells = <1>; 72 interrupt-map-mask = <0xf800 0 0 7>; 73 interrupt-map = 74 /* IDSEL 12 */ 75 <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */ 76 <0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */ 77 <0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */ 78 <0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */ 79 /* IDSEL 13 */ 80 <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ 81 <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ 82 <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ 83 <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ 84 /* IDSEL 14 */ 85 <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ 86 <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ 87 <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ 88 <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ 89 }; 90 91 /* 92 * CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind 93 * of Realtek DSA switch on the board. 94 */ 95 96 /* EthB */ 97 ethernet@c8009000 { 98 status = "okay"; 99 queue-rx = <&qmgr 3>; 100 queue-txready = <&qmgr 20>; 101 phy-mode = "rgmii"; 102 phy-handle = <&phy5>; 103 104 mdio { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 phy4: ethernet-phy@4 { 109 reg = <4>; 110 }; 111 112 phy5: ethernet-phy@5 { 113 reg = <5>; 114 }; 115 }; 116 }; 117 118 /* EthC */ 119 ethernet@c800a000 { 120 status = "okay"; 121 queue-rx = <&qmgr 4>; 122 queue-txready = <&qmgr 21>; 123 phy-mode = "rgmii"; 124 phy-handle = <&phy4>; 125 }; 126 }; 127}; 128