1// SPDX-License-Identifier: GPL-2.0-only 2// Copyright (C) 2014 Broadcom Corporation 3 4#include <dt-bindings/clock/bcm21664.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 model = "BCM21664 SoC"; 12 compatible = "brcm,bcm21664"; 13 interrupt-parent = <&gic>; 14 15 chosen { 16 bootargs = "console=ttyS0,115200n8"; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a9"; 26 reg = <0>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 enable-method = "brcm,bcm11351-cpu-method"; 33 secondary-boot-reg = <0x35004178>; 34 reg = <1>; 35 }; 36 }; 37 38 gic: interrupt-controller@3ff00100 { 39 compatible = "arm,cortex-a9-gic"; 40 #interrupt-cells = <3>; 41 #address-cells = <0>; 42 interrupt-controller; 43 reg = <0x3ff01000 0x1000>, 44 <0x3ff00100 0x100>; 45 }; 46 47 smc@3404e000 { 48 compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; 49 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ 50 }; 51 52 uartb: serial@3e000000 { 53 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 54 reg = <0x3e000000 0x118>; 55 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; 56 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 57 reg-shift = <2>; 58 reg-io-width = <4>; 59 status = "disabled"; 60 }; 61 62 uartb2: serial@3e001000 { 63 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 64 reg = <0x3e001000 0x118>; 65 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; 66 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 67 reg-shift = <2>; 68 reg-io-width = <4>; 69 status = "disabled"; 70 }; 71 72 uartb3: serial@3e002000 { 73 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 74 reg = <0x3e002000 0x118>; 75 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; 76 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 77 reg-shift = <2>; 78 reg-io-width = <4>; 79 status = "disabled"; 80 }; 81 82 L2: cache-controller@3ff20000 { 83 compatible = "arm,pl310-cache"; 84 reg = <0x3ff20000 0x1000>; 85 cache-unified; 86 cache-level = <2>; 87 }; 88 89 brcm,resetmgr@35001f00 { 90 compatible = "brcm,bcm21664-resetmgr"; 91 reg = <0x35001f00 0x24>; 92 }; 93 94 timer@35006000 { 95 compatible = "brcm,kona-timer"; 96 reg = <0x35006000 0x1c>; 97 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; 99 }; 100 101 gpio: gpio@35003000 { 102 compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; 103 reg = <0x35003000 0x524>; 104 interrupts = 105 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 106 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 107 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 108 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 109 #gpio-cells = <2>; 110 #interrupt-cells = <2>; 111 gpio-controller; 112 interrupt-controller; 113 }; 114 115 sdio1: mmc@3f180000 { 116 compatible = "brcm,kona-sdhci"; 117 reg = <0x3f180000 0x801c>; 118 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; 120 status = "disabled"; 121 }; 122 123 sdio2: mmc@3f190000 { 124 compatible = "brcm,kona-sdhci"; 125 reg = <0x3f190000 0x801c>; 126 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; 128 status = "disabled"; 129 }; 130 131 sdio3: mmc@3f1a0000 { 132 compatible = "brcm,kona-sdhci"; 133 reg = <0x3f1a0000 0x801c>; 134 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; 136 status = "disabled"; 137 }; 138 139 sdio4: mmc@3f1b0000 { 140 compatible = "brcm,kona-sdhci"; 141 reg = <0x3f1b0000 0x801c>; 142 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; 144 status = "disabled"; 145 }; 146 147 bsc1: i2c@3e016000 { 148 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 149 reg = <0x3e016000 0x70>; 150 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; 154 status = "disabled"; 155 }; 156 157 bsc2: i2c@3e017000 { 158 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 159 reg = <0x3e017000 0x70>; 160 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; 164 status = "disabled"; 165 }; 166 167 bsc3: i2c@3e018000 { 168 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 169 reg = <0x3e018000 0x70>; 170 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; 174 status = "disabled"; 175 }; 176 177 bsc4: i2c@3e01c000 { 178 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 179 reg = <0x3e01c000 0x70>; 180 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; 184 status = "disabled"; 185 }; 186 187 clocks { 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges; 191 192 /* 193 * Fixed clocks are defined before CCUs whose 194 * clocks may depend on them. 195 */ 196 197 ref_32k_clk: ref_32k { 198 #clock-cells = <0>; 199 compatible = "fixed-clock"; 200 clock-frequency = <32768>; 201 }; 202 203 bbl_32k_clk: bbl_32k { 204 #clock-cells = <0>; 205 compatible = "fixed-clock"; 206 clock-frequency = <32768>; 207 }; 208 209 ref_13m_clk: ref_13m { 210 #clock-cells = <0>; 211 compatible = "fixed-clock"; 212 clock-frequency = <13000000>; 213 }; 214 215 var_13m_clk: var_13m { 216 #clock-cells = <0>; 217 compatible = "fixed-clock"; 218 clock-frequency = <13000000>; 219 }; 220 221 dft_19_5m_clk: dft_19_5m { 222 #clock-cells = <0>; 223 compatible = "fixed-clock"; 224 clock-frequency = <19500000>; 225 }; 226 227 ref_crystal_clk: ref_crystal { 228 #clock-cells = <0>; 229 compatible = "fixed-clock"; 230 clock-frequency = <26000000>; 231 }; 232 233 ref_52m_clk: ref_52m { 234 #clock-cells = <0>; 235 compatible = "fixed-clock"; 236 clock-frequency = <52000000>; 237 }; 238 239 var_52m_clk: var_52m { 240 #clock-cells = <0>; 241 compatible = "fixed-clock"; 242 clock-frequency = <52000000>; 243 }; 244 245 usb_otg_ahb_clk: usb_otg_ahb { 246 #clock-cells = <0>; 247 compatible = "fixed-clock"; 248 clock-frequency = <52000000>; 249 }; 250 251 ref_96m_clk: ref_96m { 252 #clock-cells = <0>; 253 compatible = "fixed-clock"; 254 clock-frequency = <96000000>; 255 }; 256 257 var_96m_clk: var_96m { 258 #clock-cells = <0>; 259 compatible = "fixed-clock"; 260 clock-frequency = <96000000>; 261 }; 262 263 ref_104m_clk: ref_104m { 264 #clock-cells = <0>; 265 compatible = "fixed-clock"; 266 clock-frequency = <104000000>; 267 }; 268 269 var_104m_clk: var_104m { 270 #clock-cells = <0>; 271 compatible = "fixed-clock"; 272 clock-frequency = <104000000>; 273 }; 274 275 ref_156m_clk: ref_156m { 276 #clock-cells = <0>; 277 compatible = "fixed-clock"; 278 clock-frequency = <156000000>; 279 }; 280 281 var_156m_clk: var_156m { 282 #clock-cells = <0>; 283 compatible = "fixed-clock"; 284 clock-frequency = <156000000>; 285 }; 286 287 root_ccu: root_ccu@35001000 { 288 compatible = "brcm,bcm21664-root-ccu"; 289 reg = <0x35001000 0x0f00>; 290 #clock-cells = <1>; 291 clock-output-names = "frac_1m"; 292 }; 293 294 aon_ccu: aon_ccu@35002000 { 295 compatible = "brcm,bcm21664-aon-ccu"; 296 reg = <0x35002000 0x0f00>; 297 #clock-cells = <1>; 298 clock-output-names = "hub_timer"; 299 }; 300 301 master_ccu: master_ccu@3f001000 { 302 compatible = "brcm,bcm21664-master-ccu"; 303 reg = <0x3f001000 0x0f00>; 304 #clock-cells = <1>; 305 clock-output-names = "sdio1", 306 "sdio2", 307 "sdio3", 308 "sdio4", 309 "sdio1_sleep", 310 "sdio2_sleep", 311 "sdio3_sleep", 312 "sdio4_sleep"; 313 }; 314 315 slave_ccu: slave_ccu@3e011000 { 316 compatible = "brcm,bcm21664-slave-ccu"; 317 reg = <0x3e011000 0x0f00>; 318 #clock-cells = <1>; 319 clock-output-names = "uartb", 320 "uartb2", 321 "uartb3", 322 "bsc1", 323 "bsc2", 324 "bsc3", 325 "bsc4"; 326 }; 327 }; 328 329 usbotg: usb@3f120000 { 330 compatible = "snps,dwc2"; 331 reg = <0x3f120000 0x10000>; 332 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&usb_otg_ahb_clk>; 334 clock-names = "otg"; 335 phys = <&usbphy>; 336 phy-names = "usb2-phy"; 337 status = "disabled"; 338 }; 339 340 usbphy: usb-phy@3f130000 { 341 compatible = "brcm,kona-usb2-phy"; 342 reg = <0x3f130000 0x28>; 343 #phy-cells = <0>; 344 status = "disabled"; 345 }; 346}; 347