1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34#include <dt-bindings/interrupt-controller/irq.h> 35 36/ { 37 compatible = "brcm,hr2"; 38 model = "Broadcom Hurricane 2 SoC"; 39 interrupt-parent = <&gic>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a9"; 50 next-level-cache = <&L2>; 51 reg = <0x0>; 52 }; 53 }; 54 55 pmu { 56 compatible = "arm,cortex-a9-pmu"; 57 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 59 interrupt-affinity = <&cpu0>; 60 }; 61 62 mpcore@19000000 { 63 compatible = "simple-bus"; 64 ranges = <0x00000000 0x19000000 0x00023000>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 68 a9pll: arm_clk@0 { 69 #clock-cells = <0>; 70 compatible = "brcm,hr2-armpll"; 71 clocks = <&osc>; 72 reg = <0x0 0x1000>; 73 }; 74 75 timer@20200 { 76 compatible = "arm,cortex-a9-global-timer"; 77 reg = <0x20200 0x100>; 78 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 79 clocks = <&periph_clk>; 80 }; 81 82 twd-timer@20600 { 83 compatible = "arm,cortex-a9-twd-timer"; 84 reg = <0x20600 0x20>; 85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 86 IRQ_TYPE_EDGE_RISING)>; 87 clocks = <&periph_clk>; 88 }; 89 90 twd-watchdog@20620 { 91 compatible = "arm,cortex-a9-twd-wdt"; 92 reg = <0x20620 0x20>; 93 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 94 IRQ_TYPE_EDGE_RISING)>; 95 clocks = <&periph_clk>; 96 }; 97 98 gic: interrupt-controller@21000 { 99 compatible = "arm,cortex-a9-gic"; 100 #interrupt-cells = <3>; 101 #address-cells = <0>; 102 interrupt-controller; 103 reg = <0x21000 0x1000>, 104 <0x20100 0x100>; 105 }; 106 107 L2: cache-controller@22000 { 108 compatible = "arm,pl310-cache"; 109 reg = <0x22000 0x1000>; 110 cache-unified; 111 cache-level = <2>; 112 }; 113 }; 114 115 clocks { 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges; 119 120 osc: oscillator { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 clock-frequency = <25000000>; 124 }; 125 126 periph_clk: periph_clk { 127 #clock-cells = <0>; 128 compatible = "fixed-factor-clock"; 129 clocks = <&a9pll>; 130 clock-div = <2>; 131 clock-mult = <1>; 132 }; 133 }; 134 135 axi@18000000 { 136 compatible = "simple-bus"; 137 ranges = <0x00000000 0x18000000 0x0011c40c>; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 141 uart0: serial@300 { 142 compatible = "ns16550a"; 143 reg = <0x0300 0x100>; 144 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&osc>; 146 status = "disabled"; 147 }; 148 149 uart1: serial@400 { 150 compatible = "ns16550a"; 151 reg = <0x0400 0x100>; 152 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&osc>; 154 status = "disabled"; 155 }; 156 157 dma@20000 { 158 compatible = "arm,pl330", "arm,primecell"; 159 reg = <0x20000 0x1000>; 160 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 169 #dma-cells = <1>; 170 status = "disabled"; 171 }; 172 173 amac0: ethernet@22000 { 174 compatible = "brcm,nsp-amac"; 175 reg = <0x22000 0x1000>, 176 <0x110000 0x1000>; 177 reg-names = "amac_base", "idm_base"; 178 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 179 status = "disabled"; 180 }; 181 182 nand_controller: nand-controller@26000 { 183 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 184 reg = <0x26000 0x600>, 185 <0x11b408 0x600>, 186 <0x026f00 0x20>; 187 reg-names = "nand", "iproc-idm", "iproc-ext"; 188 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 189 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 brcm,nand-has-wp; 194 }; 195 196 gpiob: gpio@30000 { 197 compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; 198 reg = <0x30000 0x50>; 199 #gpio-cells = <2>; 200 gpio-controller; 201 ngpios = <4>; 202 interrupt-controller; 203 #interrupt-cells = <2>; 204 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 205 }; 206 207 pwm: pwm@31000 { 208 compatible = "brcm,iproc-pwm"; 209 reg = <0x31000 0x28>; 210 clocks = <&osc>; 211 #pwm-cells = <3>; 212 status = "disabled"; 213 }; 214 215 rng: rng@33000 { 216 compatible = "brcm,bcm-nsp-rng"; 217 reg = <0x33000 0x14>; 218 }; 219 220 qspi: spi@27200 { 221 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 222 reg = <0x027200 0x184>, 223 <0x027000 0x124>, 224 <0x11c408 0x004>, 225 <0x0273a0 0x01c>; 226 reg-names = "mspi", "bspi", "intr_regs", 227 "intr_status_reg"; 228 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "spi_lr_fullness_reached", 236 "spi_lr_session_aborted", 237 "spi_lr_impatient", 238 "spi_lr_session_done", 239 "spi_lr_overhead", 240 "mspi_done", 241 "mspi_halted"; 242 num-cs = <2>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* partitions defined in board DTS */ 247 }; 248 249 ccbtimer0: timer@34000 { 250 compatible = "arm,sp804"; 251 reg = <0x34000 0x1000>; 252 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 254 }; 255 256 ccbtimer1: timer@35000 { 257 compatible = "arm,sp804"; 258 reg = <0x35000 0x1000>; 259 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 261 }; 262 263 i2c0: i2c@38000 { 264 compatible = "brcm,iproc-i2c"; 265 reg = <0x38000 0x50>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 269 clock-frequency = <100000>; 270 }; 271 272 watchdog: watchdog@39000 { 273 compatible = "arm,sp805", "arm,primecell"; 274 reg = <0x39000 0x1000>; 275 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 i2c1: i2c@3b000 { 279 compatible = "brcm,iproc-i2c"; 280 reg = <0x3b000 0x50>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 284 clock-frequency = <100000>; 285 }; 286 }; 287 288 pflash: nor@20000000 { 289 compatible = "cfi-flash", "jedec-flash"; 290 reg = <0x20000000 0x04000000>; 291 status = "disabled"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 295 /* partitions defined in board DTS */ 296 }; 297 298 pcie0: pcie@18012000 { 299 compatible = "brcm,iproc-pcie"; 300 reg = <0x18012000 0x1000>; 301 302 #interrupt-cells = <1>; 303 interrupt-map-mask = <0 0 0 0>; 304 interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 305 306 linux,pci-domain = <0>; 307 308 bus-range = <0x00 0xff>; 309 310 #address-cells = <3>; 311 #size-cells = <2>; 312 device_type = "pci"; 313 314 /* Note: The HW does not support I/O resources. So, 315 * only the memory resource range is being specified. 316 */ 317 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; 318 319 status = "disabled"; 320 321 msi-parent = <&msi0>; 322 msi0: msi { 323 compatible = "brcm,iproc-msi"; 324 msi-controller; 325 interrupt-parent = <&gic>; 326 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 330 brcm,pcie-msi-inten; 331 }; 332 }; 333 334 pcie1: pcie@18013000 { 335 compatible = "brcm,iproc-pcie"; 336 reg = <0x18013000 0x1000>; 337 338 #interrupt-cells = <1>; 339 interrupt-map-mask = <0 0 0 0>; 340 interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 341 342 linux,pci-domain = <1>; 343 344 bus-range = <0x00 0xff>; 345 346 #address-cells = <3>; 347 #size-cells = <2>; 348 device_type = "pci"; 349 350 /* Note: The HW does not support I/O resources. So, 351 * only the memory resource range is being specified. 352 */ 353 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; 354 355 status = "disabled"; 356 357 msi-parent = <&msi1>; 358 msi1: msi { 359 compatible = "brcm,iproc-msi"; 360 msi-controller; 361 interrupt-parent = <&gic>; 362 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 366 brcm,pcie-msi-inten; 367 }; 368 }; 369}; 370