1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3 4/ { 5 model = "Aspeed BMC"; 6 compatible = "aspeed,ast2400"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart5; 31 serial5 = &vuart; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 device_type = "cpu"; 41 reg = <0>; 42 }; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0x40000000 0>; 48 }; 49 50 ahb { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 56 fmc: spi@1e620000 { 57 reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 compatible = "aspeed,ast2400-fmc"; 61 clocks = <&syscon ASPEED_CLK_AHB>; 62 status = "disabled"; 63 interrupts = <19>; 64 flash@0 { 65 reg = < 0 >; 66 compatible = "jedec,spi-nor"; 67 spi-rx-bus-width = <2>; 68 spi-max-frequency = <50000000>; 69 status = "disabled"; 70 }; 71 flash@1 { 72 reg = < 1 >; 73 compatible = "jedec,spi-nor"; 74 spi-rx-bus-width = <2>; 75 spi-max-frequency = <50000000>; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 spi-rx-bus-width = <2>; 82 spi-max-frequency = <50000000>; 83 status = "disabled"; 84 }; 85 flash@3 { 86 reg = < 3 >; 87 compatible = "jedec,spi-nor"; 88 spi-rx-bus-width = <2>; 89 spi-max-frequency = <50000000>; 90 status = "disabled"; 91 }; 92 flash@4 { 93 reg = < 4 >; 94 compatible = "jedec,spi-nor"; 95 spi-rx-bus-width = <2>; 96 spi-max-frequency = <50000000>; 97 status = "disabled"; 98 }; 99 }; 100 101 spi: spi@1e630000 { 102 reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 compatible = "aspeed,ast2400-spi"; 106 clocks = <&syscon ASPEED_CLK_AHB>; 107 status = "disabled"; 108 flash@0 { 109 reg = < 0 >; 110 compatible = "jedec,spi-nor"; 111 spi-max-frequency = <50000000>; 112 spi-rx-bus-width = <2>; 113 status = "disabled"; 114 }; 115 }; 116 117 vic: interrupt-controller@1e6c0080 { 118 compatible = "aspeed,ast2400-vic"; 119 interrupt-controller; 120 #interrupt-cells = <1>; 121 valid-sources = <0xffffffff 0x0007ffff>; 122 reg = <0x1e6c0080 0x80>; 123 }; 124 125 cvic: copro-interrupt-controller@1e6c2000 { 126 compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; 127 valid-sources = <0x7fffffff>; 128 reg = <0x1e6c2000 0x80>; 129 }; 130 131 mac0: ethernet@1e660000 { 132 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 133 reg = <0x1e660000 0x180>; 134 interrupts = <2>; 135 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 136 status = "disabled"; 137 }; 138 139 mac1: ethernet@1e680000 { 140 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 141 reg = <0x1e680000 0x180>; 142 interrupts = <3>; 143 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 144 status = "disabled"; 145 }; 146 147 ehci0: usb@1e6a1000 { 148 compatible = "aspeed,ast2400-ehci", "generic-ehci"; 149 reg = <0x1e6a1000 0x100>; 150 interrupts = <5>; 151 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_usb2h_default>; 154 status = "disabled"; 155 }; 156 157 uhci: usb@1e6b0000 { 158 compatible = "aspeed,ast2400-uhci", "generic-uhci"; 159 reg = <0x1e6b0000 0x100>; 160 interrupts = <14>; 161 #ports = <3>; 162 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 163 status = "disabled"; 164 /* 165 * No default pinmux, it will follow EHCI, use an explicit pinmux 166 * override if you don't enable EHCI 167 */ 168 }; 169 170 vhub: usb-vhub@1e6a0000 { 171 compatible = "aspeed,ast2400-usb-vhub"; 172 reg = <0x1e6a0000 0x300>; 173 interrupts = <5>; 174 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 175 aspeed,vhub-downstream-ports = <5>; 176 aspeed,vhub-generic-endpoints = <15>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_usb2d_default>; 179 status = "disabled"; 180 }; 181 182 apb { 183 compatible = "simple-bus"; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 ranges; 187 188 syscon: syscon@1e6e2000 { 189 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; 190 reg = <0x1e6e2000 0x1a8>; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0 0x1e6e2000 0x1000>; 194 #clock-cells = <1>; 195 #reset-cells = <1>; 196 197 p2a: p2a-control@2c { 198 reg = <0x2c 0x4>; 199 compatible = "aspeed,ast2400-p2a-ctrl"; 200 status = "disabled"; 201 }; 202 203 silicon-id@7c { 204 compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; 205 reg = <0x7c 0x4>; 206 }; 207 208 pinctrl: pinctrl@80 { 209 reg = <0x80 0x18>, <0xa0 0x10>; 210 compatible = "aspeed,ast2400-pinctrl"; 211 }; 212 }; 213 214 rng: hwrng@1e6e2078 { 215 compatible = "timeriomem_rng"; 216 reg = <0x1e6e2078 0x4>; 217 period = <1>; 218 quality = <100>; 219 }; 220 221 adc: adc@1e6e9000 { 222 compatible = "aspeed,ast2400-adc"; 223 reg = <0x1e6e9000 0xb0>; 224 clocks = <&syscon ASPEED_CLK_APB>; 225 resets = <&syscon ASPEED_RESET_ADC>; 226 #io-channel-cells = <1>; 227 status = "disabled"; 228 }; 229 230 sram: sram@1e720000 { 231 compatible = "mmio-sram"; 232 reg = <0x1e720000 0x8000>; // 32K 233 }; 234 235 video: video@1e700000 { 236 compatible = "aspeed,ast2400-video-engine"; 237 reg = <0x1e700000 0x1000>; 238 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 239 <&syscon ASPEED_CLK_GATE_ECLK>; 240 clock-names = "vclk", "eclk"; 241 interrupts = <7>; 242 status = "disabled"; 243 }; 244 245 sdmmc: sd-controller@1e740000 { 246 compatible = "aspeed,ast2400-sd-controller"; 247 reg = <0x1e740000 0x100>; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges = <0 0x1e740000 0x10000>; 251 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 252 status = "disabled"; 253 254 sdhci0: sdhci@100 { 255 compatible = "aspeed,ast2400-sdhci"; 256 reg = <0x100 0x100>; 257 interrupts = <26>; 258 sdhci,auto-cmd12; 259 clocks = <&syscon ASPEED_CLK_SDIO>; 260 status = "disabled"; 261 }; 262 263 sdhci1: sdhci@200 { 264 compatible = "aspeed,ast2400-sdhci"; 265 reg = <0x200 0x100>; 266 interrupts = <26>; 267 sdhci,auto-cmd12; 268 clocks = <&syscon ASPEED_CLK_SDIO>; 269 status = "disabled"; 270 }; 271 }; 272 273 gpio: gpio@1e780000 { 274 #gpio-cells = <2>; 275 gpio-controller; 276 compatible = "aspeed,ast2400-gpio"; 277 reg = <0x1e780000 0x1000>; 278 interrupts = <20>; 279 gpio-ranges = <&pinctrl 0 0 220>; 280 clocks = <&syscon ASPEED_CLK_APB>; 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 }; 284 285 timer: timer@1e782000 { 286 /* This timer is a Faraday FTTMR010 derivative */ 287 compatible = "aspeed,ast2400-timer"; 288 reg = <0x1e782000 0x90>; 289 interrupts = <16 17 18 35 36 37 38 39>; 290 clocks = <&syscon ASPEED_CLK_APB>; 291 clock-names = "PCLK"; 292 }; 293 294 rtc: rtc@1e781000 { 295 compatible = "aspeed,ast2400-rtc"; 296 reg = <0x1e781000 0x18>; 297 status = "disabled"; 298 }; 299 300 uart1: serial@1e783000 { 301 compatible = "ns16550a"; 302 reg = <0x1e783000 0x20>; 303 reg-shift = <2>; 304 interrupts = <9>; 305 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 306 resets = <&lpc_reset 4>; 307 no-loopback-test; 308 status = "disabled"; 309 }; 310 311 uart5: serial@1e784000 { 312 compatible = "ns16550a"; 313 reg = <0x1e784000 0x20>; 314 reg-shift = <2>; 315 interrupts = <10>; 316 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 317 no-loopback-test; 318 status = "disabled"; 319 }; 320 321 wdt1: watchdog@1e785000 { 322 compatible = "aspeed,ast2400-wdt"; 323 reg = <0x1e785000 0x1c>; 324 clocks = <&syscon ASPEED_CLK_APB>; 325 }; 326 327 wdt2: watchdog@1e785020 { 328 compatible = "aspeed,ast2400-wdt"; 329 reg = <0x1e785020 0x1c>; 330 clocks = <&syscon ASPEED_CLK_APB>; 331 }; 332 333 pwm_tacho: pwm-tacho-controller@1e786000 { 334 compatible = "aspeed,ast2400-pwm-tacho"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <0x1e786000 0x1000>; 338 clocks = <&syscon ASPEED_CLK_24M>; 339 resets = <&syscon ASPEED_RESET_PWM>; 340 status = "disabled"; 341 }; 342 343 vuart: serial@1e787000 { 344 compatible = "aspeed,ast2400-vuart"; 345 reg = <0x1e787000 0x40>; 346 reg-shift = <2>; 347 interrupts = <8>; 348 clocks = <&syscon ASPEED_CLK_APB>; 349 no-loopback-test; 350 status = "disabled"; 351 }; 352 353 lpc: lpc@1e789000 { 354 compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"; 355 reg = <0x1e789000 0x1000>; 356 reg-io-width = <4>; 357 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges = <0x0 0x1e789000 0x1000>; 361 362 lpc_ctrl: lpc-ctrl@80 { 363 compatible = "aspeed,ast2400-lpc-ctrl"; 364 reg = <0x80 0x10>; 365 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 366 status = "disabled"; 367 }; 368 369 lpc_snoop: lpc-snoop@90 { 370 compatible = "aspeed,ast2400-lpc-snoop"; 371 reg = <0x90 0x8>; 372 interrupts = <8>; 373 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 374 status = "disabled"; 375 }; 376 377 lhc: lhc@a0 { 378 compatible = "aspeed,ast2400-lhc"; 379 reg = <0xa0 0x24 0xc8 0x8>; 380 }; 381 382 lpc_reset: reset-controller@98 { 383 compatible = "aspeed,ast2400-lpc-reset"; 384 reg = <0x98 0x4>; 385 #reset-cells = <1>; 386 }; 387 388 ibt: ibt@140 { 389 compatible = "aspeed,ast2400-ibt-bmc"; 390 reg = <0x140 0x18>; 391 interrupts = <8>; 392 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 393 status = "disabled"; 394 }; 395 396 uart_routing: uart-routing@9c { 397 compatible = "aspeed,ast2400-uart-routing"; 398 reg = <0x9c 0x4>; 399 status = "disabled"; 400 }; 401 }; 402 403 peci0: peci-controller@1e78b000 { 404 compatible = "aspeed,ast2400-peci"; 405 reg = <0x1e78b000 0x60>; 406 interrupts = <15>; 407 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; 408 resets = <&syscon ASPEED_RESET_PECI>; 409 cmd-timeout-ms = <1000>; 410 clock-frequency = <1000000>; 411 status = "disabled"; 412 }; 413 414 uart2: serial@1e78d000 { 415 compatible = "ns16550a"; 416 reg = <0x1e78d000 0x20>; 417 reg-shift = <2>; 418 interrupts = <32>; 419 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 420 resets = <&lpc_reset 5>; 421 no-loopback-test; 422 status = "disabled"; 423 }; 424 425 uart3: serial@1e78e000 { 426 compatible = "ns16550a"; 427 reg = <0x1e78e000 0x20>; 428 reg-shift = <2>; 429 interrupts = <33>; 430 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 431 resets = <&lpc_reset 6>; 432 no-loopback-test; 433 status = "disabled"; 434 }; 435 436 uart4: serial@1e78f000 { 437 compatible = "ns16550a"; 438 reg = <0x1e78f000 0x20>; 439 reg-shift = <2>; 440 interrupts = <34>; 441 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 442 resets = <&lpc_reset 7>; 443 no-loopback-test; 444 status = "disabled"; 445 }; 446 447 i2c: bus@1e78a000 { 448 compatible = "simple-bus"; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 ranges = <0 0x1e78a000 0x1000>; 452 }; 453 }; 454 }; 455}; 456 457&i2c { 458 i2c_ic: interrupt-controller@0 { 459 #interrupt-cells = <1>; 460 compatible = "aspeed,ast2400-i2c-ic"; 461 reg = <0x0 0x40>; 462 interrupts = <12>; 463 interrupt-controller; 464 }; 465 466 i2c0: i2c-bus@40 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 #interrupt-cells = <1>; 470 471 reg = <0x40 0x40>; 472 compatible = "aspeed,ast2400-i2c-bus"; 473 clocks = <&syscon ASPEED_CLK_APB>; 474 resets = <&syscon ASPEED_RESET_I2C>; 475 bus-frequency = <100000>; 476 interrupts = <0>; 477 interrupt-parent = <&i2c_ic>; 478 status = "disabled"; 479 /* Does not need pinctrl properties */ 480 }; 481 482 i2c1: i2c-bus@80 { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 #interrupt-cells = <1>; 486 487 reg = <0x80 0x40>; 488 compatible = "aspeed,ast2400-i2c-bus"; 489 clocks = <&syscon ASPEED_CLK_APB>; 490 resets = <&syscon ASPEED_RESET_I2C>; 491 bus-frequency = <100000>; 492 interrupts = <1>; 493 interrupt-parent = <&i2c_ic>; 494 status = "disabled"; 495 /* Does not need pinctrl properties */ 496 }; 497 498 i2c2: i2c-bus@c0 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 #interrupt-cells = <1>; 502 503 reg = <0xc0 0x40>; 504 compatible = "aspeed,ast2400-i2c-bus"; 505 clocks = <&syscon ASPEED_CLK_APB>; 506 resets = <&syscon ASPEED_RESET_I2C>; 507 bus-frequency = <100000>; 508 interrupts = <2>; 509 interrupt-parent = <&i2c_ic>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pinctrl_i2c3_default>; 512 status = "disabled"; 513 }; 514 515 i2c3: i2c-bus@100 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 #interrupt-cells = <1>; 519 520 reg = <0x100 0x40>; 521 compatible = "aspeed,ast2400-i2c-bus"; 522 clocks = <&syscon ASPEED_CLK_APB>; 523 resets = <&syscon ASPEED_RESET_I2C>; 524 bus-frequency = <100000>; 525 interrupts = <3>; 526 interrupt-parent = <&i2c_ic>; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&pinctrl_i2c4_default>; 529 status = "disabled"; 530 }; 531 532 i2c4: i2c-bus@140 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 #interrupt-cells = <1>; 536 537 reg = <0x140 0x40>; 538 compatible = "aspeed,ast2400-i2c-bus"; 539 clocks = <&syscon ASPEED_CLK_APB>; 540 resets = <&syscon ASPEED_RESET_I2C>; 541 bus-frequency = <100000>; 542 interrupts = <4>; 543 interrupt-parent = <&i2c_ic>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_i2c5_default>; 546 status = "disabled"; 547 }; 548 549 i2c5: i2c-bus@180 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 #interrupt-cells = <1>; 553 554 reg = <0x180 0x40>; 555 compatible = "aspeed,ast2400-i2c-bus"; 556 clocks = <&syscon ASPEED_CLK_APB>; 557 resets = <&syscon ASPEED_RESET_I2C>; 558 bus-frequency = <100000>; 559 interrupts = <5>; 560 interrupt-parent = <&i2c_ic>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_i2c6_default>; 563 status = "disabled"; 564 }; 565 566 i2c6: i2c-bus@1c0 { 567 #address-cells = <1>; 568 #size-cells = <0>; 569 #interrupt-cells = <1>; 570 571 reg = <0x1c0 0x40>; 572 compatible = "aspeed,ast2400-i2c-bus"; 573 clocks = <&syscon ASPEED_CLK_APB>; 574 resets = <&syscon ASPEED_RESET_I2C>; 575 bus-frequency = <100000>; 576 interrupts = <6>; 577 interrupt-parent = <&i2c_ic>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_i2c7_default>; 580 status = "disabled"; 581 }; 582 583 i2c7: i2c-bus@300 { 584 #address-cells = <1>; 585 #size-cells = <0>; 586 #interrupt-cells = <1>; 587 588 reg = <0x300 0x40>; 589 compatible = "aspeed,ast2400-i2c-bus"; 590 clocks = <&syscon ASPEED_CLK_APB>; 591 resets = <&syscon ASPEED_RESET_I2C>; 592 bus-frequency = <100000>; 593 interrupts = <7>; 594 interrupt-parent = <&i2c_ic>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&pinctrl_i2c8_default>; 597 status = "disabled"; 598 }; 599 600 i2c8: i2c-bus@340 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 #interrupt-cells = <1>; 604 605 reg = <0x340 0x40>; 606 compatible = "aspeed,ast2400-i2c-bus"; 607 clocks = <&syscon ASPEED_CLK_APB>; 608 resets = <&syscon ASPEED_RESET_I2C>; 609 bus-frequency = <100000>; 610 interrupts = <8>; 611 interrupt-parent = <&i2c_ic>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pinctrl_i2c9_default>; 614 status = "disabled"; 615 }; 616 617 i2c9: i2c-bus@380 { 618 #address-cells = <1>; 619 #size-cells = <0>; 620 #interrupt-cells = <1>; 621 622 reg = <0x380 0x40>; 623 compatible = "aspeed,ast2400-i2c-bus"; 624 clocks = <&syscon ASPEED_CLK_APB>; 625 resets = <&syscon ASPEED_RESET_I2C>; 626 bus-frequency = <100000>; 627 interrupts = <9>; 628 interrupt-parent = <&i2c_ic>; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&pinctrl_i2c10_default>; 631 status = "disabled"; 632 }; 633 634 i2c10: i2c-bus@3c0 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 #interrupt-cells = <1>; 638 639 reg = <0x3c0 0x40>; 640 compatible = "aspeed,ast2400-i2c-bus"; 641 clocks = <&syscon ASPEED_CLK_APB>; 642 resets = <&syscon ASPEED_RESET_I2C>; 643 bus-frequency = <100000>; 644 interrupts = <10>; 645 interrupt-parent = <&i2c_ic>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_i2c11_default>; 648 status = "disabled"; 649 }; 650 651 i2c11: i2c-bus@400 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 #interrupt-cells = <1>; 655 656 reg = <0x400 0x40>; 657 compatible = "aspeed,ast2400-i2c-bus"; 658 clocks = <&syscon ASPEED_CLK_APB>; 659 resets = <&syscon ASPEED_RESET_I2C>; 660 bus-frequency = <100000>; 661 interrupts = <11>; 662 interrupt-parent = <&i2c_ic>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&pinctrl_i2c12_default>; 665 status = "disabled"; 666 }; 667 668 i2c12: i2c-bus@440 { 669 #address-cells = <1>; 670 #size-cells = <0>; 671 #interrupt-cells = <1>; 672 673 reg = <0x440 0x40>; 674 compatible = "aspeed,ast2400-i2c-bus"; 675 clocks = <&syscon ASPEED_CLK_APB>; 676 resets = <&syscon ASPEED_RESET_I2C>; 677 bus-frequency = <100000>; 678 interrupts = <12>; 679 interrupt-parent = <&i2c_ic>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_i2c13_default>; 682 status = "disabled"; 683 }; 684 685 i2c13: i2c-bus@480 { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 #interrupt-cells = <1>; 689 690 reg = <0x480 0x40>; 691 compatible = "aspeed,ast2400-i2c-bus"; 692 clocks = <&syscon ASPEED_CLK_APB>; 693 resets = <&syscon ASPEED_RESET_I2C>; 694 bus-frequency = <100000>; 695 interrupts = <13>; 696 interrupt-parent = <&i2c_ic>; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&pinctrl_i2c14_default>; 699 status = "disabled"; 700 }; 701}; 702 703&pinctrl { 704 pinctrl_acpi_default: acpi_default { 705 function = "ACPI"; 706 groups = "ACPI"; 707 }; 708 709 pinctrl_adc0_default: adc0_default { 710 function = "ADC0"; 711 groups = "ADC0"; 712 }; 713 714 pinctrl_adc1_default: adc1_default { 715 function = "ADC1"; 716 groups = "ADC1"; 717 }; 718 719 pinctrl_adc10_default: adc10_default { 720 function = "ADC10"; 721 groups = "ADC10"; 722 }; 723 724 pinctrl_adc11_default: adc11_default { 725 function = "ADC11"; 726 groups = "ADC11"; 727 }; 728 729 pinctrl_adc12_default: adc12_default { 730 function = "ADC12"; 731 groups = "ADC12"; 732 }; 733 734 pinctrl_adc13_default: adc13_default { 735 function = "ADC13"; 736 groups = "ADC13"; 737 }; 738 739 pinctrl_adc14_default: adc14_default { 740 function = "ADC14"; 741 groups = "ADC14"; 742 }; 743 744 pinctrl_adc15_default: adc15_default { 745 function = "ADC15"; 746 groups = "ADC15"; 747 }; 748 749 pinctrl_adc2_default: adc2_default { 750 function = "ADC2"; 751 groups = "ADC2"; 752 }; 753 754 pinctrl_adc3_default: adc3_default { 755 function = "ADC3"; 756 groups = "ADC3"; 757 }; 758 759 pinctrl_adc4_default: adc4_default { 760 function = "ADC4"; 761 groups = "ADC4"; 762 }; 763 764 pinctrl_adc5_default: adc5_default { 765 function = "ADC5"; 766 groups = "ADC5"; 767 }; 768 769 pinctrl_adc6_default: adc6_default { 770 function = "ADC6"; 771 groups = "ADC6"; 772 }; 773 774 pinctrl_adc7_default: adc7_default { 775 function = "ADC7"; 776 groups = "ADC7"; 777 }; 778 779 pinctrl_adc8_default: adc8_default { 780 function = "ADC8"; 781 groups = "ADC8"; 782 }; 783 784 pinctrl_adc9_default: adc9_default { 785 function = "ADC9"; 786 groups = "ADC9"; 787 }; 788 789 pinctrl_bmcint_default: bmcint_default { 790 function = "BMCINT"; 791 groups = "BMCINT"; 792 }; 793 794 pinctrl_ddcclk_default: ddcclk_default { 795 function = "DDCCLK"; 796 groups = "DDCCLK"; 797 }; 798 799 pinctrl_ddcdat_default: ddcdat_default { 800 function = "DDCDAT"; 801 groups = "DDCDAT"; 802 }; 803 804 pinctrl_extrst_default: extrst_default { 805 function = "EXTRST"; 806 groups = "EXTRST"; 807 }; 808 809 pinctrl_flack_default: flack_default { 810 function = "FLACK"; 811 groups = "FLACK"; 812 }; 813 814 pinctrl_flbusy_default: flbusy_default { 815 function = "FLBUSY"; 816 groups = "FLBUSY"; 817 }; 818 819 pinctrl_flwp_default: flwp_default { 820 function = "FLWP"; 821 groups = "FLWP"; 822 }; 823 824 pinctrl_gpid_default: gpid_default { 825 function = "GPID"; 826 groups = "GPID"; 827 }; 828 829 pinctrl_gpid0_default: gpid0_default { 830 function = "GPID0"; 831 groups = "GPID0"; 832 }; 833 834 pinctrl_gpid2_default: gpid2_default { 835 function = "GPID2"; 836 groups = "GPID2"; 837 }; 838 839 pinctrl_gpid4_default: gpid4_default { 840 function = "GPID4"; 841 groups = "GPID4"; 842 }; 843 844 pinctrl_gpid6_default: gpid6_default { 845 function = "GPID6"; 846 groups = "GPID6"; 847 }; 848 849 pinctrl_gpie0_default: gpie0_default { 850 function = "GPIE0"; 851 groups = "GPIE0"; 852 }; 853 854 pinctrl_gpie2_default: gpie2_default { 855 function = "GPIE2"; 856 groups = "GPIE2"; 857 }; 858 859 pinctrl_gpie4_default: gpie4_default { 860 function = "GPIE4"; 861 groups = "GPIE4"; 862 }; 863 864 pinctrl_gpie6_default: gpie6_default { 865 function = "GPIE6"; 866 groups = "GPIE6"; 867 }; 868 869 pinctrl_i2c10_default: i2c10_default { 870 function = "I2C10"; 871 groups = "I2C10"; 872 }; 873 874 pinctrl_i2c11_default: i2c11_default { 875 function = "I2C11"; 876 groups = "I2C11"; 877 }; 878 879 pinctrl_i2c12_default: i2c12_default { 880 function = "I2C12"; 881 groups = "I2C12"; 882 }; 883 884 pinctrl_i2c13_default: i2c13_default { 885 function = "I2C13"; 886 groups = "I2C13"; 887 }; 888 889 pinctrl_i2c14_default: i2c14_default { 890 function = "I2C14"; 891 groups = "I2C14"; 892 }; 893 894 pinctrl_i2c3_default: i2c3_default { 895 function = "I2C3"; 896 groups = "I2C3"; 897 }; 898 899 pinctrl_i2c4_default: i2c4_default { 900 function = "I2C4"; 901 groups = "I2C4"; 902 }; 903 904 pinctrl_i2c5_default: i2c5_default { 905 function = "I2C5"; 906 groups = "I2C5"; 907 }; 908 909 pinctrl_i2c6_default: i2c6_default { 910 function = "I2C6"; 911 groups = "I2C6"; 912 }; 913 914 pinctrl_i2c7_default: i2c7_default { 915 function = "I2C7"; 916 groups = "I2C7"; 917 }; 918 919 pinctrl_i2c8_default: i2c8_default { 920 function = "I2C8"; 921 groups = "I2C8"; 922 }; 923 924 pinctrl_i2c9_default: i2c9_default { 925 function = "I2C9"; 926 groups = "I2C9"; 927 }; 928 929 pinctrl_lpcpd_default: lpcpd_default { 930 function = "LPCPD"; 931 groups = "LPCPD"; 932 }; 933 934 pinctrl_lpcpme_default: lpcpme_default { 935 function = "LPCPME"; 936 groups = "LPCPME"; 937 }; 938 939 pinctrl_lpcrst_default: lpcrst_default { 940 function = "LPCRST"; 941 groups = "LPCRST"; 942 }; 943 944 pinctrl_lpcsmi_default: lpcsmi_default { 945 function = "LPCSMI"; 946 groups = "LPCSMI"; 947 }; 948 949 pinctrl_mac1link_default: mac1link_default { 950 function = "MAC1LINK"; 951 groups = "MAC1LINK"; 952 }; 953 954 pinctrl_mac2link_default: mac2link_default { 955 function = "MAC2LINK"; 956 groups = "MAC2LINK"; 957 }; 958 959 pinctrl_mdio1_default: mdio1_default { 960 function = "MDIO1"; 961 groups = "MDIO1"; 962 }; 963 964 pinctrl_mdio2_default: mdio2_default { 965 function = "MDIO2"; 966 groups = "MDIO2"; 967 }; 968 969 pinctrl_ncts1_default: ncts1_default { 970 function = "NCTS1"; 971 groups = "NCTS1"; 972 }; 973 974 pinctrl_ncts2_default: ncts2_default { 975 function = "NCTS2"; 976 groups = "NCTS2"; 977 }; 978 979 pinctrl_ncts3_default: ncts3_default { 980 function = "NCTS3"; 981 groups = "NCTS3"; 982 }; 983 984 pinctrl_ncts4_default: ncts4_default { 985 function = "NCTS4"; 986 groups = "NCTS4"; 987 }; 988 989 pinctrl_ndcd1_default: ndcd1_default { 990 function = "NDCD1"; 991 groups = "NDCD1"; 992 }; 993 994 pinctrl_ndcd2_default: ndcd2_default { 995 function = "NDCD2"; 996 groups = "NDCD2"; 997 }; 998 999 pinctrl_ndcd3_default: ndcd3_default { 1000 function = "NDCD3"; 1001 groups = "NDCD3"; 1002 }; 1003 1004 pinctrl_ndcd4_default: ndcd4_default { 1005 function = "NDCD4"; 1006 groups = "NDCD4"; 1007 }; 1008 1009 pinctrl_ndsr1_default: ndsr1_default { 1010 function = "NDSR1"; 1011 groups = "NDSR1"; 1012 }; 1013 1014 pinctrl_ndsr2_default: ndsr2_default { 1015 function = "NDSR2"; 1016 groups = "NDSR2"; 1017 }; 1018 1019 pinctrl_ndsr3_default: ndsr3_default { 1020 function = "NDSR3"; 1021 groups = "NDSR3"; 1022 }; 1023 1024 pinctrl_ndsr4_default: ndsr4_default { 1025 function = "NDSR4"; 1026 groups = "NDSR4"; 1027 }; 1028 1029 pinctrl_ndtr1_default: ndtr1_default { 1030 function = "NDTR1"; 1031 groups = "NDTR1"; 1032 }; 1033 1034 pinctrl_ndtr2_default: ndtr2_default { 1035 function = "NDTR2"; 1036 groups = "NDTR2"; 1037 }; 1038 1039 pinctrl_ndtr3_default: ndtr3_default { 1040 function = "NDTR3"; 1041 groups = "NDTR3"; 1042 }; 1043 1044 pinctrl_ndtr4_default: ndtr4_default { 1045 function = "NDTR4"; 1046 groups = "NDTR4"; 1047 }; 1048 1049 pinctrl_ndts4_default: ndts4_default { 1050 function = "NDTS4"; 1051 groups = "NDTS4"; 1052 }; 1053 1054 pinctrl_nri1_default: nri1_default { 1055 function = "NRI1"; 1056 groups = "NRI1"; 1057 }; 1058 1059 pinctrl_nri2_default: nri2_default { 1060 function = "NRI2"; 1061 groups = "NRI2"; 1062 }; 1063 1064 pinctrl_nri3_default: nri3_default { 1065 function = "NRI3"; 1066 groups = "NRI3"; 1067 }; 1068 1069 pinctrl_nri4_default: nri4_default { 1070 function = "NRI4"; 1071 groups = "NRI4"; 1072 }; 1073 1074 pinctrl_nrts1_default: nrts1_default { 1075 function = "NRTS1"; 1076 groups = "NRTS1"; 1077 }; 1078 1079 pinctrl_nrts2_default: nrts2_default { 1080 function = "NRTS2"; 1081 groups = "NRTS2"; 1082 }; 1083 1084 pinctrl_nrts3_default: nrts3_default { 1085 function = "NRTS3"; 1086 groups = "NRTS3"; 1087 }; 1088 1089 pinctrl_oscclk_default: oscclk_default { 1090 function = "OSCCLK"; 1091 groups = "OSCCLK"; 1092 }; 1093 1094 pinctrl_pwm0_default: pwm0_default { 1095 function = "PWM0"; 1096 groups = "PWM0"; 1097 }; 1098 1099 pinctrl_pwm1_default: pwm1_default { 1100 function = "PWM1"; 1101 groups = "PWM1"; 1102 }; 1103 1104 pinctrl_pwm2_default: pwm2_default { 1105 function = "PWM2"; 1106 groups = "PWM2"; 1107 }; 1108 1109 pinctrl_pwm3_default: pwm3_default { 1110 function = "PWM3"; 1111 groups = "PWM3"; 1112 }; 1113 1114 pinctrl_pwm4_default: pwm4_default { 1115 function = "PWM4"; 1116 groups = "PWM4"; 1117 }; 1118 1119 pinctrl_pwm5_default: pwm5_default { 1120 function = "PWM5"; 1121 groups = "PWM5"; 1122 }; 1123 1124 pinctrl_pwm6_default: pwm6_default { 1125 function = "PWM6"; 1126 groups = "PWM6"; 1127 }; 1128 1129 pinctrl_pwm7_default: pwm7_default { 1130 function = "PWM7"; 1131 groups = "PWM7"; 1132 }; 1133 1134 pinctrl_rgmii1_default: rgmii1_default { 1135 function = "RGMII1"; 1136 groups = "RGMII1"; 1137 }; 1138 1139 pinctrl_rgmii2_default: rgmii2_default { 1140 function = "RGMII2"; 1141 groups = "RGMII2"; 1142 }; 1143 1144 pinctrl_rmii1_default: rmii1_default { 1145 function = "RMII1"; 1146 groups = "RMII1"; 1147 }; 1148 1149 pinctrl_rmii2_default: rmii2_default { 1150 function = "RMII2"; 1151 groups = "RMII2"; 1152 }; 1153 1154 pinctrl_rom16_default: rom16_default { 1155 function = "ROM16"; 1156 groups = "ROM16"; 1157 }; 1158 1159 pinctrl_rom8_default: rom8_default { 1160 function = "ROM8"; 1161 groups = "ROM8"; 1162 }; 1163 1164 pinctrl_romcs1_default: romcs1_default { 1165 function = "ROMCS1"; 1166 groups = "ROMCS1"; 1167 }; 1168 1169 pinctrl_romcs2_default: romcs2_default { 1170 function = "ROMCS2"; 1171 groups = "ROMCS2"; 1172 }; 1173 1174 pinctrl_romcs3_default: romcs3_default { 1175 function = "ROMCS3"; 1176 groups = "ROMCS3"; 1177 }; 1178 1179 pinctrl_romcs4_default: romcs4_default { 1180 function = "ROMCS4"; 1181 groups = "ROMCS4"; 1182 }; 1183 1184 pinctrl_rxd1_default: rxd1_default { 1185 function = "RXD1"; 1186 groups = "RXD1"; 1187 }; 1188 1189 pinctrl_rxd2_default: rxd2_default { 1190 function = "RXD2"; 1191 groups = "RXD2"; 1192 }; 1193 1194 pinctrl_rxd3_default: rxd3_default { 1195 function = "RXD3"; 1196 groups = "RXD3"; 1197 }; 1198 1199 pinctrl_rxd4_default: rxd4_default { 1200 function = "RXD4"; 1201 groups = "RXD4"; 1202 }; 1203 1204 pinctrl_salt1_default: salt1_default { 1205 function = "SALT1"; 1206 groups = "SALT1"; 1207 }; 1208 1209 pinctrl_salt2_default: salt2_default { 1210 function = "SALT2"; 1211 groups = "SALT2"; 1212 }; 1213 1214 pinctrl_salt3_default: salt3_default { 1215 function = "SALT3"; 1216 groups = "SALT3"; 1217 }; 1218 1219 pinctrl_salt4_default: salt4_default { 1220 function = "SALT4"; 1221 groups = "SALT4"; 1222 }; 1223 1224 pinctrl_sd1_default: sd1_default { 1225 function = "SD1"; 1226 groups = "SD1"; 1227 }; 1228 1229 pinctrl_sd2_default: sd2_default { 1230 function = "SD2"; 1231 groups = "SD2"; 1232 }; 1233 1234 pinctrl_sgpmck_default: sgpmck_default { 1235 function = "SGPMCK"; 1236 groups = "SGPMCK"; 1237 }; 1238 1239 pinctrl_sgpmi_default: sgpmi_default { 1240 function = "SGPMI"; 1241 groups = "SGPMI"; 1242 }; 1243 1244 pinctrl_sgpmld_default: sgpmld_default { 1245 function = "SGPMLD"; 1246 groups = "SGPMLD"; 1247 }; 1248 1249 pinctrl_sgpmo_default: sgpmo_default { 1250 function = "SGPMO"; 1251 groups = "SGPMO"; 1252 }; 1253 1254 pinctrl_sgpsck_default: sgpsck_default { 1255 function = "SGPSCK"; 1256 groups = "SGPSCK"; 1257 }; 1258 1259 pinctrl_sgpsi0_default: sgpsi0_default { 1260 function = "SGPSI0"; 1261 groups = "SGPSI0"; 1262 }; 1263 1264 pinctrl_sgpsi1_default: sgpsi1_default { 1265 function = "SGPSI1"; 1266 groups = "SGPSI1"; 1267 }; 1268 1269 pinctrl_sgpsld_default: sgpsld_default { 1270 function = "SGPSLD"; 1271 groups = "SGPSLD"; 1272 }; 1273 1274 pinctrl_sioonctrl_default: sioonctrl_default { 1275 function = "SIOONCTRL"; 1276 groups = "SIOONCTRL"; 1277 }; 1278 1279 pinctrl_siopbi_default: siopbi_default { 1280 function = "SIOPBI"; 1281 groups = "SIOPBI"; 1282 }; 1283 1284 pinctrl_siopbo_default: siopbo_default { 1285 function = "SIOPBO"; 1286 groups = "SIOPBO"; 1287 }; 1288 1289 pinctrl_siopwreq_default: siopwreq_default { 1290 function = "SIOPWREQ"; 1291 groups = "SIOPWREQ"; 1292 }; 1293 1294 pinctrl_siopwrgd_default: siopwrgd_default { 1295 function = "SIOPWRGD"; 1296 groups = "SIOPWRGD"; 1297 }; 1298 1299 pinctrl_sios3_default: sios3_default { 1300 function = "SIOS3"; 1301 groups = "SIOS3"; 1302 }; 1303 1304 pinctrl_sios5_default: sios5_default { 1305 function = "SIOS5"; 1306 groups = "SIOS5"; 1307 }; 1308 1309 pinctrl_siosci_default: siosci_default { 1310 function = "SIOSCI"; 1311 groups = "SIOSCI"; 1312 }; 1313 1314 pinctrl_spi1_default: spi1_default { 1315 function = "SPI1"; 1316 groups = "SPI1"; 1317 }; 1318 1319 pinctrl_spi1debug_default: spi1debug_default { 1320 function = "SPI1DEBUG"; 1321 groups = "SPI1DEBUG"; 1322 }; 1323 1324 pinctrl_spi1passthru_default: spi1passthru_default { 1325 function = "SPI1PASSTHRU"; 1326 groups = "SPI1PASSTHRU"; 1327 }; 1328 1329 pinctrl_spics1_default: spics1_default { 1330 function = "SPICS1"; 1331 groups = "SPICS1"; 1332 }; 1333 1334 pinctrl_timer3_default: timer3_default { 1335 function = "TIMER3"; 1336 groups = "TIMER3"; 1337 }; 1338 1339 pinctrl_timer4_default: timer4_default { 1340 function = "TIMER4"; 1341 groups = "TIMER4"; 1342 }; 1343 1344 pinctrl_timer5_default: timer5_default { 1345 function = "TIMER5"; 1346 groups = "TIMER5"; 1347 }; 1348 1349 pinctrl_timer6_default: timer6_default { 1350 function = "TIMER6"; 1351 groups = "TIMER6"; 1352 }; 1353 1354 pinctrl_timer7_default: timer7_default { 1355 function = "TIMER7"; 1356 groups = "TIMER7"; 1357 }; 1358 1359 pinctrl_timer8_default: timer8_default { 1360 function = "TIMER8"; 1361 groups = "TIMER8"; 1362 }; 1363 1364 pinctrl_txd1_default: txd1_default { 1365 function = "TXD1"; 1366 groups = "TXD1"; 1367 }; 1368 1369 pinctrl_txd2_default: txd2_default { 1370 function = "TXD2"; 1371 groups = "TXD2"; 1372 }; 1373 1374 pinctrl_txd3_default: txd3_default { 1375 function = "TXD3"; 1376 groups = "TXD3"; 1377 }; 1378 1379 pinctrl_txd4_default: txd4_default { 1380 function = "TXD4"; 1381 groups = "TXD4"; 1382 }; 1383 1384 pinctrl_uart6_default: uart6_default { 1385 function = "UART6"; 1386 groups = "UART6"; 1387 }; 1388 1389 pinctrl_usbcki_default: usbcki_default { 1390 function = "USBCKI"; 1391 groups = "USBCKI"; 1392 }; 1393 1394 pinctrl_usb2h_default: usb2h_default { 1395 function = "USB2H1"; 1396 groups = "USB2H1"; 1397 }; 1398 1399 pinctrl_usb2d_default: usb2d_default { 1400 function = "USB2D1"; 1401 groups = "USB2D1"; 1402 }; 1403 1404 pinctrl_vgabios_rom_default: vgabios_rom_default { 1405 function = "VGABIOS_ROM"; 1406 groups = "VGABIOS_ROM"; 1407 }; 1408 1409 pinctrl_vgahs_default: vgahs_default { 1410 function = "VGAHS"; 1411 groups = "VGAHS"; 1412 }; 1413 1414 pinctrl_vgavs_default: vgavs_default { 1415 function = "VGAVS"; 1416 groups = "VGAVS"; 1417 }; 1418 1419 pinctrl_vpi18_default: vpi18_default { 1420 function = "VPI18"; 1421 groups = "VPI18"; 1422 }; 1423 1424 pinctrl_vpi24_default: vpi24_default { 1425 function = "VPI24"; 1426 groups = "VPI24"; 1427 }; 1428 1429 pinctrl_vpi30_default: vpi30_default { 1430 function = "VPI30"; 1431 groups = "VPI30"; 1432 }; 1433 1434 pinctrl_vpo12_default: vpo12_default { 1435 function = "VPO12"; 1436 groups = "VPO12"; 1437 }; 1438 1439 pinctrl_vpo24_default: vpo24_default { 1440 function = "VPO24"; 1441 groups = "VPO24"; 1442 }; 1443 1444 pinctrl_wdtrst1_default: wdtrst1_default { 1445 function = "WDTRST1"; 1446 groups = "WDTRST1"; 1447 }; 1448 1449 pinctrl_wdtrst2_default: wdtrst2_default { 1450 function = "WDTRST2"; 1451 groups = "WDTRST2"; 1452 }; 1453}; 1454