xref: /freebsd/sys/contrib/device-tree/src/arm/aspeed/aspeed-bmc-facebook-wedge400.dts (revision e1e636193db45630c7881246d25902e57c43d24e) 
1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2019 Facebook Inc.
3/dts-v1/;
4
5#include <dt-bindings/gpio/aspeed-gpio.h>
6#include "ast2500-facebook-netbmc-common.dtsi"
7
8/ {
9	model = "Facebook Wedge 400 BMC";
10	compatible = "facebook,wedge400-bmc", "aspeed,ast2500";
11
12	aliases {
13		/*
14		 * PCA9548 (2-0070) provides 8 channels connecting to
15		 * SCM (System Controller Module).
16		 */
17		i2c16 = &imux16;
18		i2c17 = &imux17;
19		i2c18 = &imux18;
20		i2c19 = &imux19;
21		i2c20 = &imux20;
22		i2c21 = &imux21;
23		i2c22 = &imux22;
24		i2c23 = &imux23;
25
26		/*
27		 * PCA9548 (8-0070) provides 8 channels connecting to
28		 * SMB (Switch Main Board).
29		 */
30		i2c24 = &imux24;
31		i2c25 = &imux25;
32		i2c26 = &imux26;
33		i2c27 = &imux27;
34		i2c28 = &imux28;
35		i2c29 = &imux29;
36		i2c30 = &imux30;
37		i2c31 = &imux31;
38
39		/*
40		 * PCA9548 (11-0076) provides 8 channels connecting to
41		 * FCM (Fan Controller Module).
42		 */
43		i2c32 = &imux32;
44		i2c33 = &imux33;
45		i2c34 = &imux34;
46		i2c35 = &imux35;
47		i2c36 = &imux36;
48		i2c37 = &imux37;
49		i2c38 = &imux38;
50		i2c39 = &imux39;
51
52		spi2 = &spi_gpio;
53	};
54
55	chosen {
56		stdout-path = &uart1;
57		bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
58	};
59
60	ast-adc-hwmon {
61		compatible = "iio-hwmon";
62		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
63	};
64
65	/*
66	 * GPIO-based SPI Master is required to access SPI TPM, because
67	 * full-duplex SPI transactions are not supported by ASPEED SPI
68	 * Controllers.
69	 */
70	spi_gpio: spi {
71		status = "okay";
72		compatible = "spi-gpio";
73		#address-cells = <1>;
74		#size-cells = <0>;
75
76		cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>;
77		gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
78		gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
79		gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
80		num-chipselects = <1>;
81
82		tpmdev@0 {
83			compatible = "tcg,tpm_tis-spi";
84			spi-max-frequency = <33000000>;
85			reg = <0>;
86		};
87	};
88};
89
90/*
91 * Both firmware flashes are 128MB on Wedge400 BMC.
92 */
93&fmc_flash0 {
94#include "facebook-bmc-flash-layout-128.dtsi"
95};
96
97&fmc_flash1 {
98	partitions {
99		compatible = "fixed-partitions";
100		#address-cells = <1>;
101		#size-cells = <1>;
102
103		flash1@0 {
104			reg = <0x0 0x8000000>;
105			label = "flash1";
106		};
107	};
108};
109
110&uart2 {
111	status = "okay";
112	pinctrl-names = "default";
113	pinctrl-0 = <&pinctrl_txd2_default
114		     &pinctrl_rxd2_default>;
115};
116
117&uart4 {
118	status = "okay";
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_txd4_default
121		     &pinctrl_rxd4_default>;
122};
123
124/*
125 * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC
126 * communication.
127 */
128&i2c0 {
129	status = "okay";
130	multi-master;
131	bus-frequency = <1000000>;
132};
133
134&i2c1 {
135	status = "okay";
136};
137
138&i2c2 {
139	status = "okay";
140
141	i2c-switch@70 {
142		compatible = "nxp,pca9548";
143		#address-cells = <1>;
144		#size-cells = <0>;
145		reg = <0x70>;
146		i2c-mux-idle-disconnect;
147
148		imux16: i2c@0 {
149			#address-cells = <1>;
150			#size-cells = <0>;
151			reg = <0>;
152		};
153
154		imux17: i2c@1 {
155			#address-cells = <1>;
156			#size-cells = <0>;
157			reg = <1>;
158		};
159
160		imux18: i2c@2 {
161			#address-cells = <1>;
162			#size-cells = <0>;
163			reg = <2>;
164		};
165
166		imux19: i2c@3 {
167			#address-cells = <1>;
168			#size-cells = <0>;
169			reg = <3>;
170		};
171
172		imux20: i2c@4 {
173			#address-cells = <1>;
174			#size-cells = <0>;
175			reg = <4>;
176		};
177
178		imux21: i2c@5 {
179			#address-cells = <1>;
180			#size-cells = <0>;
181			reg = <5>;
182		};
183
184		imux22: i2c@6 {
185			#address-cells = <1>;
186			#size-cells = <0>;
187			reg = <6>;
188		};
189
190		imux23: i2c@7 {
191			#address-cells = <1>;
192			#size-cells = <0>;
193			reg = <7>;
194		};
195	};
196};
197
198&i2c3 {
199	status = "okay";
200};
201
202&i2c4 {
203	status = "okay";
204};
205
206&i2c5 {
207	status = "okay";
208};
209
210&i2c6 {
211	status = "okay";
212};
213
214&i2c7 {
215	status = "okay";
216};
217
218&i2c8 {
219	status = "okay";
220
221	i2c-switch@70 {
222		compatible = "nxp,pca9548";
223		#address-cells = <1>;
224		#size-cells = <0>;
225		reg = <0x70>;
226		i2c-mux-idle-disconnect;
227
228		imux24: i2c@0 {
229			#address-cells = <1>;
230			#size-cells = <0>;
231			reg = <0>;
232		};
233
234		imux25: i2c@1 {
235			#address-cells = <1>;
236			#size-cells = <0>;
237			reg = <1>;
238		};
239
240		imux26: i2c@2 {
241			#address-cells = <1>;
242			#size-cells = <0>;
243			reg = <2>;
244		};
245
246		imux27: i2c@3 {
247			#address-cells = <1>;
248			#size-cells = <0>;
249			reg = <3>;
250		};
251
252		imux28: i2c@4 {
253			#address-cells = <1>;
254			#size-cells = <0>;
255			reg = <4>;
256		};
257
258		imux29: i2c@5 {
259			#address-cells = <1>;
260			#size-cells = <0>;
261			reg = <5>;
262		};
263
264		imux30: i2c@6 {
265			#address-cells = <1>;
266			#size-cells = <0>;
267			reg = <6>;
268		};
269
270		imux31: i2c@7 {
271			#address-cells = <1>;
272			#size-cells = <0>;
273			reg = <7>;
274		};
275
276	};
277};
278
279&i2c9 {
280	status = "okay";
281};
282
283&i2c10 {
284	status = "okay";
285};
286
287&i2c11 {
288	status = "okay";
289
290	i2c-switch@76 {
291		compatible = "nxp,pca9548";
292		#address-cells = <1>;
293		#size-cells = <0>;
294		reg = <0x76>;
295		i2c-mux-idle-disconnect;
296
297		imux32: i2c@0 {
298			#address-cells = <1>;
299			#size-cells = <0>;
300			reg = <0>;
301		};
302
303		imux33: i2c@1 {
304			#address-cells = <1>;
305			#size-cells = <0>;
306			reg = <1>;
307		};
308
309		imux34: i2c@2 {
310			#address-cells = <1>;
311			#size-cells = <0>;
312			reg = <2>;
313		};
314
315		imux35: i2c@3 {
316			#address-cells = <1>;
317			#size-cells = <0>;
318			reg = <3>;
319		};
320
321		imux36: i2c@4 {
322			#address-cells = <1>;
323			#size-cells = <0>;
324			reg = <4>;
325		};
326
327		imux37: i2c@5 {
328			#address-cells = <1>;
329			#size-cells = <0>;
330			reg = <5>;
331		};
332
333		imux38: i2c@6 {
334			#address-cells = <1>;
335			#size-cells = <0>;
336			reg = <6>;
337		};
338
339		imux39: i2c@7 {
340			#address-cells = <1>;
341			#size-cells = <0>;
342			reg = <7>;
343		};
344
345	};
346};
347
348&i2c12 {
349	status = "okay";
350};
351
352&i2c13 {
353	status = "okay";
354};
355
356&adc {
357	status = "okay";
358};
359
360&ehci1 {
361	status = "okay";
362};
363
364&uhci {
365	status = "okay";
366};
367
368&sdhci1 {
369	/*
370	 * DMA mode needs to be disabled to avoid conflicts with UHCI
371	 * Controller in AST2500 SoC.
372	 */
373	sdhci-caps-mask = <0x0 0x580000>;
374};
375