1/* 2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/sun6i-rtc.h> 44#include <dt-bindings/clock/sun8i-de2.h> 45#include <dt-bindings/clock/sun8i-h3-ccu.h> 46#include <dt-bindings/clock/sun8i-r-ccu.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/reset/sun8i-de2.h> 49#include <dt-bindings/reset/sun8i-h3-ccu.h> 50#include <dt-bindings/reset/sun8i-r-ccu.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 57 chosen { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges; 61 62 framebuffer-hdmi { 63 compatible = "allwinner,simple-framebuffer", 64 "simple-framebuffer"; 65 allwinner,pipeline = "mixer0-lcd0-hdmi"; 66 clocks = <&display_clocks CLK_MIXER0>, 67 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; 68 status = "disabled"; 69 }; 70 71 framebuffer-tve { 72 compatible = "allwinner,simple-framebuffer", 73 "simple-framebuffer"; 74 allwinner,pipeline = "mixer1-lcd1-tve"; 75 clocks = <&display_clocks CLK_MIXER1>, 76 <&ccu CLK_TVE>; 77 status = "disabled"; 78 }; 79 }; 80 81 clocks { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 osc24M: osc24M_clk { 87 #clock-cells = <0>; 88 compatible = "fixed-clock"; 89 clock-frequency = <24000000>; 90 clock-accuracy = <50000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-accuracy = <50000>; 99 clock-output-names = "ext_osc32k"; 100 }; 101 }; 102 103 de: display-engine { 104 compatible = "allwinner,sun8i-h3-display-engine"; 105 allwinner,pipelines = <&mixer0>; 106 status = "disabled"; 107 }; 108 109 soc { 110 compatible = "simple-bus"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 dma-ranges; 114 ranges; 115 116 display_clocks: clock@1000000 { 117 /* compatible is in per SoC .dtsi file */ 118 reg = <0x01000000 0x10000>; 119 clocks = <&ccu CLK_BUS_DE>, 120 <&ccu CLK_DE>; 121 clock-names = "bus", 122 "mod"; 123 resets = <&ccu RST_BUS_DE>; 124 #clock-cells = <1>; 125 #reset-cells = <1>; 126 }; 127 128 mixer0: mixer@1100000 { 129 compatible = "allwinner,sun8i-h3-de2-mixer-0"; 130 reg = <0x01100000 0x100000>; 131 clocks = <&display_clocks CLK_BUS_MIXER0>, 132 <&display_clocks CLK_MIXER0>; 133 clock-names = "bus", 134 "mod"; 135 resets = <&display_clocks RST_MIXER0>; 136 137 ports { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 141 mixer0_out: port@1 { 142 reg = <1>; 143 144 mixer0_out_tcon0: endpoint { 145 remote-endpoint = <&tcon0_in_mixer0>; 146 }; 147 }; 148 }; 149 }; 150 151 dma: dma-controller@1c02000 { 152 compatible = "allwinner,sun8i-h3-dma"; 153 reg = <0x01c02000 0x1000>; 154 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&ccu CLK_BUS_DMA>; 156 resets = <&ccu RST_BUS_DMA>; 157 #dma-cells = <1>; 158 }; 159 160 tcon0: lcd-controller@1c0c000 { 161 compatible = "allwinner,sun8i-h3-tcon-tv", 162 "allwinner,sun8i-a83t-tcon-tv"; 163 reg = <0x01c0c000 0x1000>; 164 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 166 clock-names = "ahb", "tcon-ch1"; 167 resets = <&ccu RST_BUS_TCON0>; 168 reset-names = "lcd"; 169 170 ports { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 tcon0_in: port@0 { 175 reg = <0>; 176 177 tcon0_in_mixer0: endpoint { 178 remote-endpoint = <&mixer0_out_tcon0>; 179 }; 180 }; 181 182 tcon0_out: port@1 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 reg = <1>; 186 187 tcon0_out_hdmi: endpoint@1 { 188 reg = <1>; 189 remote-endpoint = <&hdmi_in_tcon0>; 190 }; 191 }; 192 }; 193 }; 194 195 mmc0: mmc@1c0f000 { 196 /* compatible and clocks are in per SoC .dtsi file */ 197 reg = <0x01c0f000 0x1000>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&mmc0_pins>; 200 resets = <&ccu RST_BUS_MMC0>; 201 reset-names = "ahb"; 202 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 203 status = "disabled"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 }; 207 208 mmc1: mmc@1c10000 { 209 /* compatible and clocks are in per SoC .dtsi file */ 210 reg = <0x01c10000 0x1000>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&mmc1_pins>; 213 resets = <&ccu RST_BUS_MMC1>; 214 reset-names = "ahb"; 215 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 216 status = "disabled"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 }; 220 221 mmc2: mmc@1c11000 { 222 /* compatible and clocks are in per SoC .dtsi file */ 223 reg = <0x01c11000 0x1000>; 224 resets = <&ccu RST_BUS_MMC2>; 225 reset-names = "ahb"; 226 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 227 status = "disabled"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 sid: eeprom@1c14000 { 233 /* compatible is in per SoC .dtsi file */ 234 reg = <0x1c14000 0x400>; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 238 ths_calibration: thermal-sensor-calibration@34 { 239 reg = <0x34 4>; 240 }; 241 }; 242 243 msgbox: mailbox@1c17000 { 244 compatible = "allwinner,sun8i-h3-msgbox", 245 "allwinner,sun6i-a31-msgbox"; 246 reg = <0x01c17000 0x1000>; 247 clocks = <&ccu CLK_BUS_MSGBOX>; 248 resets = <&ccu RST_BUS_MSGBOX>; 249 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 250 #mbox-cells = <1>; 251 }; 252 253 usb_otg: usb@1c19000 { 254 compatible = "allwinner,sun8i-h3-musb"; 255 reg = <0x01c19000 0x400>; 256 clocks = <&ccu CLK_BUS_OTG>; 257 resets = <&ccu RST_BUS_OTG>; 258 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 259 interrupt-names = "mc"; 260 phys = <&usbphy 0>; 261 phy-names = "usb"; 262 extcon = <&usbphy 0>; 263 dr_mode = "otg"; 264 status = "disabled"; 265 }; 266 267 usbphy: phy@1c19400 { 268 compatible = "allwinner,sun8i-h3-usb-phy"; 269 reg = <0x01c19400 0x2c>, 270 <0x01c1a800 0x4>, 271 <0x01c1b800 0x4>, 272 <0x01c1c800 0x4>, 273 <0x01c1d800 0x4>; 274 reg-names = "phy_ctrl", 275 "pmu0", 276 "pmu1", 277 "pmu2", 278 "pmu3"; 279 clocks = <&ccu CLK_USB_PHY0>, 280 <&ccu CLK_USB_PHY1>, 281 <&ccu CLK_USB_PHY2>, 282 <&ccu CLK_USB_PHY3>; 283 clock-names = "usb0_phy", 284 "usb1_phy", 285 "usb2_phy", 286 "usb3_phy"; 287 resets = <&ccu RST_USB_PHY0>, 288 <&ccu RST_USB_PHY1>, 289 <&ccu RST_USB_PHY2>, 290 <&ccu RST_USB_PHY3>; 291 reset-names = "usb0_reset", 292 "usb1_reset", 293 "usb2_reset", 294 "usb3_reset"; 295 status = "disabled"; 296 #phy-cells = <1>; 297 }; 298 299 ehci0: usb@1c1a000 { 300 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 301 reg = <0x01c1a000 0x100>; 302 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; 304 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 305 phys = <&usbphy 0>; 306 phy-names = "usb"; 307 status = "disabled"; 308 }; 309 310 ohci0: usb@1c1a400 { 311 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 312 reg = <0x01c1a400 0x100>; 313 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, 315 <&ccu CLK_USB_OHCI0>; 316 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 317 phys = <&usbphy 0>; 318 phy-names = "usb"; 319 status = "disabled"; 320 }; 321 322 ehci1: usb@1c1b000 { 323 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 324 reg = <0x01c1b000 0x100>; 325 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; 327 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 328 phys = <&usbphy 1>; 329 phy-names = "usb"; 330 status = "disabled"; 331 }; 332 333 ohci1: usb@1c1b400 { 334 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 335 reg = <0x01c1b400 0x100>; 336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, 338 <&ccu CLK_USB_OHCI1>; 339 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 340 phys = <&usbphy 1>; 341 phy-names = "usb"; 342 status = "disabled"; 343 }; 344 345 ehci2: usb@1c1c000 { 346 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 347 reg = <0x01c1c000 0x100>; 348 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; 350 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 351 phys = <&usbphy 2>; 352 phy-names = "usb"; 353 status = "disabled"; 354 }; 355 356 ohci2: usb@1c1c400 { 357 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 358 reg = <0x01c1c400 0x100>; 359 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, 361 <&ccu CLK_USB_OHCI2>; 362 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 363 phys = <&usbphy 2>; 364 phy-names = "usb"; 365 status = "disabled"; 366 }; 367 368 ehci3: usb@1c1d000 { 369 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 370 reg = <0x01c1d000 0x100>; 371 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; 373 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 374 phys = <&usbphy 3>; 375 phy-names = "usb"; 376 status = "disabled"; 377 }; 378 379 ohci3: usb@1c1d400 { 380 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 381 reg = <0x01c1d400 0x100>; 382 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, 384 <&ccu CLK_USB_OHCI3>; 385 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 386 phys = <&usbphy 3>; 387 phy-names = "usb"; 388 status = "disabled"; 389 }; 390 391 ccu: clock@1c20000 { 392 /* compatible is in per SoC .dtsi file */ 393 reg = <0x01c20000 0x400>; 394 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 395 clock-names = "hosc", "losc"; 396 #clock-cells = <1>; 397 #reset-cells = <1>; 398 }; 399 400 pio: pinctrl@1c20800 { 401 /* compatible is in per SoC .dtsi file */ 402 reg = <0x01c20800 0x400>; 403 interrupt-parent = <&r_intc>; 404 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 407 <&rtc CLK_OSC32K>; 408 clock-names = "apb", "hosc", "losc"; 409 gpio-controller; 410 #gpio-cells = <3>; 411 interrupt-controller; 412 #interrupt-cells = <3>; 413 414 csi_pins: csi-pins { 415 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 416 "PE6", "PE7", "PE8", "PE9", "PE10", 417 "PE11"; 418 function = "csi"; 419 }; 420 421 emac_rgmii_pins: emac-rgmii-pins { 422 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 423 "PD5", "PD7", "PD8", "PD9", "PD10", 424 "PD12", "PD13", "PD15", "PD16", "PD17"; 425 function = "emac"; 426 drive-strength = <40>; 427 }; 428 429 i2c0_pins: i2c0-pins { 430 pins = "PA11", "PA12"; 431 function = "i2c0"; 432 }; 433 434 i2c1_pins: i2c1-pins { 435 pins = "PA18", "PA19"; 436 function = "i2c1"; 437 }; 438 439 i2c2_pins: i2c2-pins { 440 pins = "PE12", "PE13"; 441 function = "i2c2"; 442 }; 443 444 mmc0_pins: mmc0-pins { 445 pins = "PF0", "PF1", "PF2", "PF3", 446 "PF4", "PF5"; 447 function = "mmc0"; 448 drive-strength = <30>; 449 bias-pull-up; 450 }; 451 452 mmc1_pins: mmc1-pins { 453 pins = "PG0", "PG1", "PG2", "PG3", 454 "PG4", "PG5"; 455 function = "mmc1"; 456 drive-strength = <30>; 457 bias-pull-up; 458 }; 459 460 mmc2_8bit_pins: mmc2-8bit-pins { 461 pins = "PC5", "PC6", "PC8", 462 "PC9", "PC10", "PC11", 463 "PC12", "PC13", "PC14", 464 "PC15", "PC16"; 465 function = "mmc2"; 466 drive-strength = <30>; 467 bias-pull-up; 468 }; 469 470 spdif_tx_pin: spdif-tx-pin { 471 pins = "PA17"; 472 function = "spdif"; 473 }; 474 475 spi0_pins: spi0-pins { 476 pins = "PC0", "PC1", "PC2", "PC3"; 477 function = "spi0"; 478 }; 479 480 spi1_pins: spi1-pins { 481 pins = "PA15", "PA16", "PA14", "PA13"; 482 function = "spi1"; 483 }; 484 485 uart0_pa_pins: uart0-pa-pins { 486 pins = "PA4", "PA5"; 487 function = "uart0"; 488 }; 489 490 uart1_pins: uart1-pins { 491 pins = "PG6", "PG7"; 492 function = "uart1"; 493 }; 494 495 uart1_rts_cts_pins: uart1-rts-cts-pins { 496 pins = "PG8", "PG9"; 497 function = "uart1"; 498 }; 499 500 uart2_pins: uart2-pins { 501 pins = "PA0", "PA1"; 502 function = "uart2"; 503 }; 504 505 uart2_rts_cts_pins: uart2-rts-cts-pins { 506 pins = "PA2", "PA3"; 507 function = "uart2"; 508 }; 509 510 uart3_pins: uart3-pins { 511 pins = "PA13", "PA14"; 512 function = "uart3"; 513 }; 514 515 uart3_rts_cts_pins: uart3-rts-cts-pins { 516 pins = "PA15", "PA16"; 517 function = "uart3"; 518 }; 519 }; 520 521 timer@1c20c00 { 522 compatible = "allwinner,sun8i-a23-timer"; 523 reg = <0x01c20c00 0xa0>; 524 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&osc24M>; 527 }; 528 529 emac: ethernet@1c30000 { 530 compatible = "allwinner,sun8i-h3-emac"; 531 syscon = <&syscon>; 532 reg = <0x01c30000 0x10000>; 533 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 534 interrupt-names = "macirq"; 535 resets = <&ccu RST_BUS_EMAC>; 536 reset-names = "stmmaceth"; 537 clocks = <&ccu CLK_BUS_EMAC>; 538 clock-names = "stmmaceth"; 539 status = "disabled"; 540 541 mdio: mdio { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 compatible = "snps,dwmac-mdio"; 545 }; 546 547 mdio-mux { 548 compatible = "allwinner,sun8i-h3-mdio-mux"; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 552 mdio-parent-bus = <&mdio>; 553 /* Only one MDIO is usable at the time */ 554 internal_mdio: mdio@1 { 555 compatible = "allwinner,sun8i-h3-mdio-internal"; 556 reg = <1>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 560 int_mii_phy: ethernet-phy@1 { 561 compatible = "ethernet-phy-ieee802.3-c22"; 562 reg = <1>; 563 clocks = <&ccu CLK_BUS_EPHY>; 564 resets = <&ccu RST_BUS_EPHY>; 565 }; 566 }; 567 568 external_mdio: mdio@2 { 569 reg = <2>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 }; 573 }; 574 }; 575 576 mbus: dram-controller@1c62000 { 577 /* compatible is in per SoC .dtsi file */ 578 reg = <0x01c62000 0x1000>, 579 <0x01c63000 0x1000>; 580 reg-names = "mbus", "dram"; 581 clocks = <&ccu CLK_MBUS>, 582 <&ccu CLK_DRAM>, 583 <&ccu CLK_BUS_DRAM>; 584 clock-names = "mbus", "dram", "bus"; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 588 #interconnect-cells = <1>; 589 }; 590 591 spi0: spi@1c68000 { 592 compatible = "allwinner,sun8i-h3-spi"; 593 reg = <0x01c68000 0x1000>; 594 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 596 clock-names = "ahb", "mod"; 597 dmas = <&dma 23>, <&dma 23>; 598 dma-names = "rx", "tx"; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&spi0_pins>; 601 resets = <&ccu RST_BUS_SPI0>; 602 status = "disabled"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 }; 606 607 spi1: spi@1c69000 { 608 compatible = "allwinner,sun8i-h3-spi"; 609 reg = <0x01c69000 0x1000>; 610 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 612 clock-names = "ahb", "mod"; 613 dmas = <&dma 24>, <&dma 24>; 614 dma-names = "rx", "tx"; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&spi1_pins>; 617 resets = <&ccu RST_BUS_SPI1>; 618 status = "disabled"; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 }; 622 623 wdt0: watchdog@1c20ca0 { 624 compatible = "allwinner,sun6i-a31-wdt"; 625 reg = <0x01c20ca0 0x20>; 626 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&osc24M>; 628 }; 629 630 spdif: spdif@1c21000 { 631 #sound-dai-cells = <0>; 632 compatible = "allwinner,sun8i-h3-spdif"; 633 reg = <0x01c21000 0x400>; 634 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 636 resets = <&ccu RST_BUS_SPDIF>; 637 clock-names = "apb", "spdif"; 638 dmas = <&dma 2>; 639 dma-names = "tx"; 640 status = "disabled"; 641 }; 642 643 pwm: pwm@1c21400 { 644 compatible = "allwinner,sun8i-h3-pwm"; 645 reg = <0x01c21400 0x8>; 646 clocks = <&osc24M>; 647 #pwm-cells = <3>; 648 status = "disabled"; 649 }; 650 651 i2s0: i2s@1c22000 { 652 #sound-dai-cells = <0>; 653 compatible = "allwinner,sun8i-h3-i2s"; 654 reg = <0x01c22000 0x400>; 655 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 657 clock-names = "apb", "mod"; 658 dmas = <&dma 3>, <&dma 3>; 659 resets = <&ccu RST_BUS_I2S0>; 660 dma-names = "rx", "tx"; 661 status = "disabled"; 662 }; 663 664 i2s1: i2s@1c22400 { 665 #sound-dai-cells = <0>; 666 compatible = "allwinner,sun8i-h3-i2s"; 667 reg = <0x01c22400 0x400>; 668 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 670 clock-names = "apb", "mod"; 671 dmas = <&dma 4>, <&dma 4>; 672 resets = <&ccu RST_BUS_I2S1>; 673 dma-names = "rx", "tx"; 674 status = "disabled"; 675 }; 676 677 i2s2: i2s@1c22800 { 678 #sound-dai-cells = <0>; 679 compatible = "allwinner,sun8i-h3-i2s"; 680 reg = <0x01c22800 0x400>; 681 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 683 clock-names = "apb", "mod"; 684 dmas = <&dma 27>; 685 resets = <&ccu RST_BUS_I2S2>; 686 dma-names = "tx"; 687 status = "disabled"; 688 }; 689 690 codec: codec@1c22c00 { 691 #sound-dai-cells = <0>; 692 compatible = "allwinner,sun8i-h3-codec"; 693 reg = <0x01c22c00 0x400>; 694 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 696 clock-names = "apb", "codec"; 697 resets = <&ccu RST_BUS_CODEC>; 698 dmas = <&dma 15>, <&dma 15>; 699 dma-names = "rx", "tx"; 700 allwinner,codec-analog-controls = <&codec_analog>; 701 status = "disabled"; 702 }; 703 704 uart0: serial@1c28000 { 705 compatible = "snps,dw-apb-uart"; 706 reg = <0x01c28000 0x400>; 707 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 708 reg-shift = <2>; 709 reg-io-width = <4>; 710 clocks = <&ccu CLK_BUS_UART0>; 711 resets = <&ccu RST_BUS_UART0>; 712 dmas = <&dma 6>, <&dma 6>; 713 dma-names = "tx", "rx"; 714 status = "disabled"; 715 }; 716 717 uart1: serial@1c28400 { 718 compatible = "snps,dw-apb-uart"; 719 reg = <0x01c28400 0x400>; 720 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 721 reg-shift = <2>; 722 reg-io-width = <4>; 723 clocks = <&ccu CLK_BUS_UART1>; 724 resets = <&ccu RST_BUS_UART1>; 725 dmas = <&dma 7>, <&dma 7>; 726 dma-names = "tx", "rx"; 727 status = "disabled"; 728 }; 729 730 uart2: serial@1c28800 { 731 compatible = "snps,dw-apb-uart"; 732 reg = <0x01c28800 0x400>; 733 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 734 reg-shift = <2>; 735 reg-io-width = <4>; 736 clocks = <&ccu CLK_BUS_UART2>; 737 resets = <&ccu RST_BUS_UART2>; 738 dmas = <&dma 8>, <&dma 8>; 739 dma-names = "tx", "rx"; 740 status = "disabled"; 741 }; 742 743 uart3: serial@1c28c00 { 744 compatible = "snps,dw-apb-uart"; 745 reg = <0x01c28c00 0x400>; 746 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 747 reg-shift = <2>; 748 reg-io-width = <4>; 749 clocks = <&ccu CLK_BUS_UART3>; 750 resets = <&ccu RST_BUS_UART3>; 751 dmas = <&dma 9>, <&dma 9>; 752 dma-names = "tx", "rx"; 753 status = "disabled"; 754 }; 755 756 i2c0: i2c@1c2ac00 { 757 compatible = "allwinner,sun6i-a31-i2c"; 758 reg = <0x01c2ac00 0x400>; 759 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&ccu CLK_BUS_I2C0>; 761 resets = <&ccu RST_BUS_I2C0>; 762 pinctrl-names = "default"; 763 pinctrl-0 = <&i2c0_pins>; 764 status = "disabled"; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 }; 768 769 i2c1: i2c@1c2b000 { 770 compatible = "allwinner,sun6i-a31-i2c"; 771 reg = <0x01c2b000 0x400>; 772 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&ccu CLK_BUS_I2C1>; 774 resets = <&ccu RST_BUS_I2C1>; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&i2c1_pins>; 777 status = "disabled"; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 }; 781 782 i2c2: i2c@1c2b400 { 783 compatible = "allwinner,sun6i-a31-i2c"; 784 reg = <0x01c2b400 0x400>; 785 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_I2C2>; 787 resets = <&ccu RST_BUS_I2C2>; 788 pinctrl-names = "default"; 789 pinctrl-0 = <&i2c2_pins>; 790 status = "disabled"; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 }; 794 795 gic: interrupt-controller@1c81000 { 796 compatible = "arm,gic-400"; 797 reg = <0x01c81000 0x1000>, 798 <0x01c82000 0x2000>, 799 <0x01c84000 0x2000>, 800 <0x01c86000 0x2000>; 801 interrupt-controller; 802 #interrupt-cells = <3>; 803 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 804 }; 805 806 csi: camera@1cb0000 { 807 compatible = "allwinner,sun8i-h3-csi"; 808 reg = <0x01cb0000 0x1000>; 809 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&ccu CLK_BUS_CSI>, 811 <&ccu CLK_CSI_SCLK>, 812 <&ccu CLK_DRAM_CSI>; 813 clock-names = "bus", "mod", "ram"; 814 resets = <&ccu RST_BUS_CSI>; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&csi_pins>; 817 status = "disabled"; 818 }; 819 820 hdmi: hdmi@1ee0000 { 821 compatible = "allwinner,sun8i-h3-dw-hdmi", 822 "allwinner,sun8i-a83t-dw-hdmi"; 823 reg = <0x01ee0000 0x10000>; 824 reg-io-width = <1>; 825 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 827 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 828 clock-names = "iahb", "isfr", "tmds", "cec"; 829 resets = <&ccu RST_BUS_HDMI1>; 830 reset-names = "ctrl"; 831 phys = <&hdmi_phy>; 832 phy-names = "phy"; 833 status = "disabled"; 834 835 ports { 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 hdmi_in: port@0 { 840 reg = <0>; 841 842 hdmi_in_tcon0: endpoint { 843 remote-endpoint = <&tcon0_out_hdmi>; 844 }; 845 }; 846 847 hdmi_out: port@1 { 848 reg = <1>; 849 }; 850 }; 851 }; 852 853 hdmi_phy: hdmi-phy@1ef0000 { 854 compatible = "allwinner,sun8i-h3-hdmi-phy"; 855 reg = <0x01ef0000 0x10000>; 856 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 857 <&ccu CLK_PLL_VIDEO>; 858 clock-names = "bus", "mod", "pll-0"; 859 resets = <&ccu RST_BUS_HDMI0>; 860 reset-names = "phy"; 861 #phy-cells = <0>; 862 }; 863 864 rtc: rtc@1f00000 { 865 /* compatible is in per SoC .dtsi file */ 866 reg = <0x01f00000 0x400>; 867 interrupt-parent = <&r_intc>; 868 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 870 clock-output-names = "osc32k", "osc32k-out", "iosc"; 871 clocks = <&osc32k>; 872 #clock-cells = <1>; 873 }; 874 875 r_intc: interrupt-controller@1f00c00 { 876 compatible = "allwinner,sun8i-h3-r-intc", 877 "allwinner,sun6i-a31-r-intc"; 878 interrupt-controller; 879 #interrupt-cells = <3>; 880 reg = <0x01f00c00 0x400>; 881 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 882 }; 883 884 r_ccu: clock@1f01400 { 885 compatible = "allwinner,sun8i-h3-r-ccu"; 886 reg = <0x01f01400 0x100>; 887 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 888 <&ccu CLK_PLL_PERIPH0>; 889 clock-names = "hosc", "losc", "iosc", "pll-periph"; 890 #clock-cells = <1>; 891 #reset-cells = <1>; 892 }; 893 894 codec_analog: codec-analog@1f015c0 { 895 compatible = "allwinner,sun8i-h3-codec-analog"; 896 reg = <0x01f015c0 0x4>; 897 }; 898 899 ir: ir@1f02000 { 900 compatible = "allwinner,sun6i-a31-ir"; 901 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 902 clock-names = "apb", "ir"; 903 resets = <&r_ccu RST_APB0_IR>; 904 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 905 reg = <0x01f02000 0x400>; 906 status = "disabled"; 907 }; 908 909 r_i2c: i2c@1f02400 { 910 compatible = "allwinner,sun6i-a31-i2c"; 911 reg = <0x01f02400 0x400>; 912 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&r_i2c_pins>; 915 clocks = <&r_ccu CLK_APB0_I2C>; 916 resets = <&r_ccu RST_APB0_I2C>; 917 status = "disabled"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 }; 921 922 r_uart: serial@1f02800 { 923 compatible = "snps,dw-apb-uart"; 924 reg = <0x01f02800 0x400>; 925 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 926 reg-shift = <2>; 927 reg-io-width = <4>; 928 clocks = <&r_ccu CLK_APB0_UART>; 929 resets = <&r_ccu RST_APB0_UART>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&r_uart_pins>; 932 status = "disabled"; 933 }; 934 935 r_pio: pinctrl@1f02c00 { 936 compatible = "allwinner,sun8i-h3-r-pinctrl"; 937 reg = <0x01f02c00 0x400>; 938 interrupt-parent = <&r_intc>; 939 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 941 <&rtc CLK_OSC32K>; 942 clock-names = "apb", "hosc", "losc"; 943 gpio-controller; 944 #gpio-cells = <3>; 945 interrupt-controller; 946 #interrupt-cells = <3>; 947 948 r_ir_rx_pin: r-ir-rx-pin { 949 pins = "PL11"; 950 function = "s_cir_rx"; 951 }; 952 953 r_i2c_pins: r-i2c-pins { 954 pins = "PL0", "PL1"; 955 function = "s_i2c"; 956 }; 957 958 r_pwm_pin: r-pwm-pin { 959 pins = "PL10"; 960 function = "s_pwm"; 961 }; 962 963 r_uart_pins: r-uart-pins { 964 pins = "PL2", "PL3"; 965 function = "s_uart"; 966 }; 967 }; 968 969 r_pwm: pwm@1f03800 { 970 compatible = "allwinner,sun8i-h3-pwm"; 971 reg = <0x01f03800 0x8>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&r_pwm_pin>; 974 clocks = <&osc24M>; 975 #pwm-cells = <3>; 976 status = "disabled"; 977 }; 978 }; 979}; 980