1/* 2 * Copyright 2012 Stefan Roese 3 * Stefan Roese <sr@denx.de> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This library is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/thermal/thermal.h> 45#include <dt-bindings/dma/sun4i-a10.h> 46#include <dt-bindings/clock/sun4i-a10-ccu.h> 47#include <dt-bindings/reset/sun4i-a10-ccu.h> 48 49/ { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 interrupt-parent = <&intc>; 53 54 aliases { 55 ethernet0 = &emac; 56 }; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 framebuffer-lcd0-hdmi { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "de_be0-lcd0-hdmi"; 67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, 68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; 70 status = "disabled"; 71 }; 72 73 framebuffer-fe0-lcd0-hdmi { 74 compatible = "allwinner,simple-framebuffer", 75 "simple-framebuffer"; 76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; 77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, 78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, 79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, 80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, 81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; 82 status = "disabled"; 83 }; 84 85 framebuffer-fe0-lcd0 { 86 compatible = "allwinner,simple-framebuffer", 87 "simple-framebuffer"; 88 allwinner,pipeline = "de_fe0-de_be0-lcd0"; 89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, 90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, 91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, 92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; 93 status = "disabled"; 94 }; 95 96 framebuffer-fe0-lcd0-tve0 { 97 compatible = "allwinner,simple-framebuffer", 98 "simple-framebuffer"; 99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; 100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, 101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, 102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, 103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, 104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; 105 status = "disabled"; 106 }; 107 }; 108 109 cpus { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 cpu0: cpu@0 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a8"; 115 reg = <0x0>; 116 clocks = <&ccu CLK_CPU>; 117 clock-latency = <244144>; /* 8 32k periods */ 118 operating-points = 119 /* kHz uV */ 120 <1008000 1400000>, 121 <912000 1350000>, 122 <864000 1300000>, 123 <624000 1250000>; 124 #cooling-cells = <2>; 125 }; 126 }; 127 128 thermal-zones { 129 cpu-thermal { 130 /* milliseconds */ 131 polling-delay-passive = <250>; 132 polling-delay = <1000>; 133 thermal-sensors = <&rtp>; 134 135 cooling-maps { 136 map0 { 137 trip = <&cpu_alert0>; 138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 139 }; 140 }; 141 142 trips { 143 cpu_alert0: cpu-alert0 { 144 /* milliCelsius */ 145 temperature = <85000>; 146 hysteresis = <2000>; 147 type = "passive"; 148 }; 149 150 cpu_crit: cpu-crit { 151 /* milliCelsius */ 152 temperature = <100000>; 153 hysteresis = <2000>; 154 type = "critical"; 155 }; 156 }; 157 }; 158 }; 159 160 clocks { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges; 164 165 osc24M: clk-24M { 166 #clock-cells = <0>; 167 compatible = "fixed-clock"; 168 clock-frequency = <24000000>; 169 clock-output-names = "osc24M"; 170 }; 171 172 osc32k: clk-32k { 173 #clock-cells = <0>; 174 compatible = "fixed-clock"; 175 clock-frequency = <32768>; 176 clock-output-names = "osc32k"; 177 }; 178 }; 179 180 de: display-engine { 181 compatible = "allwinner,sun4i-a10-display-engine"; 182 allwinner,pipelines = <&fe0>, <&fe1>; 183 status = "disabled"; 184 }; 185 186 pmu { 187 compatible = "arm,cortex-a8-pmu"; 188 interrupts = <3>; 189 }; 190 191 reserved-memory { 192 #address-cells = <1>; 193 #size-cells = <1>; 194 ranges; 195 196 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ 197 default-pool { 198 compatible = "shared-dma-pool"; 199 size = <0x6000000>; 200 alloc-ranges = <0x40000000 0x10000000>; 201 reusable; 202 linux,cma-default; 203 }; 204 }; 205 206 soc { 207 compatible = "simple-bus"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 system-control@1c00000 { 213 compatible = "allwinner,sun4i-a10-system-control"; 214 reg = <0x01c00000 0x30>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 sram_a: sram@0 { 220 compatible = "mmio-sram"; 221 reg = <0x00000000 0xc000>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x00000000 0xc000>; 225 226 emac_sram: sram-section@8000 { 227 compatible = "allwinner,sun4i-a10-sram-a3-a4"; 228 reg = <0x8000 0x4000>; 229 status = "disabled"; 230 }; 231 }; 232 233 sram_d: sram@10000 { 234 compatible = "mmio-sram"; 235 reg = <0x00010000 0x1000>; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 ranges = <0 0x00010000 0x1000>; 239 240 otg_sram: sram-section@0 { 241 compatible = "allwinner,sun4i-a10-sram-d"; 242 reg = <0x0000 0x1000>; 243 status = "disabled"; 244 }; 245 }; 246 247 sram_c: sram@1d00000 { 248 compatible = "mmio-sram"; 249 reg = <0x01d00000 0xd0000>; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 ranges = <0 0x01d00000 0xd0000>; 253 254 ve_sram: sram-section@0 { 255 compatible = "allwinner,sun4i-a10-sram-c1"; 256 reg = <0x000000 0x80000>; 257 }; 258 }; 259 }; 260 261 dma: dma-controller@1c02000 { 262 compatible = "allwinner,sun4i-a10-dma"; 263 reg = <0x01c02000 0x1000>; 264 interrupts = <27>; 265 clocks = <&ccu CLK_AHB_DMA>; 266 #dma-cells = <2>; 267 }; 268 269 nfc: nand-controller@1c03000 { 270 compatible = "allwinner,sun4i-a10-nand"; 271 reg = <0x01c03000 0x1000>; 272 interrupts = <37>; 273 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; 274 clock-names = "ahb", "mod"; 275 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 276 dma-names = "rxtx"; 277 status = "disabled"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 }; 281 282 spi0: spi@1c05000 { 283 compatible = "allwinner,sun4i-a10-spi"; 284 reg = <0x01c05000 0x1000>; 285 interrupts = <10>; 286 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; 287 clock-names = "ahb", "mod"; 288 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 289 <&dma SUN4I_DMA_DEDICATED 26>; 290 dma-names = "rx", "tx"; 291 status = "disabled"; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 }; 295 296 spi1: spi@1c06000 { 297 compatible = "allwinner,sun4i-a10-spi"; 298 reg = <0x01c06000 0x1000>; 299 interrupts = <11>; 300 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; 301 clock-names = "ahb", "mod"; 302 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 303 <&dma SUN4I_DMA_DEDICATED 8>; 304 dma-names = "rx", "tx"; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; 307 status = "disabled"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 }; 311 312 emac: ethernet@1c0b000 { 313 compatible = "allwinner,sun4i-a10-emac"; 314 reg = <0x01c0b000 0x1000>; 315 interrupts = <55>; 316 clocks = <&ccu CLK_AHB_EMAC>; 317 allwinner,sram = <&emac_sram 1>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&emac_pins>; 320 status = "disabled"; 321 }; 322 323 mdio: mdio@1c0b080 { 324 compatible = "allwinner,sun4i-a10-mdio"; 325 reg = <0x01c0b080 0x14>; 326 status = "disabled"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 }; 330 331 tcon0: lcd-controller@1c0c000 { 332 compatible = "allwinner,sun4i-a10-tcon"; 333 reg = <0x01c0c000 0x1000>; 334 interrupts = <44>; 335 resets = <&ccu RST_TCON0>; 336 reset-names = "lcd"; 337 clocks = <&ccu CLK_AHB_LCD0>, 338 <&ccu CLK_TCON0_CH0>, 339 <&ccu CLK_TCON0_CH1>; 340 clock-names = "ahb", 341 "tcon-ch0", 342 "tcon-ch1"; 343 clock-output-names = "tcon0-pixel-clock"; 344 #clock-cells = <0>; 345 dmas = <&dma SUN4I_DMA_DEDICATED 14>; 346 347 ports { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 tcon0_in: port@0 { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 reg = <0>; 355 356 tcon0_in_be0: endpoint@0 { 357 reg = <0>; 358 remote-endpoint = <&be0_out_tcon0>; 359 }; 360 361 tcon0_in_be1: endpoint@1 { 362 reg = <1>; 363 remote-endpoint = <&be1_out_tcon0>; 364 }; 365 }; 366 367 tcon0_out: port@1 { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <1>; 371 372 tcon0_out_hdmi: endpoint@1 { 373 reg = <1>; 374 remote-endpoint = <&hdmi_in_tcon0>; 375 allwinner,tcon-channel = <1>; 376 }; 377 }; 378 }; 379 }; 380 381 tcon1: lcd-controller@1c0d000 { 382 compatible = "allwinner,sun4i-a10-tcon"; 383 reg = <0x01c0d000 0x1000>; 384 interrupts = <45>; 385 resets = <&ccu RST_TCON1>; 386 reset-names = "lcd"; 387 clocks = <&ccu CLK_AHB_LCD1>, 388 <&ccu CLK_TCON1_CH0>, 389 <&ccu CLK_TCON1_CH1>; 390 clock-names = "ahb", 391 "tcon-ch0", 392 "tcon-ch1"; 393 clock-output-names = "tcon1-pixel-clock"; 394 #clock-cells = <0>; 395 dmas = <&dma SUN4I_DMA_DEDICATED 15>; 396 397 ports { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 401 tcon1_in: port@0 { 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0>; 405 406 tcon1_in_be0: endpoint@0 { 407 reg = <0>; 408 remote-endpoint = <&be0_out_tcon1>; 409 }; 410 411 tcon1_in_be1: endpoint@1 { 412 reg = <1>; 413 remote-endpoint = <&be1_out_tcon1>; 414 }; 415 }; 416 417 tcon1_out: port@1 { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 reg = <1>; 421 422 tcon1_out_hdmi: endpoint@1 { 423 reg = <1>; 424 remote-endpoint = <&hdmi_in_tcon1>; 425 allwinner,tcon-channel = <1>; 426 }; 427 }; 428 }; 429 }; 430 431 video-codec@1c0e000 { 432 compatible = "allwinner,sun4i-a10-video-engine"; 433 reg = <0x01c0e000 0x1000>; 434 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, 435 <&ccu CLK_DRAM_VE>; 436 clock-names = "ahb", "mod", "ram"; 437 resets = <&ccu RST_VE>; 438 interrupts = <53>; 439 allwinner,sram = <&ve_sram 1>; 440 }; 441 442 mmc0: mmc@1c0f000 { 443 compatible = "allwinner,sun4i-a10-mmc"; 444 reg = <0x01c0f000 0x1000>; 445 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; 446 clock-names = "ahb", "mmc"; 447 interrupts = <32>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&mmc0_pins>; 450 status = "disabled"; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 }; 454 455 mmc1: mmc@1c10000 { 456 compatible = "allwinner,sun4i-a10-mmc"; 457 reg = <0x01c10000 0x1000>; 458 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; 459 clock-names = "ahb", "mmc"; 460 interrupts = <33>; 461 status = "disabled"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 }; 465 466 mmc2: mmc@1c11000 { 467 compatible = "allwinner,sun4i-a10-mmc"; 468 reg = <0x01c11000 0x1000>; 469 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; 470 clock-names = "ahb", "mmc"; 471 interrupts = <34>; 472 status = "disabled"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 }; 476 477 mmc3: mmc@1c12000 { 478 compatible = "allwinner,sun4i-a10-mmc"; 479 reg = <0x01c12000 0x1000>; 480 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; 481 clock-names = "ahb", "mmc"; 482 interrupts = <35>; 483 status = "disabled"; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 }; 487 488 usb_otg: usb@1c13000 { 489 compatible = "allwinner,sun4i-a10-musb"; 490 reg = <0x01c13000 0x0400>; 491 clocks = <&ccu CLK_AHB_OTG>; 492 interrupts = <38>; 493 interrupt-names = "mc"; 494 phys = <&usbphy 0>; 495 phy-names = "usb"; 496 extcon = <&usbphy 0>; 497 allwinner,sram = <&otg_sram 1>; 498 dr_mode = "otg"; 499 status = "disabled"; 500 }; 501 502 usbphy: phy@1c13400 { 503 #phy-cells = <1>; 504 compatible = "allwinner,sun4i-a10-usb-phy"; 505 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; 506 reg-names = "phy_ctrl", "pmu1", "pmu2"; 507 clocks = <&ccu CLK_USB_PHY>; 508 clock-names = "usb_phy"; 509 resets = <&ccu RST_USB_PHY0>, 510 <&ccu RST_USB_PHY1>, 511 <&ccu RST_USB_PHY2>; 512 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 513 status = "disabled"; 514 }; 515 516 ehci0: usb@1c14000 { 517 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 518 reg = <0x01c14000 0x100>; 519 interrupts = <39>; 520 clocks = <&ccu CLK_AHB_EHCI0>; 521 phys = <&usbphy 1>; 522 phy-names = "usb"; 523 status = "disabled"; 524 }; 525 526 ohci0: usb@1c14400 { 527 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 528 reg = <0x01c14400 0x100>; 529 interrupts = <64>; 530 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; 531 phys = <&usbphy 1>; 532 phy-names = "usb"; 533 status = "disabled"; 534 }; 535 536 crypto: crypto-engine@1c15000 { 537 compatible = "allwinner,sun4i-a10-crypto"; 538 reg = <0x01c15000 0x1000>; 539 interrupts = <86>; 540 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; 541 clock-names = "ahb", "mod"; 542 }; 543 544 hdmi: hdmi@1c16000 { 545 compatible = "allwinner,sun4i-a10-hdmi"; 546 reg = <0x01c16000 0x1000>; 547 interrupts = <58>; 548 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, 549 <&ccu CLK_PLL_VIDEO0_2X>, 550 <&ccu CLK_PLL_VIDEO1_2X>; 551 clock-names = "ahb", "mod", "pll-0", "pll-1"; 552 dmas = <&dma SUN4I_DMA_NORMAL 16>, 553 <&dma SUN4I_DMA_NORMAL 16>, 554 <&dma SUN4I_DMA_DEDICATED 24>; 555 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 556 status = "disabled"; 557 558 ports { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 562 hdmi_in: port@0 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 reg = <0>; 566 567 hdmi_in_tcon0: endpoint@0 { 568 reg = <0>; 569 remote-endpoint = <&tcon0_out_hdmi>; 570 }; 571 572 hdmi_in_tcon1: endpoint@1 { 573 reg = <1>; 574 remote-endpoint = <&tcon1_out_hdmi>; 575 }; 576 }; 577 578 hdmi_out: port@1 { 579 reg = <1>; 580 }; 581 }; 582 }; 583 584 spi2: spi@1c17000 { 585 compatible = "allwinner,sun4i-a10-spi"; 586 reg = <0x01c17000 0x1000>; 587 interrupts = <12>; 588 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; 589 clock-names = "ahb", "mod"; 590 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 591 <&dma SUN4I_DMA_DEDICATED 28>; 592 dma-names = "rx", "tx"; 593 status = "disabled"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 }; 597 598 ahci: sata@1c18000 { 599 compatible = "allwinner,sun4i-a10-ahci"; 600 reg = <0x01c18000 0x1000>; 601 interrupts = <56>; 602 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; 603 status = "disabled"; 604 }; 605 606 ehci1: usb@1c1c000 { 607 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 608 reg = <0x01c1c000 0x100>; 609 interrupts = <40>; 610 clocks = <&ccu CLK_AHB_EHCI1>; 611 phys = <&usbphy 2>; 612 phy-names = "usb"; 613 status = "disabled"; 614 }; 615 616 ohci1: usb@1c1c400 { 617 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 618 reg = <0x01c1c400 0x100>; 619 interrupts = <65>; 620 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; 621 phys = <&usbphy 2>; 622 phy-names = "usb"; 623 status = "disabled"; 624 }; 625 626 csi1: csi@1c1d000 { 627 compatible = "allwinner,sun4i-a10-csi1"; 628 reg = <0x01c1d000 0x1000>; 629 interrupts = <43>; 630 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; 631 clock-names = "bus", "ram"; 632 resets = <&ccu RST_CSI1>; 633 status = "disabled"; 634 }; 635 636 spi3: spi@1c1f000 { 637 compatible = "allwinner,sun4i-a10-spi"; 638 reg = <0x01c1f000 0x1000>; 639 interrupts = <50>; 640 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; 641 clock-names = "ahb", "mod"; 642 dmas = <&dma SUN4I_DMA_DEDICATED 31>, 643 <&dma SUN4I_DMA_DEDICATED 30>; 644 dma-names = "rx", "tx"; 645 status = "disabled"; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 }; 649 650 ccu: clock@1c20000 { 651 compatible = "allwinner,sun4i-a10-ccu"; 652 reg = <0x01c20000 0x400>; 653 clocks = <&osc24M>, <&osc32k>; 654 clock-names = "hosc", "losc"; 655 #clock-cells = <1>; 656 #reset-cells = <1>; 657 }; 658 659 intc: interrupt-controller@1c20400 { 660 compatible = "allwinner,sun4i-a10-ic"; 661 reg = <0x01c20400 0x400>; 662 interrupt-controller; 663 #interrupt-cells = <1>; 664 }; 665 666 pio: pinctrl@1c20800 { 667 compatible = "allwinner,sun4i-a10-pinctrl"; 668 reg = <0x01c20800 0x400>; 669 interrupts = <28>; 670 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 671 clock-names = "apb", "hosc", "losc"; 672 gpio-controller; 673 interrupt-controller; 674 #interrupt-cells = <3>; 675 #gpio-cells = <3>; 676 677 can0_ph_pins: can0-ph-pins { 678 pins = "PH20", "PH21"; 679 function = "can"; 680 }; 681 682 /omit-if-no-ref/ 683 csi1_8bits_pg_pins: csi1-8bits-pg-pins { 684 pins = "PG0", "PG2", "PG3", "PG4", "PG5", 685 "PG6", "PG7", "PG8", "PG9", "PG10", 686 "PG11"; 687 function = "csi1"; 688 }; 689 690 /omit-if-no-ref/ 691 csi1_24bits_ph_pins: csi1-24bits-ph-pins { 692 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 693 "PH5", "PH6", "PH7", "PH8", "PH9", 694 "PH10", "PH11", "PH12", "PH13", "PH14", 695 "PH15", "PH16", "PH17", "PH18", "PH19", 696 "PH20", "PH21", "PH22", "PH23", "PH24", 697 "PH25", "PH26", "PH27"; 698 function = "csi1"; 699 }; 700 701 /omit-if-no-ref/ 702 csi1_clk_pg_pin: csi1-clk-pg-pin { 703 pins = "PG1"; 704 function = "csi1"; 705 }; 706 707 emac_pins: emac0-pins { 708 pins = "PA0", "PA1", "PA2", 709 "PA3", "PA4", "PA5", "PA6", 710 "PA7", "PA8", "PA9", "PA10", 711 "PA11", "PA12", "PA13", "PA14", 712 "PA15", "PA16"; 713 function = "emac"; 714 }; 715 716 i2c0_pins: i2c0-pins { 717 pins = "PB0", "PB1"; 718 function = "i2c0"; 719 }; 720 721 i2c1_pins: i2c1-pins { 722 pins = "PB18", "PB19"; 723 function = "i2c1"; 724 }; 725 726 i2c2_pins: i2c2-pins { 727 pins = "PB20", "PB21"; 728 function = "i2c2"; 729 }; 730 731 ir0_rx_pins: ir0-rx-pin { 732 pins = "PB4"; 733 function = "ir0"; 734 }; 735 736 ir0_tx_pins: ir0-tx-pin { 737 pins = "PB3"; 738 function = "ir0"; 739 }; 740 741 ir1_rx_pins: ir1-rx-pin { 742 pins = "PB23"; 743 function = "ir1"; 744 }; 745 746 ir1_tx_pins: ir1-tx-pin { 747 pins = "PB22"; 748 function = "ir1"; 749 }; 750 751 mmc0_pins: mmc0-pins { 752 pins = "PF0", "PF1", "PF2", 753 "PF3", "PF4", "PF5"; 754 function = "mmc0"; 755 drive-strength = <30>; 756 bias-pull-up; 757 }; 758 759 ps2_ch0_pins: ps2-ch0-pins { 760 pins = "PI20", "PI21"; 761 function = "ps2"; 762 }; 763 764 ps2_ch1_ph_pins: ps2-ch1-ph-pins { 765 pins = "PH12", "PH13"; 766 function = "ps2"; 767 }; 768 769 pwm0_pin: pwm0-pin { 770 pins = "PB2"; 771 function = "pwm"; 772 }; 773 774 pwm1_pin: pwm1-pin { 775 pins = "PI3"; 776 function = "pwm"; 777 }; 778 779 spdif_tx_pin: spdif-tx-pin { 780 pins = "PB13"; 781 function = "spdif"; 782 bias-pull-up; 783 }; 784 785 spi0_pi_pins: spi0-pi-pins { 786 pins = "PI11", "PI12", "PI13"; 787 function = "spi0"; 788 }; 789 790 spi0_cs0_pi_pin: spi0-cs0-pi-pin { 791 pins = "PI10"; 792 function = "spi0"; 793 }; 794 795 spi1_pins: spi1-pins { 796 pins = "PI17", "PI18", "PI19"; 797 function = "spi1"; 798 }; 799 800 spi1_cs0_pin: spi1-cs0-pin { 801 pins = "PI16"; 802 function = "spi1"; 803 }; 804 805 spi2_pb_pins: spi2-pb-pins { 806 pins = "PB15", "PB16", "PB17"; 807 function = "spi2"; 808 }; 809 810 spi2_pc_pins: spi2-pc-pins { 811 pins = "PC20", "PC21", "PC22"; 812 function = "spi2"; 813 }; 814 815 spi2_cs0_pb_pin: spi2-cs0-pb-pin { 816 pins = "PB14"; 817 function = "spi2"; 818 }; 819 820 spi2_cs0_pc_pins: spi2-cs0-pc-pin { 821 pins = "PC19"; 822 function = "spi2"; 823 }; 824 825 uart0_pb_pins: uart0-pb-pins { 826 pins = "PB22", "PB23"; 827 function = "uart0"; 828 }; 829 830 uart0_pf_pins: uart0-pf-pins { 831 pins = "PF2", "PF4"; 832 function = "uart0"; 833 }; 834 835 uart1_pins: uart1-pins { 836 pins = "PA10", "PA11"; 837 function = "uart1"; 838 }; 839 }; 840 841 timer@1c20c00 { 842 compatible = "allwinner,sun4i-a10-timer"; 843 reg = <0x01c20c00 0x90>; 844 interrupts = <22>, 845 <23>, 846 <24>, 847 <25>, 848 <67>, 849 <68>; 850 clocks = <&osc24M>; 851 }; 852 853 wdt: watchdog@1c20c90 { 854 compatible = "allwinner,sun4i-a10-wdt"; 855 reg = <0x01c20c90 0x10>; 856 interrupts = <24>; 857 clocks = <&osc24M>; 858 }; 859 860 rtc: rtc@1c20d00 { 861 compatible = "allwinner,sun4i-a10-rtc"; 862 reg = <0x01c20d00 0x20>; 863 interrupts = <24>; 864 }; 865 866 pwm: pwm@1c20e00 { 867 compatible = "allwinner,sun4i-a10-pwm"; 868 reg = <0x01c20e00 0xc>; 869 clocks = <&osc24M>; 870 #pwm-cells = <3>; 871 status = "disabled"; 872 }; 873 874 spdif: spdif@1c21000 { 875 #sound-dai-cells = <0>; 876 compatible = "allwinner,sun4i-a10-spdif"; 877 reg = <0x01c21000 0x400>; 878 interrupts = <13>; 879 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; 880 clock-names = "apb", "spdif"; 881 dmas = <&dma SUN4I_DMA_NORMAL 2>, 882 <&dma SUN4I_DMA_NORMAL 2>; 883 dma-names = "rx", "tx"; 884 status = "disabled"; 885 }; 886 887 ir0: ir@1c21800 { 888 compatible = "allwinner,sun4i-a10-ir"; 889 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; 890 clock-names = "apb", "ir"; 891 interrupts = <5>; 892 reg = <0x01c21800 0x40>; 893 status = "disabled"; 894 }; 895 896 ir1: ir@1c21c00 { 897 compatible = "allwinner,sun4i-a10-ir"; 898 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; 899 clock-names = "apb", "ir"; 900 interrupts = <6>; 901 reg = <0x01c21c00 0x40>; 902 status = "disabled"; 903 }; 904 905 i2s0: i2s@1c22400 { 906 #sound-dai-cells = <0>; 907 compatible = "allwinner,sun4i-a10-i2s"; 908 reg = <0x01c22400 0x400>; 909 interrupts = <16>; 910 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; 911 clock-names = "apb", "mod"; 912 dmas = <&dma SUN4I_DMA_NORMAL 3>, 913 <&dma SUN4I_DMA_NORMAL 3>; 914 dma-names = "rx", "tx"; 915 status = "disabled"; 916 }; 917 918 lradc: lradc@1c22800 { 919 compatible = "allwinner,sun4i-a10-lradc-keys"; 920 reg = <0x01c22800 0x100>; 921 interrupts = <31>; 922 status = "disabled"; 923 }; 924 925 codec: codec@1c22c00 { 926 #sound-dai-cells = <0>; 927 compatible = "allwinner,sun4i-a10-codec"; 928 reg = <0x01c22c00 0x40>; 929 interrupts = <30>; 930 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; 931 clock-names = "apb", "codec"; 932 dmas = <&dma SUN4I_DMA_NORMAL 19>, 933 <&dma SUN4I_DMA_NORMAL 19>; 934 dma-names = "rx", "tx"; 935 status = "disabled"; 936 }; 937 938 sid: eeprom@1c23800 { 939 compatible = "allwinner,sun4i-a10-sid"; 940 reg = <0x01c23800 0x10>; 941 }; 942 943 rtp: rtp@1c25000 { 944 compatible = "allwinner,sun4i-a10-ts"; 945 reg = <0x01c25000 0x100>; 946 interrupts = <29>; 947 #thermal-sensor-cells = <0>; 948 }; 949 950 uart0: serial@1c28000 { 951 compatible = "snps,dw-apb-uart"; 952 reg = <0x01c28000 0x400>; 953 interrupts = <1>; 954 reg-shift = <2>; 955 reg-io-width = <4>; 956 clocks = <&ccu CLK_APB1_UART0>; 957 status = "disabled"; 958 }; 959 960 uart1: serial@1c28400 { 961 compatible = "snps,dw-apb-uart"; 962 reg = <0x01c28400 0x400>; 963 interrupts = <2>; 964 reg-shift = <2>; 965 reg-io-width = <4>; 966 clocks = <&ccu CLK_APB1_UART1>; 967 status = "disabled"; 968 }; 969 970 uart2: serial@1c28800 { 971 compatible = "snps,dw-apb-uart"; 972 reg = <0x01c28800 0x400>; 973 interrupts = <3>; 974 reg-shift = <2>; 975 reg-io-width = <4>; 976 clocks = <&ccu CLK_APB1_UART2>; 977 status = "disabled"; 978 }; 979 980 uart3: serial@1c28c00 { 981 compatible = "snps,dw-apb-uart"; 982 reg = <0x01c28c00 0x400>; 983 interrupts = <4>; 984 reg-shift = <2>; 985 reg-io-width = <4>; 986 clocks = <&ccu CLK_APB1_UART3>; 987 status = "disabled"; 988 }; 989 990 uart4: serial@1c29000 { 991 compatible = "snps,dw-apb-uart"; 992 reg = <0x01c29000 0x400>; 993 interrupts = <17>; 994 reg-shift = <2>; 995 reg-io-width = <4>; 996 clocks = <&ccu CLK_APB1_UART4>; 997 status = "disabled"; 998 }; 999 1000 uart5: serial@1c29400 { 1001 compatible = "snps,dw-apb-uart"; 1002 reg = <0x01c29400 0x400>; 1003 interrupts = <18>; 1004 reg-shift = <2>; 1005 reg-io-width = <4>; 1006 clocks = <&ccu CLK_APB1_UART5>; 1007 status = "disabled"; 1008 }; 1009 1010 uart6: serial@1c29800 { 1011 compatible = "snps,dw-apb-uart"; 1012 reg = <0x01c29800 0x400>; 1013 interrupts = <19>; 1014 reg-shift = <2>; 1015 reg-io-width = <4>; 1016 clocks = <&ccu CLK_APB1_UART6>; 1017 status = "disabled"; 1018 }; 1019 1020 uart7: serial@1c29c00 { 1021 compatible = "snps,dw-apb-uart"; 1022 reg = <0x01c29c00 0x400>; 1023 interrupts = <20>; 1024 reg-shift = <2>; 1025 reg-io-width = <4>; 1026 clocks = <&ccu CLK_APB1_UART7>; 1027 status = "disabled"; 1028 }; 1029 1030 ps20: ps2@1c2a000 { 1031 compatible = "allwinner,sun4i-a10-ps2"; 1032 reg = <0x01c2a000 0x400>; 1033 interrupts = <62>; 1034 clocks = <&ccu CLK_APB1_PS20>; 1035 status = "disabled"; 1036 }; 1037 1038 ps21: ps2@1c2a400 { 1039 compatible = "allwinner,sun4i-a10-ps2"; 1040 reg = <0x01c2a400 0x400>; 1041 interrupts = <63>; 1042 clocks = <&ccu CLK_APB1_PS21>; 1043 status = "disabled"; 1044 }; 1045 1046 i2c0: i2c@1c2ac00 { 1047 compatible = "allwinner,sun4i-a10-i2c"; 1048 reg = <0x01c2ac00 0x400>; 1049 interrupts = <7>; 1050 clocks = <&ccu CLK_APB1_I2C0>; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&i2c0_pins>; 1053 status = "disabled"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 }; 1057 1058 i2c1: i2c@1c2b000 { 1059 compatible = "allwinner,sun4i-a10-i2c"; 1060 reg = <0x01c2b000 0x400>; 1061 interrupts = <8>; 1062 clocks = <&ccu CLK_APB1_I2C1>; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&i2c1_pins>; 1065 status = "disabled"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 }; 1069 1070 i2c2: i2c@1c2b400 { 1071 compatible = "allwinner,sun4i-a10-i2c"; 1072 reg = <0x01c2b400 0x400>; 1073 interrupts = <9>; 1074 clocks = <&ccu CLK_APB1_I2C2>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&i2c2_pins>; 1077 status = "disabled"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 }; 1081 1082 can0: can@1c2bc00 { 1083 compatible = "allwinner,sun4i-a10-can"; 1084 reg = <0x01c2bc00 0x400>; 1085 interrupts = <26>; 1086 clocks = <&ccu CLK_APB1_CAN>; 1087 status = "disabled"; 1088 }; 1089 1090 mali: gpu@1c40000 { 1091 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; 1092 reg = <0x01c40000 0x10000>; 1093 interrupts = <69>, 1094 <70>, 1095 <71>, 1096 <72>, 1097 <73>; 1098 interrupt-names = "gp", 1099 "gpmmu", 1100 "pp0", 1101 "ppmmu0", 1102 "pmu"; 1103 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; 1104 clock-names = "bus", "core"; 1105 resets = <&ccu RST_GPU>; 1106 1107 assigned-clocks = <&ccu CLK_GPU>; 1108 assigned-clock-rates = <384000000>; 1109 }; 1110 1111 fe0: display-frontend@1e00000 { 1112 compatible = "allwinner,sun4i-a10-display-frontend"; 1113 reg = <0x01e00000 0x20000>; 1114 interrupts = <47>; 1115 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, 1116 <&ccu CLK_DRAM_DE_FE0>; 1117 clock-names = "ahb", "mod", 1118 "ram"; 1119 resets = <&ccu RST_DE_FE0>; 1120 1121 ports { 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 1125 fe0_out: port@1 { 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 reg = <1>; 1129 1130 fe0_out_be0: endpoint@0 { 1131 reg = <0>; 1132 remote-endpoint = <&be0_in_fe0>; 1133 }; 1134 1135 fe0_out_be1: endpoint@1 { 1136 reg = <1>; 1137 remote-endpoint = <&be1_in_fe0>; 1138 }; 1139 }; 1140 }; 1141 }; 1142 1143 fe1: display-frontend@1e20000 { 1144 compatible = "allwinner,sun4i-a10-display-frontend"; 1145 reg = <0x01e20000 0x20000>; 1146 interrupts = <48>; 1147 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, 1148 <&ccu CLK_DRAM_DE_FE1>; 1149 clock-names = "ahb", "mod", 1150 "ram"; 1151 resets = <&ccu RST_DE_FE1>; 1152 1153 ports { 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 1157 fe1_out: port@1 { 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 reg = <1>; 1161 1162 fe1_out_be0: endpoint@0 { 1163 reg = <0>; 1164 remote-endpoint = <&be0_in_fe1>; 1165 }; 1166 1167 fe1_out_be1: endpoint@1 { 1168 reg = <1>; 1169 remote-endpoint = <&be1_in_fe1>; 1170 }; 1171 }; 1172 }; 1173 }; 1174 1175 be1: display-backend@1e40000 { 1176 compatible = "allwinner,sun4i-a10-display-backend"; 1177 reg = <0x01e40000 0x10000>; 1178 interrupts = <48>; 1179 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, 1180 <&ccu CLK_DRAM_DE_BE1>; 1181 clock-names = "ahb", "mod", 1182 "ram"; 1183 resets = <&ccu RST_DE_BE1>; 1184 1185 ports { 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 1189 be1_in: port@0 { 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 reg = <0>; 1193 1194 be1_in_fe0: endpoint@0 { 1195 reg = <0>; 1196 remote-endpoint = <&fe0_out_be1>; 1197 }; 1198 1199 be1_in_fe1: endpoint@1 { 1200 reg = <1>; 1201 remote-endpoint = <&fe1_out_be1>; 1202 }; 1203 }; 1204 1205 be1_out: port@1 { 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 reg = <1>; 1209 1210 be1_out_tcon0: endpoint@0 { 1211 reg = <0>; 1212 remote-endpoint = <&tcon0_in_be1>; 1213 }; 1214 1215 be1_out_tcon1: endpoint@1 { 1216 reg = <1>; 1217 remote-endpoint = <&tcon1_in_be1>; 1218 }; 1219 }; 1220 }; 1221 }; 1222 1223 be0: display-backend@1e60000 { 1224 compatible = "allwinner,sun4i-a10-display-backend"; 1225 reg = <0x01e60000 0x10000>; 1226 interrupts = <47>; 1227 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 1228 <&ccu CLK_DRAM_DE_BE0>; 1229 clock-names = "ahb", "mod", 1230 "ram"; 1231 resets = <&ccu RST_DE_BE0>; 1232 1233 ports { 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 1237 be0_in: port@0 { 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 reg = <0>; 1241 1242 be0_in_fe0: endpoint@0 { 1243 reg = <0>; 1244 remote-endpoint = <&fe0_out_be0>; 1245 }; 1246 1247 be0_in_fe1: endpoint@1 { 1248 reg = <1>; 1249 remote-endpoint = <&fe1_out_be0>; 1250 }; 1251 }; 1252 1253 be0_out: port@1 { 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 reg = <1>; 1257 1258 be0_out_tcon0: endpoint@0 { 1259 reg = <0>; 1260 remote-endpoint = <&tcon0_in_be0>; 1261 }; 1262 1263 be0_out_tcon1: endpoint@1 { 1264 reg = <1>; 1265 remote-endpoint = <&tcon1_in_be0>; 1266 }; 1267 }; 1268 }; 1269 }; 1270 }; 1271}; 1272