1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Actions Semi S500 SoC 4 * 5 * Copyright (c) 2016-2017 Andreas Färber 6 */ 7 8#include <dt-bindings/clock/actions,s500-cmu.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/owl-s500-powergate.h> 12#include <dt-bindings/reset/actions,s500-reset.h> 13 14/ { 15 compatible = "actions,s500"; 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 }; 22 23 chosen { 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a9"; 33 reg = <0x0>; 34 enable-method = "actions,s500-smp"; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a9"; 40 reg = <0x1>; 41 enable-method = "actions,s500-smp"; 42 }; 43 44 cpu2: cpu@2 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a9"; 47 reg = <0x2>; 48 enable-method = "actions,s500-smp"; 49 power-domains = <&sps S500_PD_CPU2>; 50 }; 51 52 cpu3: cpu@3 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a9"; 55 reg = <0x3>; 56 enable-method = "actions,s500-smp"; 57 power-domains = <&sps S500_PD_CPU3>; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a9-pmu"; 63 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 hosc: hosc { 71 compatible = "fixed-clock"; 72 clock-frequency = <24000000>; 73 #clock-cells = <0>; 74 }; 75 76 losc: losc { 77 compatible = "fixed-clock"; 78 clock-frequency = <32768>; 79 #clock-cells = <0>; 80 }; 81 82 soc { 83 compatible = "simple-bus"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 88 scu: scu@b0020000 { 89 compatible = "arm,cortex-a9-scu"; 90 reg = <0xb0020000 0x100>; 91 }; 92 93 global_timer: timer@b0020200 { 94 compatible = "arm,cortex-a9-global-timer"; 95 reg = <0xb0020200 0x100>; 96 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 97 status = "disabled"; 98 }; 99 100 twd_timer: timer@b0020600 { 101 compatible = "arm,cortex-a9-twd-timer"; 102 reg = <0xb0020600 0x20>; 103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 104 status = "disabled"; 105 }; 106 107 twd_wdt: wdt@b0020620 { 108 compatible = "arm,cortex-a9-twd-wdt"; 109 reg = <0xb0020620 0xe0>; 110 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 111 status = "disabled"; 112 }; 113 114 gic: interrupt-controller@b0021000 { 115 compatible = "arm,cortex-a9-gic"; 116 reg = <0xb0021000 0x1000>, 117 <0xb0020100 0x0100>; 118 interrupt-controller; 119 #interrupt-cells = <3>; 120 }; 121 122 l2: cache-controller@b0022000 { 123 compatible = "arm,pl310-cache"; 124 reg = <0xb0022000 0x1000>; 125 cache-unified; 126 cache-level = <2>; 127 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 128 arm,tag-latency = <3 3 2>; 129 arm,data-latency = <5 3 3>; 130 }; 131 132 uart0: serial@b0120000 { 133 compatible = "actions,s500-uart", "actions,owl-uart"; 134 reg = <0xb0120000 0x2000>; 135 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&cmu CLK_UART0>; 137 status = "disabled"; 138 }; 139 140 uart1: serial@b0122000 { 141 compatible = "actions,s500-uart", "actions,owl-uart"; 142 reg = <0xb0122000 0x2000>; 143 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&cmu CLK_UART1>; 145 status = "disabled"; 146 }; 147 148 uart2: serial@b0124000 { 149 compatible = "actions,s500-uart", "actions,owl-uart"; 150 reg = <0xb0124000 0x2000>; 151 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&cmu CLK_UART2>; 153 status = "disabled"; 154 }; 155 156 uart3: serial@b0126000 { 157 compatible = "actions,s500-uart", "actions,owl-uart"; 158 reg = <0xb0126000 0x2000>; 159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&cmu CLK_UART3>; 161 status = "disabled"; 162 }; 163 164 uart4: serial@b0128000 { 165 compatible = "actions,s500-uart", "actions,owl-uart"; 166 reg = <0xb0128000 0x2000>; 167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&cmu CLK_UART4>; 169 status = "disabled"; 170 }; 171 172 uart5: serial@b012a000 { 173 compatible = "actions,s500-uart", "actions,owl-uart"; 174 reg = <0xb012a000 0x2000>; 175 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&cmu CLK_UART5>; 177 status = "disabled"; 178 }; 179 180 uart6: serial@b012c000 { 181 compatible = "actions,s500-uart", "actions,owl-uart"; 182 reg = <0xb012c000 0x2000>; 183 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&cmu CLK_UART6>; 185 status = "disabled"; 186 }; 187 188 cmu: clock-controller@b0160000 { 189 compatible = "actions,s500-cmu"; 190 reg = <0xb0160000 0x8000>; 191 clocks = <&hosc>, <&losc>; 192 #clock-cells = <1>; 193 #reset-cells = <1>; 194 }; 195 196 i2c0: i2c@b0170000 { 197 compatible = "actions,s500-i2c"; 198 reg = <0xb0170000 0x4000>; 199 clocks = <&cmu CLK_I2C0>; 200 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 status = "disabled"; 204 }; 205 206 i2c1: i2c@b0174000 { 207 compatible = "actions,s500-i2c"; 208 reg = <0xb0174000 0x4000>; 209 clocks = <&cmu CLK_I2C1>; 210 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 status = "disabled"; 214 }; 215 216 i2c2: i2c@b0178000 { 217 compatible = "actions,s500-i2c"; 218 reg = <0xb0178000 0x4000>; 219 clocks = <&cmu CLK_I2C2>; 220 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 status = "disabled"; 224 }; 225 226 i2c3: i2c@b017c000 { 227 compatible = "actions,s500-i2c"; 228 reg = <0xb017c000 0x4000>; 229 clocks = <&cmu CLK_I2C3>; 230 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 status = "disabled"; 234 }; 235 236 sirq: interrupt-controller@b01b0200 { 237 compatible = "actions,s500-sirq"; 238 reg = <0xb01b0200 0x4>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */ 242 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */ 243 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */ 244 }; 245 246 timer: timer@b0168000 { 247 compatible = "actions,s500-timer"; 248 reg = <0xb0168000 0x8000>; 249 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; 254 }; 255 256 sps: power-controller@b01b0100 { 257 compatible = "actions,s500-sps"; 258 reg = <0xb01b0100 0x100>; 259 #power-domain-cells = <1>; 260 }; 261 262 pinctrl: pinctrl@b01b0000 { 263 compatible = "actions,s500-pinctrl"; 264 reg = <0xb01b0000 0x40>, /* GPIO */ 265 <0xb01b0040 0x10>, /* Multiplexing Control */ 266 <0xb01b0060 0x18>, /* PAD Control */ 267 <0xb01b0080 0xc>; /* PAD Drive Capacity */ 268 clocks = <&cmu CLK_GPIO>; 269 gpio-controller; 270 gpio-ranges = <&pinctrl 0 0 132>; 271 #gpio-cells = <2>; 272 interrupt-controller; 273 #interrupt-cells = <2>; 274 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* GPIOA */ 275 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* GPIOB */ 276 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* GPIOC */ 277 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, /* GPIOD */ 278 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /* GPIOE */ 279 }; 280 281 dma: dma-controller@b0260000 { 282 compatible = "actions,s500-dma"; 283 reg = <0xb0260000 0xd00>; 284 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 288 #dma-cells = <1>; 289 dma-channels = <12>; 290 dma-requests = <46>; 291 clocks = <&cmu CLK_DMAC>; 292 power-domains = <&sps S500_PD_DMA>; 293 }; 294 295 mmc0: mmc@b0230000 { 296 compatible = "actions,s500-mmc", "actions,owl-mmc"; 297 reg = <0xb0230000 0x38>; 298 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&cmu CLK_SD0>; 300 resets = <&cmu RESET_SD0>; 301 dmas = <&dma 2>; 302 dma-names = "mmc"; 303 status = "disabled"; 304 }; 305 306 mmc1: mmc@b0234000 { 307 compatible = "actions,s500-mmc", "actions,owl-mmc"; 308 reg = <0xb0234000 0x38>; 309 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cmu CLK_SD1>; 311 resets = <&cmu RESET_SD1>; 312 dmas = <&dma 3>; 313 dma-names = "mmc"; 314 status = "disabled"; 315 }; 316 317 mmc2: mmc@b0238000 { 318 compatible = "actions,s500-mmc", "actions,owl-mmc"; 319 reg = <0xb0238000 0x38>; 320 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cmu CLK_SD2>; 322 resets = <&cmu RESET_SD2>; 323 dmas = <&dma 4>; 324 dma-names = "mmc"; 325 status = "disabled"; 326 }; 327 328 ethernet: ethernet@b0310000 { 329 compatible = "actions,s500-emac", "actions,owl-emac"; 330 reg = <0xb0310000 0x10000>; 331 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>; 333 clock-names = "eth", "rmii"; 334 resets = <&cmu RESET_ETHERNET>; 335 status = "disabled"; 336 }; 337 }; 338}; 339