1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright(c) 2015 EZchip Technologies. 4 */ 5 6/dts-v1/; 7 8/ { 9 compatible = "ezchip,arc-nps"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&intc>; 13 present-cpus = "0-1,16-17"; 14 possible-cpus = "0-4095"; 15 16 aliases { 17 ethernet0 = &gmac0; 18 }; 19 20 chosen { 21 bootargs = "earlycon=uart8250,mmio32be,0xf7209000,115200n8 console=ttyS0,115200n8"; 22 }; 23 24 memory { 25 device_type = "memory"; 26 reg = <0x80000000 0x20000000>; /* 512M */ 27 }; 28 29 clocks { 30 sysclk: sysclk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <83333333>; 34 }; 35 }; 36 37 soc { 38 compatible = "simple-bus"; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 42 /* child and parent address space 1:1 mapped */ 43 ranges; 44 45 intc: interrupt-controller { 46 compatible = "ezchip,nps400-ic"; 47 interrupt-controller; 48 #interrupt-cells = <1>; 49 }; 50 51 timer0: timer_clkevt { 52 compatible = "snps,arc-timer"; 53 interrupts = <3>; 54 clocks = <&sysclk>; 55 }; 56 57 timer1: timer_clksrc { 58 compatible = "ezchip,nps400-timer"; 59 clocks = <&sysclk>; 60 clock-names="sysclk"; 61 }; 62 63 uart@f7209000 { 64 compatible = "snps,dw-apb-uart"; 65 device_type = "serial"; 66 reg = <0xf7209000 0x100>; 67 interrupts = <6>; 68 clocks = <&sysclk>; 69 clock-names="baudclk"; 70 baud = <115200>; 71 reg-shift = <2>; 72 reg-io-width = <4>; 73 native-endian; 74 }; 75 76 gmac0: ethernet@f7470000 { 77 compatible = "ezchip,nps-mgt-enet"; 78 reg = <0xf7470000 0x1940>; 79 interrupts = <7>; 80 /* Filled in by U-Boot */ 81 mac-address = [ 00 C0 00 F0 04 03 ]; 82 }; 83 }; 84}; 85