1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #ifndef __MEDIATEK_LVTS_DT_H 8 #define __MEDIATEK_LVTS_DT_H 9 10 #define MT7988_CPU_0 0 11 #define MT7988_CPU_1 1 12 #define MT7988_ETH2P5G_0 2 13 #define MT7988_ETH2P5G_1 3 14 #define MT7988_TOPS_0 4 15 #define MT7988_TOPS_1 5 16 #define MT7988_ETHWARP_0 6 17 #define MT7988_ETHWARP_1 7 18 19 #define MT8195_MCU_BIG_CPU0 0 20 #define MT8195_MCU_BIG_CPU1 1 21 #define MT8195_MCU_BIG_CPU2 2 22 #define MT8195_MCU_BIG_CPU3 3 23 #define MT8195_MCU_LITTLE_CPU0 4 24 #define MT8195_MCU_LITTLE_CPU1 5 25 #define MT8195_MCU_LITTLE_CPU2 6 26 #define MT8195_MCU_LITTLE_CPU3 7 27 28 #define MT8195_AP_VPU0 8 29 #define MT8195_AP_VPU1 9 30 #define MT8195_AP_GPU0 10 31 #define MT8195_AP_GPU1 11 32 #define MT8195_AP_VDEC 12 33 #define MT8195_AP_IMG 13 34 #define MT8195_AP_INFRA 14 35 #define MT8195_AP_CAM0 15 36 #define MT8195_AP_CAM1 16 37 38 #define MT8192_MCU_BIG_CPU0 0 39 #define MT8192_MCU_BIG_CPU1 1 40 #define MT8192_MCU_BIG_CPU2 2 41 #define MT8192_MCU_BIG_CPU3 3 42 #define MT8192_MCU_LITTLE_CPU0 4 43 #define MT8192_MCU_LITTLE_CPU1 5 44 #define MT8192_MCU_LITTLE_CPU2 6 45 #define MT8192_MCU_LITTLE_CPU3 7 46 47 #define MT8192_AP_VPU0 8 48 #define MT8192_AP_VPU1 9 49 #define MT8192_AP_GPU0 10 50 #define MT8192_AP_GPU1 11 51 #define MT8192_AP_INFRA 12 52 #define MT8192_AP_CAM 13 53 #define MT8192_AP_MD0 14 54 #define MT8192_AP_MD1 15 55 #define MT8192_AP_MD2 16 56 57 #endif /* __MEDIATEK_LVTS_DT_H */ 58