16be33864SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*c9ccf3a3SEmmanuel Vadot /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 36be33864SEmmanuel Vadot 46be33864SEmmanuel Vadot #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H 56be33864SEmmanuel Vadot #define DT_BINDINGS_RESET_TEGRA234_RESET_H 66be33864SEmmanuel Vadot 7e67e8565SEmmanuel Vadot /** 8e67e8565SEmmanuel Vadot * @file 9e67e8565SEmmanuel Vadot * @defgroup bpmp_reset_ids Reset ID's 10e67e8565SEmmanuel Vadot * @brief Identifiers for Resets controllable by firmware 11e67e8565SEmmanuel Vadot * @{ 12e67e8565SEmmanuel Vadot */ 13*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX1_CORE_6 11U 14*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX1_CORE_6_APB 12U 15*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX1_COMMON_APB 13U 16*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_7 14U 17*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_7_APB 15U 18*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_HDA 20U 19*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_HDACODEC 21U 20*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C1 24U 21*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_8 25U 22*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_8_APB 26U 23*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_9 27U 24*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_9_APB 28U 25*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C2 29U 26*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C3 30U 27*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C4 31U 28*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C6 32U 29*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C7 33U 30*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C8 34U 31*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_I2C9 35U 32*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_10 56U 33*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_CORE_10_APB 57U 34*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX2_COMMON_APB 58U 35*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM1 68U 36*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM2 69U 37*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM3 70U 38*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM4 71U 39*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM5 72U 40*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM6 73U 41*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM7 74U 42*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PWM8 75U 43e67e8565SEmmanuel Vadot #define TEGRA234_RESET_SDMMC4 85U 44e67e8565SEmmanuel Vadot #define TEGRA234_RESET_UARTA 100U 45*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_0 116U 46*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_1 117U 47*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_2 118U 48*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_3 119U 49*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_4 120U 50*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_0_APB 121U 51*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_1_APB 122U 52*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_2_APB 123U 53*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_3_APB 124U 54*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_CORE_4_APB 125U 55*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX0_COMMON_APB 126U 56*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX1_CORE_5 129U 57*c9ccf3a3SEmmanuel Vadot #define TEGRA234_RESET_PEX1_CORE_5_APB 130U 58e67e8565SEmmanuel Vadot 59e67e8565SEmmanuel Vadot /** @} */ 606be33864SEmmanuel Vadot 616be33864SEmmanuel Vadot #endif 62