1*8d13bc63SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2*8d13bc63SEmmanuel Vadot /* 3*8d13bc63SEmmanuel Vadot * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4*8d13bc63SEmmanuel Vadot * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> 5*8d13bc63SEmmanuel Vadot */ 6*8d13bc63SEmmanuel Vadot 7*8d13bc63SEmmanuel Vadot #ifndef _DT_BINDINGS_STM32MP25_RESET_H_ 8*8d13bc63SEmmanuel Vadot #define _DT_BINDINGS_STM32MP25_RESET_H_ 9*8d13bc63SEmmanuel Vadot 10*8d13bc63SEmmanuel Vadot #define TIM1_R 0 11*8d13bc63SEmmanuel Vadot #define TIM2_R 1 12*8d13bc63SEmmanuel Vadot #define TIM3_R 2 13*8d13bc63SEmmanuel Vadot #define TIM4_R 3 14*8d13bc63SEmmanuel Vadot #define TIM5_R 4 15*8d13bc63SEmmanuel Vadot #define TIM6_R 5 16*8d13bc63SEmmanuel Vadot #define TIM7_R 6 17*8d13bc63SEmmanuel Vadot #define TIM8_R 7 18*8d13bc63SEmmanuel Vadot #define TIM10_R 8 19*8d13bc63SEmmanuel Vadot #define TIM11_R 9 20*8d13bc63SEmmanuel Vadot #define TIM12_R 10 21*8d13bc63SEmmanuel Vadot #define TIM13_R 11 22*8d13bc63SEmmanuel Vadot #define TIM14_R 12 23*8d13bc63SEmmanuel Vadot #define TIM15_R 13 24*8d13bc63SEmmanuel Vadot #define TIM16_R 14 25*8d13bc63SEmmanuel Vadot #define TIM17_R 15 26*8d13bc63SEmmanuel Vadot #define TIM20_R 16 27*8d13bc63SEmmanuel Vadot #define LPTIM1_R 17 28*8d13bc63SEmmanuel Vadot #define LPTIM2_R 18 29*8d13bc63SEmmanuel Vadot #define LPTIM3_R 19 30*8d13bc63SEmmanuel Vadot #define LPTIM4_R 20 31*8d13bc63SEmmanuel Vadot #define LPTIM5_R 21 32*8d13bc63SEmmanuel Vadot #define SPI1_R 22 33*8d13bc63SEmmanuel Vadot #define SPI2_R 23 34*8d13bc63SEmmanuel Vadot #define SPI3_R 24 35*8d13bc63SEmmanuel Vadot #define SPI4_R 25 36*8d13bc63SEmmanuel Vadot #define SPI5_R 26 37*8d13bc63SEmmanuel Vadot #define SPI6_R 27 38*8d13bc63SEmmanuel Vadot #define SPI7_R 28 39*8d13bc63SEmmanuel Vadot #define SPI8_R 29 40*8d13bc63SEmmanuel Vadot #define SPDIFRX_R 30 41*8d13bc63SEmmanuel Vadot #define USART1_R 31 42*8d13bc63SEmmanuel Vadot #define USART2_R 32 43*8d13bc63SEmmanuel Vadot #define USART3_R 33 44*8d13bc63SEmmanuel Vadot #define UART4_R 34 45*8d13bc63SEmmanuel Vadot #define UART5_R 35 46*8d13bc63SEmmanuel Vadot #define USART6_R 36 47*8d13bc63SEmmanuel Vadot #define UART7_R 37 48*8d13bc63SEmmanuel Vadot #define UART8_R 38 49*8d13bc63SEmmanuel Vadot #define UART9_R 39 50*8d13bc63SEmmanuel Vadot #define LPUART1_R 40 51*8d13bc63SEmmanuel Vadot #define IS2M_R 41 52*8d13bc63SEmmanuel Vadot #define I2C1_R 42 53*8d13bc63SEmmanuel Vadot #define I2C2_R 43 54*8d13bc63SEmmanuel Vadot #define I2C3_R 44 55*8d13bc63SEmmanuel Vadot #define I2C4_R 45 56*8d13bc63SEmmanuel Vadot #define I2C5_R 46 57*8d13bc63SEmmanuel Vadot #define I2C6_R 47 58*8d13bc63SEmmanuel Vadot #define I2C7_R 48 59*8d13bc63SEmmanuel Vadot #define I2C8_R 49 60*8d13bc63SEmmanuel Vadot #define SAI1_R 50 61*8d13bc63SEmmanuel Vadot #define SAI2_R 51 62*8d13bc63SEmmanuel Vadot #define SAI3_R 52 63*8d13bc63SEmmanuel Vadot #define SAI4_R 53 64*8d13bc63SEmmanuel Vadot #define MDF1_R 54 65*8d13bc63SEmmanuel Vadot #define MDF2_R 55 66*8d13bc63SEmmanuel Vadot #define FDCAN_R 56 67*8d13bc63SEmmanuel Vadot #define HDP_R 57 68*8d13bc63SEmmanuel Vadot #define ADC12_R 58 69*8d13bc63SEmmanuel Vadot #define ADC3_R 59 70*8d13bc63SEmmanuel Vadot #define ETH1_R 60 71*8d13bc63SEmmanuel Vadot #define ETH2_R 61 72*8d13bc63SEmmanuel Vadot #define USB2_R 62 73*8d13bc63SEmmanuel Vadot #define USB2PHY1_R 63 74*8d13bc63SEmmanuel Vadot #define USB2PHY2_R 64 75*8d13bc63SEmmanuel Vadot #define USB3DR_R 65 76*8d13bc63SEmmanuel Vadot #define USB3PCIEPHY_R 66 77*8d13bc63SEmmanuel Vadot #define USBTC_R 67 78*8d13bc63SEmmanuel Vadot #define ETHSW_R 68 79*8d13bc63SEmmanuel Vadot #define SDMMC1_R 69 80*8d13bc63SEmmanuel Vadot #define SDMMC1DLL_R 70 81*8d13bc63SEmmanuel Vadot #define SDMMC2_R 71 82*8d13bc63SEmmanuel Vadot #define SDMMC2DLL_R 72 83*8d13bc63SEmmanuel Vadot #define SDMMC3_R 73 84*8d13bc63SEmmanuel Vadot #define SDMMC3DLL_R 74 85*8d13bc63SEmmanuel Vadot #define GPU_R 75 86*8d13bc63SEmmanuel Vadot #define LTDC_R 76 87*8d13bc63SEmmanuel Vadot #define DSI_R 77 88*8d13bc63SEmmanuel Vadot #define LVDS_R 78 89*8d13bc63SEmmanuel Vadot #define CSI_R 79 90*8d13bc63SEmmanuel Vadot #define DCMIPP_R 80 91*8d13bc63SEmmanuel Vadot #define CCI_R 81 92*8d13bc63SEmmanuel Vadot #define VDEC_R 82 93*8d13bc63SEmmanuel Vadot #define VENC_R 83 94*8d13bc63SEmmanuel Vadot #define WWDG1_R 84 95*8d13bc63SEmmanuel Vadot #define WWDG2_R 85 96*8d13bc63SEmmanuel Vadot #define VREF_R 86 97*8d13bc63SEmmanuel Vadot #define DTS_R 87 98*8d13bc63SEmmanuel Vadot #define CRC_R 88 99*8d13bc63SEmmanuel Vadot #define SERC_R 89 100*8d13bc63SEmmanuel Vadot #define OSPIIOM_R 90 101*8d13bc63SEmmanuel Vadot #define I3C1_R 91 102*8d13bc63SEmmanuel Vadot #define I3C2_R 92 103*8d13bc63SEmmanuel Vadot #define I3C3_R 93 104*8d13bc63SEmmanuel Vadot #define I3C4_R 94 105*8d13bc63SEmmanuel Vadot #define IWDG2_KER_R 95 106*8d13bc63SEmmanuel Vadot #define IWDG4_KER_R 96 107*8d13bc63SEmmanuel Vadot #define RNG_R 97 108*8d13bc63SEmmanuel Vadot #define PKA_R 98 109*8d13bc63SEmmanuel Vadot #define SAES_R 99 110*8d13bc63SEmmanuel Vadot #define HASH_R 100 111*8d13bc63SEmmanuel Vadot #define CRYP1_R 101 112*8d13bc63SEmmanuel Vadot #define CRYP2_R 102 113*8d13bc63SEmmanuel Vadot #define PCIE_R 103 114*8d13bc63SEmmanuel Vadot #define OSPI1_R 104 115*8d13bc63SEmmanuel Vadot #define OSPI1DLL_R 105 116*8d13bc63SEmmanuel Vadot #define OSPI2_R 106 117*8d13bc63SEmmanuel Vadot #define OSPI2DLL_R 107 118*8d13bc63SEmmanuel Vadot #define FMC_R 108 119*8d13bc63SEmmanuel Vadot #define DBG_R 109 120*8d13bc63SEmmanuel Vadot #define GPIOA_R 110 121*8d13bc63SEmmanuel Vadot #define GPIOB_R 111 122*8d13bc63SEmmanuel Vadot #define GPIOC_R 112 123*8d13bc63SEmmanuel Vadot #define GPIOD_R 113 124*8d13bc63SEmmanuel Vadot #define GPIOE_R 114 125*8d13bc63SEmmanuel Vadot #define GPIOF_R 115 126*8d13bc63SEmmanuel Vadot #define GPIOG_R 116 127*8d13bc63SEmmanuel Vadot #define GPIOH_R 117 128*8d13bc63SEmmanuel Vadot #define GPIOI_R 118 129*8d13bc63SEmmanuel Vadot #define GPIOJ_R 119 130*8d13bc63SEmmanuel Vadot #define GPIOK_R 120 131*8d13bc63SEmmanuel Vadot #define GPIOZ_R 121 132*8d13bc63SEmmanuel Vadot #define HPDMA1_R 122 133*8d13bc63SEmmanuel Vadot #define HPDMA2_R 123 134*8d13bc63SEmmanuel Vadot #define HPDMA3_R 124 135*8d13bc63SEmmanuel Vadot #define LPDMA_R 125 136*8d13bc63SEmmanuel Vadot #define HSEM_R 126 137*8d13bc63SEmmanuel Vadot #define IPCC1_R 127 138*8d13bc63SEmmanuel Vadot #define IPCC2_R 128 139*8d13bc63SEmmanuel Vadot #define C2_HOLDBOOT_R 129 140*8d13bc63SEmmanuel Vadot #define C1_HOLDBOOT_R 130 141*8d13bc63SEmmanuel Vadot #define C1_R 131 142*8d13bc63SEmmanuel Vadot #define C1P1POR_R 132 143*8d13bc63SEmmanuel Vadot #define C1P1_R 133 144*8d13bc63SEmmanuel Vadot #define C2_R 134 145*8d13bc63SEmmanuel Vadot #define C3_R 135 146*8d13bc63SEmmanuel Vadot #define SYS_R 136 147*8d13bc63SEmmanuel Vadot #define VSW_R 137 148*8d13bc63SEmmanuel Vadot #define C1MS_R 138 149*8d13bc63SEmmanuel Vadot #define DDRCP_R 139 150*8d13bc63SEmmanuel Vadot #define DDRCAPB_R 140 151*8d13bc63SEmmanuel Vadot #define DDRPHYCAPB_R 141 152*8d13bc63SEmmanuel Vadot #define DDRCFG_R 142 153*8d13bc63SEmmanuel Vadot #define DDR_R 143 154*8d13bc63SEmmanuel Vadot 155*8d13bc63SEmmanuel Vadot #define STM32MP25_LAST_RESET 144 156*8d13bc63SEmmanuel Vadot 157*8d13bc63SEmmanuel Vadot #define RST_SCMI_C1_R 0 158*8d13bc63SEmmanuel Vadot #define RST_SCMI_C2_R 1 159*8d13bc63SEmmanuel Vadot #define RST_SCMI_C1_HOLDBOOT_R 2 160*8d13bc63SEmmanuel Vadot #define RST_SCMI_C2_HOLDBOOT_R 3 161*8d13bc63SEmmanuel Vadot #define RST_SCMI_FMC 4 162*8d13bc63SEmmanuel Vadot #define RST_SCMI_OSPI1 5 163*8d13bc63SEmmanuel Vadot #define RST_SCMI_OSPI1DLL 6 164*8d13bc63SEmmanuel Vadot #define RST_SCMI_OSPI2 7 165*8d13bc63SEmmanuel Vadot #define RST_SCMI_OSPI2DLL 8 166*8d13bc63SEmmanuel Vadot 167*8d13bc63SEmmanuel Vadot #endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */ 168