1*8cc087a1SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*8cc087a1SEmmanuel Vadot /* 3*8cc087a1SEmmanuel Vadot * Copyright (c) 2019 MediaTek Inc. 4*8cc087a1SEmmanuel Vadot * Author: Yong Liang <yong.liang@mediatek.com> 5*8cc087a1SEmmanuel Vadot */ 6*8cc087a1SEmmanuel Vadot 7*8cc087a1SEmmanuel Vadot #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 8*8cc087a1SEmmanuel Vadot #define _DT_BINDINGS_RESET_CONTROLLER_MT2712 9*8cc087a1SEmmanuel Vadot 10*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_INFRA_SW_RST 0 11*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_MM_SW_RST 1 12*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_MFG_SW_RST 2 13*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_VENC_SW_RST 3 14*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_VDEC_SW_RST 4 15*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_IMG_SW_RST 5 16*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_INFRA_AO_SW_RST 8 17*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_USB_SW_RST 9 18*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_APMIXED_SW_RST 10 19*8cc087a1SEmmanuel Vadot 20*8cc087a1SEmmanuel Vadot #define MT2712_TOPRGU_SW_RST_NUM 11 21*8cc087a1SEmmanuel Vadot 22*8cc087a1SEmmanuel Vadot #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ 23